Module ruspiro_register::system::aarch64::clidr_el1

This is supported on AArch64 only.

CLIDR_EL1 - Cache Level ID Register

This is a read-only register

Usage Constraints

EL0	EL1 (NS)	EL1(S)	EL2	EL3(NS)	EL3(S)
-	R	R	R	R	R

Modules

CTYPE1	AArch64 Type of cache implemented at L1
CTYPE2	AArch64 Type of cache implemented at L2
CTYPE3	AArch64 Type of cache implemented at L3
ICB	AArch64 Inner cache boundary
LOC	AArch64 Level of Coherency for cache hierarchy
LOUIS	AArch64 Level of Unification inner sharable for cache hierarchy
LOUU	AArch64 Level of Unification Uniprocessor for cache hierarchy

Functions

get	AArch64 Read the raw register contents using the appropriate assembly
read	AArch64 Read the contents of a specific RegisterField. The returned value is already shifted to the right to start at bit 0. This means for a field value stored in the register at bit offset 3, the returned value is already shifted by 3 bits to the right. For example: If register raw value is 0b10110, the returned value for a register field specified as bits[4:3] would be 0b01. No further "masking" or "bit-shift" required
set	AArch64 Write the raw register contents using the appropriate contents
write	AArch64 Update the contents of a register from the RegisterFieldValue given. This will only change the bits the RegisterField definition specifies.