Module ruspiro_mmu::TTLB_BLOCKPAGE [−][src]
TTLB Block and Page Entry format
| Table entry type - Bits | [63 : 52] | [51 : 48] | [47 : 30] | [29 : 12] | [11 : 2] | [1 : 0] |
|---|---|---|---|---|---|---|
| Block entry | Block attributes | RES0 | Output address [47..30] | RES0 | Block attr. | 0 1 |
| Page entry | Page Attributes | RES0 | Output address [47..12] | Page attr. | 1 1 |
Modules
| ADDR | Output address - bits [47:12] are used if this is a page entry. Output address - bits [47:30] are used if this is a block entry. |
| AF | Access Flag bit |
| AP | |
| C | Contigues hint bit indicating that this table entry is one of a contigues sets of entries and might be cached together with the other ones |
| MEMATTR | Stage 1 memory attributes - index into MAIR_ELx register |
| NG | not Global bit determines whether this entry is globally valid or only for the current ASID value. This bit is only valid in EL1 & EL0 |
| NS | Non-Secure bit specifies whether the output address is in secure or non-secure address map. |
| PXN | Priviliged eXecute Never bit determines whether the memory region is executable in EL1. In EL2/EL3 this bit is RES0 |
| SH | Shareability flag |
| TYPE | |
| XN | eXecute Never bit determining whether the memory region is executable or not. |