Module ruspiro_arch_aarch64::register::el2::tcr_el2 [−][src]
Expand description
TCR_EL2 - Translation Control Register EL2
Controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.
Usage Constraints
| EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
|---|---|---|---|---|---|
| - | - | - | R/W | R/W | R/W |
Modules
Inner cacheability attribute for memory associated with tlb walks using ttbr0_el2
Outer cacheability attribute for memory associated with tlb walks using ttbr0_el2
Physical address size
Shareability attribute for memory associated with tlb walks using ttbr0_el2
Size offset of the memory reagion addressed by ttbr0_el2 (size = 2^(64-t0sz))
Top Byte Ignored
Granule size for the ttbr0_el2
Functions
Read the raw register contents using the appropriate assembly
Read the contents of a specific RegisterField. The returned value is already shifted
to the right to start at bit 0. This means for a field value stored in the register at
bit offset 3, the returned value is already shifted by 3 bits to the right.
For example:
If register raw value is 0b10110, the returned value for a register field specified as
bits[4:3] would be 0b01. No further “masking” or “bit-shift” required
Write the raw register contents using the appropriate contents
Update the contents of a register from the RegisterFieldValue given. This will
only change the bits the RegisterField definition specifies.