1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
/***********************************************************************************************************************
* Copyright (c) 2020 by the authors
*
* Author: André Borrmann <pspwizard@gmx.de>
* License: Apache License 2.0 / MIT
**********************************************************************************************************************/
//! # MAIR_EL2 - Memory Attribute Indirection Register EL2
//!
//! Provides the memory attribute encodings corresponding to the possible AttrIndx values in a
//! Long-descriptor format translation table entry for stage 1 translations at EL2.
//!
//! ## Usage Constraints
//! EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S)
//! ----|----------|--------|-----|---------|-------
//! - | - | - | R/W | R/W | R/W
//!
use crate::register::*;
use crate::{define_aarch64_register, impl_system_register_rw};
define_aarch64_register! {
@mair_el2<u64> {
MAIR0 OFFSET(0) BITS(8) [
NGNRNE = 0x00,
NGNRE = 0x04,
GRE = 0x0C,
NC = 0x44,
NORM = 0xFF
],
MAIR1 OFFSET(8) BITS(8) [
NGNRNE = 0x00,
NGNRE = 0x04,
GRE = 0x0C,
NC = 0x44,
NORM = 0xFF
],
MAIR2 OFFSET(16) BITS(8) [
NGNRNE = 0x00,
NGNRE = 0x04,
GRE = 0x0C,
NC = 0x44,
NORM = 0xFF
],
MAIR3 OFFSET(24) BITS(8) [
NGNRNE = 0x00,
NGNRE = 0x04,
GRE = 0x0C,
NC = 0x44,
NORM = 0xFF
],
MAIR4 OFFSET(32) BITS(8) [
NGNRNE = 0x00,
NGNRE = 0x04,
GRE = 0x0C,
NC = 0x44,
NORM = 0xFF
]
}
}