Module ruspiro_arch_aarch64::register::el1::mpidr_el1 [−][src]
Expand description
MPIDR_EL1 - Multiprocessor Affinity Register
Provides an additional core identification mechanism for scheduling purposes in a cluster system. This is a read-only register.
Usage Constraints
EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
---|---|---|---|---|---|
- | R | R | R | R | R |
Modules
Affinity level 0, indicates the core number in a processor
Affinity level 1
Affinity level 2
Affinity level 3
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multithreading type approach
Indicates a single core system, as distinct from core 0 in a cluster.
Functions
Read the raw register contents using the appropriate assembly
Read the contents of a specific RegisterField
. The returned value is already shifted
to the right to start at bit 0. This means for a field value stored in the register at
bit offset 3, the returned value is already shifted by 3 bits to the right.
For example:
If register raw value is 0b10110, the returned value for a register field specified as
bits[4:3] would be 0b01. No further “masking” or “bit-shift” required
Write the raw register contents using the appropriate contents
Update the contents of a register from the RegisterFieldValue
given. This will
only change the bits the RegisterField
definition specifies.