Module ruspiro_arch_aarch64::register::el1::sctlr_el1 [−][src]
Expand description
SCTLR_EL1 - System Control Register EL1
Provides top level control of the system, including its memory system at EL1.
Usage Constraints
| EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
|---|---|---|---|---|---|
| - | R/W | R/W | R/W | R/W | R/W |
Modules
alignment fault check
global data cache
CP15 barrier operations enabled ?
Enables access to the DC ZVA instruction at EL0
explicit data access endiannes at EL0
exception endiannes
instruction cache
IT instructions disabled ?
globally enable MMU
Non-trapping WFE instruction
Non-trapping WFI instruction
stack alignment checks
El0 stack alignment checks
SETEND instructions disabled ?
Enable EL0 access to cache maintenance instructions: DC CVAU, DC CIVAC, DC CVAC and IC IVAU in Aarch64 mode
Enables EL0 access to the CTR_EL0 register in Aacrh64 mode
Controls access to interrupt masks from EL0 if EL0 is using Aarch64
Force all memory regions with write permissions as XN
Functions
Read the raw register contents using the appropriate assembly
Read the contents of a specific RegisterField. The returned value is already shifted
to the right to start at bit 0. This means for a field value stored in the register at
bit offset 3, the returned value is already shifted by 3 bits to the right.
For example:
If register raw value is 0b10110, the returned value for a register field specified as
bits[4:3] would be 0b01. No further “masking” or “bit-shift” required
Write the raw register contents using the appropriate contents
Update the contents of a register from the RegisterFieldValue given. This will
only change the bits the RegisterField definition specifies.