Module ruspiro_arch_aarch64::register::el1::clidr_el1 [−][src]
Expand description
CLIDR_EL1 - Cache Level ID Register
This is a read-only register
Usage Constraints
| EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
|---|---|---|---|---|---|
| - | R | R | R | R | R |
Modules
Type of cache implemented at L1
Type of cache implemented at L2
Type of cache implemented at L3
Inner cache boundary
Level of Coherency for cache hierarchy
Level of Unification inner sharable for cache hierarchy
Level of Unification Uniprocessor for cache hierarchy
Functions
Read the raw register contents using the appropriate assembly
Read the contents of a specific RegisterField. The returned value is already shifted
to the right to start at bit 0. This means for a field value stored in the register at
bit offset 3, the returned value is already shifted by 3 bits to the right.
For example:
If register raw value is 0b10110, the returned value for a register field specified as
bits[4:3] would be 0b01. No further “masking” or “bit-shift” required
Write the raw register contents using the appropriate contents
Update the contents of a register from the RegisterFieldValue given. This will
only change the bits the RegisterField definition specifies.