Module ruspiro_arch_aarch64::register::el0::ctr_el0 [−][src]
Expand description
TCR_EL1 - Translation Control Register EL1
Determines which Translation Base Registers defines the base address register for a translation table walk required for stage 1 translation of a memory access from EL0 or EL1 and holds cacheability and shareability information.
Usage Constraints
| EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
|---|---|---|---|---|---|
| R/W | R/W | R/W | R/W | R/W | R/W |
Modules
Cache writeback granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified.
Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE.
Exclusives reservation granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions.
Data cache clean requirements for instruction to data coherence.
Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE
Level 1 instruction cache policy. Indicates the indexing and tagging policy for the L1 instruction cache
Functions
Read the raw register contents using the appropriate assembly
Read the contents of a specific RegisterField. The returned value is already shifted
to the right to start at bit 0. This means for a field value stored in the register at
bit offset 3, the returned value is already shifted by 3 bits to the right.
For example:
If register raw value is 0b10110, the returned value for a register field specified as
bits[4:3] would be 0b01. No further “masking” or “bit-shift” required
Write the raw register contents using the appropriate contents
Update the contents of a register from the RegisterFieldValue given. This will
only change the bits the RegisterField definition specifies.