Module ruspiro_arch_aarch64::register::el2::ttbr0_el2 [−][src]
TTBR0_EL2 - Translation Table Base Register 0 EL2
Holds the base address of translation table 0, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses from EL2 or HYP mode
Usage Constraints
EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
---|---|---|---|---|---|
- | - | - | R/W | R/W | R/W |
Modules
ASID | An ASID for the translation table base address. |
BADDR | Translation table base address bits[47:x]. x is based on the value of |
Functions
get | Read the raw register contents using the appropriate assembly |
read | Read the contents of a specific |
set | Write the raw register contents using the appropriate contents |
write | Update the contents of a register from the |