[−][src]Module ruspiro_arch_aarch64::register::el2::hcr_el2
HCR_EL2 - Hypervisor Configuration Register
Provides configuration control for virtualization, including whether various Non-secure operations are trapped to EL2.
Usage Constraints
| EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
|---|---|---|---|---|---|
| - | - | - | R/W | R/W | R/W |
Modules
| AMO | Async Abort and Error exception routing to EL2 |
| BSU | Barrier sharability upgrade |
| CD | disable stage 2 data cache |
| DC | default cacheable |
| FB | Forces broadcast |
| FMO | physical FIQ routing to EL2 |
| ID | disable stage 2 instruction cache |
| IMO | phyiscal IRQ routing to EL2 |
| PTW | |
| RW | register width control for lower exception levels |
| TACR | trap auxiliry control registers |
| TDZ | trap dc zva instruction |
| TGE | trap generel exceptions |
| TID0 | trap ID group 0 registers |
| TID1 | trap ID group 1 registers |
| TID2 | trap ID group 2 registers |
| TID3 | trap ID group 3 registers |
| TIDCP | trap implementation depended instructions |
| TPC | trap data or unified cache maintenance instructions to Point of Coherency |
| TPU | trap data or nuified cache maintenance instructions to Point of Unification |
| TRVM | trap reads of virtual memory controls |
| TSC | trap SMC instruction |
| TSW | trap data or unified cache maintenenace instructions by set or way |
| TTLB | trap ttlb maintenance instructions |
| TVM | trap virtual memory control |
| TWE | trap WFE if there is no pending WFE event |
| TWI | trap WFI if there is no pending WFI event |
| VF | virtual FIQ pending |
| VI | virtual IRQ pending |
| VM | enable second stage of translation |
| VSE | virtual system error/async abort pending |
Functions
| get | Read the raw register contents using the appropriate assembly |
| read | Read the contents of a specific |
| set | Write the raw register contents using the appropriate contents |
| write | Update the contents of a register from the |