Module ruspiro_arch_aarch64::register::el1::ccsidr_el1

CCSIDR_EL1 - Cache Size ID Register

This is a read-only register

Usage Constraints

EL0	EL1 (NS)	EL1(S)	EL2	EL3(NS)	EL3(S)
-	R	R	R	R	R

Modules

ASSOC	Indicates the associativity of the cache - 1. A value of 0 indicates an associativity of
LINESIZE	Indicates the (log2(number of words in cache line)) - 2
NUMSETS	Indicates the number of sets in cache - 1. A value of 0 indeicates 1 set in the cache. It does not need to be a power of 2.
RA	Indicates support for reas-allocation
WA	Indicates support for write-allocation
WB	Indicates support for write-back
WT	Indicates support for write-through

Functions

get	Read the raw register contents using the appropriate assembly
read	Read the contents of a specific RegisterField. The returned value is already shifted to the right to start at bit 0. This means for a field value stored in the register at bit offset 3, the returned value is already shifted by 3 bits to the right. For example: If register raw value is 0b10110, the returned value for a register field specified as bits[4:3] would be 0b01. No further "masking" or "bit-shift" required
set	Write the raw register contents using the appropriate contents
write	Update the contents of a register from the RegisterFieldValue given. This will only change the bits the RegisterField definition specifies.