Module ruspiro_arch_aarch64::register::el1::sctlr_el1

SCTLR_EL1 - System Control Register EL1

Provides top level control of the system, including its memory system at EL1.

Usage Constraints

EL0	EL1 (NS)	EL1(S)	EL2	EL3(NS)	EL3(S)
-	R/W	R/W	R/W	R/W	R/W

Modules

A	alignment fault check
C	global data cache
CP15EN	CP15 barrier operations enabled ?
DZE	Enables access to the DC ZVA instruction at EL0
E0E	explicit data access endiannes at EL0
EE	exception endiannes
I	instruction cache
ITD	IT instructions disabled ?
M	globally enable MMU
NTWE	Non-trapping WFE instruction
NTWI	Non-trapping WFI instruction
SA	stack alignment checks
SA0	El0 stack alignment checks
SED	SETEND instructions disabled ?
UCI	Enable EL0 access to cache maintenance instructions: DC CVAU, DC CIVAC, DC CVAC and IC IVAU in Aarch64 mode
UCT	Enables EL0 access to the CTR_EL0 register in Aacrh64 mode
UMA	Controls access to interrupt masks from EL0 if EL0 is using Aarch64
WXN	Force all memory regions with write permissions as XN

Functions

get	Read the raw register contents using the appropriate assembly
read	Read the contents of a specific RegisterField. The returned value is already shifted to the right to start at bit 0. This means for a field value stored in the register at bit offset 3, the returned value is already shifted by 3 bits to the right. For example: If register raw value is 0b10110, the returned value for a register field specified as bits[4:3] would be 0b01. No further "masking" or "bit-shift" required
set	Write the raw register contents using the appropriate contents
write	Update the contents of a register from the RegisterFieldValue given. This will only change the bits the RegisterField definition specifies.