[−][src]Module rsl10_pac::rf::rf_reg27
REG27
Structs
| BIAS_EN_1_EN_BIAS_BB_LO_W | Write proxy for field |
| BIAS_EN_1_EN_BIAS_PLL_W | Write proxy for field |
| BIAS_EN_1_EN_BIAS_RXTX_W | Write proxy for field |
| BIAS_EN_2_EN_PTAT_W | Write proxy for field |
| BIAS_EN_2_EN_BIAS_BB_HI_W | Write proxy for field |
| CTRL_ADC_CTRL_ADC_W | Write proxy for field |
| CTRL_ADC_ONE_CK_RSSI_PHADC_W | Write proxy for field |
| CTRL_ADC_PHADC_DELLATCH_W | Write proxy for field |
Enums
| BIAS_EN_1_EN_BIAS_BB_LO_A | Bias enable for BB (same order as biases) |
| BIAS_EN_1_EN_BIAS_PLL_A | Bias enable for PLL (same order as biases) |
| BIAS_EN_1_EN_BIAS_RXTX_A | Bias enable for RxTx (same order as biases) |
| BIAS_EN_2_EN_PTAT_A | Enable PTAT |
| BIAS_EN_2_EN_BIAS_BB_HI_A | Bias enable for BB (same order as biases) |
| CTRL_ADC_CTRL_ADC_A | bits(1:0) => phADC reset delay, bits(3:2) phADC clock delay, bit(4) phADC latch idle |
| CTRL_ADC_ONE_CK_RSSI_PHADC_A | If set to 1, the RSSI and the phADC share the same clock |
| CTRL_ADC_PHADC_DELLATCH_A | phADC delay latch trimming |
Type Definitions
| BIAS_EN_1_EN_BIAS_BB_LO_R | Reader of field |
| BIAS_EN_1_EN_BIAS_PLL_R | Reader of field |
| BIAS_EN_1_EN_BIAS_RXTX_R | Reader of field |
| BIAS_EN_2_EN_PTAT_R | Reader of field |
| BIAS_EN_2_EN_BIAS_BB_HI_R | Reader of field |
| CTRL_ADC_CTRL_ADC_R | Reader of field |
| CTRL_ADC_ONE_CK_RSSI_PHADC_R | Reader of field |
| CTRL_ADC_PHADC_DELLATCH_R | Reader of field |
| R | Reader of register RF_REG27 |
| W | Writer for register RF_REG27 |