[][src]Crate rpi_pico_sdk

Modules

ctypes

ctypes for no-std

Structs

__BindgenUnionField
__darwin_pthread_handler_rec
__mbstate_t
__va_list_tag
_opaque_pthread_attr_t
_opaque_pthread_cond_t
_opaque_pthread_condattr_t
_opaque_pthread_mutex_t
_opaque_pthread_mutexattr_t
_opaque_pthread_once_t
_opaque_pthread_rwlock_t
_opaque_pthread_rwlockattr_t
_opaque_pthread_t
absolute_time_t
alarm_pool
datetime_t

\struct datetime_t \ingroup util_datetime \brief Structure containing date and time information

interp_hw_t
padsbank0_hw_t
repeating_timer

\brief Information about a repeating timer \ingroup repeating_timer \return

sio_hw_t
stdio_driver
timer_hw_t
uart_hw_t
uart_inst

Constants

ADC_BASE
BUSCTRL_BASE
CLOCKS_BASE
DMA_BASE
GPIO_IN
GPIO_OUT
I2C0_BASE
I2C1_BASE
INT8_MAX
INT8_MIN
INT16_MAX
INT16_MIN
INT32_MAX
INT32_MIN
INT64_MAX
INT64_MIN
INTPTR_MAX
INTPTR_MIN
INT_FAST8_MAX
INT_FAST8_MIN
INT_FAST16_MAX
INT_FAST16_MIN
INT_FAST32_MAX
INT_FAST32_MIN
INT_FAST64_MAX
INT_FAST64_MIN
INT_LEAST8_MAX
INT_LEAST8_MIN
INT_LEAST16_MAX
INT_LEAST16_MIN
INT_LEAST32_MAX
INT_LEAST32_MIN
INT_LEAST64_MAX
INT_LEAST64_MIN
IO_BANK0_BASE
IO_QSPI_BASE
NUM_BANK0_GPIOS
NUM_CORES
NUM_DMA_CHANNELS
NUM_IRQS
NUM_PIOS
NUM_PIO_STATE_MACHINES
NUM_PWM_SLICES
NUM_SPIN_LOCKS
NUM_TIMERS
NUM_UARTS
N_GPIOS
PADS_BANK0_BASE
PADS_BANK0_GPIO0_BITS
PADS_BANK0_GPIO0_DRIVE_ACCESS
PADS_BANK0_GPIO0_DRIVE_BITS
PADS_BANK0_GPIO0_DRIVE_LSB
PADS_BANK0_GPIO0_DRIVE_MSB
PADS_BANK0_GPIO0_DRIVE_RESET
PADS_BANK0_GPIO0_DRIVE_VALUE_2MA
PADS_BANK0_GPIO0_DRIVE_VALUE_4MA
PADS_BANK0_GPIO0_DRIVE_VALUE_8MA
PADS_BANK0_GPIO0_DRIVE_VALUE_12MA
PADS_BANK0_GPIO0_IE_ACCESS
PADS_BANK0_GPIO0_IE_BITS
PADS_BANK0_GPIO0_IE_LSB
PADS_BANK0_GPIO0_IE_MSB
PADS_BANK0_GPIO0_IE_RESET
PADS_BANK0_GPIO0_OD_ACCESS
PADS_BANK0_GPIO0_OD_BITS
PADS_BANK0_GPIO0_OD_LSB
PADS_BANK0_GPIO0_OD_MSB
PADS_BANK0_GPIO0_OD_RESET
PADS_BANK0_GPIO0_OFFSET
PADS_BANK0_GPIO0_PDE_ACCESS
PADS_BANK0_GPIO0_PDE_BITS
PADS_BANK0_GPIO0_PDE_LSB
PADS_BANK0_GPIO0_PDE_MSB
PADS_BANK0_GPIO0_PDE_RESET
PADS_BANK0_GPIO0_PUE_ACCESS
PADS_BANK0_GPIO0_PUE_BITS
PADS_BANK0_GPIO0_PUE_LSB
PADS_BANK0_GPIO0_PUE_MSB
PADS_BANK0_GPIO0_PUE_RESET
PADS_BANK0_GPIO0_RESET
PADS_BANK0_GPIO0_SCHMITT_ACCESS
PADS_BANK0_GPIO0_SCHMITT_BITS
PADS_BANK0_GPIO0_SCHMITT_LSB
PADS_BANK0_GPIO0_SCHMITT_MSB
PADS_BANK0_GPIO0_SCHMITT_RESET
PADS_BANK0_GPIO0_SLEWFAST_ACCESS
PADS_BANK0_GPIO0_SLEWFAST_BITS
PADS_BANK0_GPIO0_SLEWFAST_LSB
PADS_BANK0_GPIO0_SLEWFAST_MSB
PADS_BANK0_GPIO0_SLEWFAST_RESET
PADS_BANK0_GPIO1_BITS
PADS_BANK0_GPIO1_DRIVE_ACCESS
PADS_BANK0_GPIO1_DRIVE_BITS
PADS_BANK0_GPIO1_DRIVE_LSB
PADS_BANK0_GPIO1_DRIVE_MSB
PADS_BANK0_GPIO1_DRIVE_RESET
PADS_BANK0_GPIO1_DRIVE_VALUE_2MA
PADS_BANK0_GPIO1_DRIVE_VALUE_4MA
PADS_BANK0_GPIO1_DRIVE_VALUE_8MA
PADS_BANK0_GPIO1_DRIVE_VALUE_12MA
PADS_BANK0_GPIO1_IE_ACCESS
PADS_BANK0_GPIO1_IE_BITS
PADS_BANK0_GPIO1_IE_LSB
PADS_BANK0_GPIO1_IE_MSB
PADS_BANK0_GPIO1_IE_RESET
PADS_BANK0_GPIO1_OD_ACCESS
PADS_BANK0_GPIO1_OD_BITS
PADS_BANK0_GPIO1_OD_LSB
PADS_BANK0_GPIO1_OD_MSB
PADS_BANK0_GPIO1_OD_RESET
PADS_BANK0_GPIO1_OFFSET
PADS_BANK0_GPIO1_PDE_ACCESS
PADS_BANK0_GPIO1_PDE_BITS
PADS_BANK0_GPIO1_PDE_LSB
PADS_BANK0_GPIO1_PDE_MSB
PADS_BANK0_GPIO1_PDE_RESET
PADS_BANK0_GPIO1_PUE_ACCESS
PADS_BANK0_GPIO1_PUE_BITS
PADS_BANK0_GPIO1_PUE_LSB
PADS_BANK0_GPIO1_PUE_MSB
PADS_BANK0_GPIO1_PUE_RESET
PADS_BANK0_GPIO1_RESET
PADS_BANK0_GPIO1_SCHMITT_ACCESS
PADS_BANK0_GPIO1_SCHMITT_BITS
PADS_BANK0_GPIO1_SCHMITT_LSB
PADS_BANK0_GPIO1_SCHMITT_MSB
PADS_BANK0_GPIO1_SCHMITT_RESET
PADS_BANK0_GPIO1_SLEWFAST_ACCESS
PADS_BANK0_GPIO1_SLEWFAST_BITS
PADS_BANK0_GPIO1_SLEWFAST_LSB
PADS_BANK0_GPIO1_SLEWFAST_MSB
PADS_BANK0_GPIO1_SLEWFAST_RESET
PADS_BANK0_GPIO2_BITS
PADS_BANK0_GPIO2_DRIVE_ACCESS
PADS_BANK0_GPIO2_DRIVE_BITS
PADS_BANK0_GPIO2_DRIVE_LSB
PADS_BANK0_GPIO2_DRIVE_MSB
PADS_BANK0_GPIO2_DRIVE_RESET
PADS_BANK0_GPIO2_DRIVE_VALUE_2MA
PADS_BANK0_GPIO2_DRIVE_VALUE_4MA
PADS_BANK0_GPIO2_DRIVE_VALUE_8MA
PADS_BANK0_GPIO2_DRIVE_VALUE_12MA
PADS_BANK0_GPIO2_IE_ACCESS
PADS_BANK0_GPIO2_IE_BITS
PADS_BANK0_GPIO2_IE_LSB
PADS_BANK0_GPIO2_IE_MSB
PADS_BANK0_GPIO2_IE_RESET
PADS_BANK0_GPIO2_OD_ACCESS
PADS_BANK0_GPIO2_OD_BITS
PADS_BANK0_GPIO2_OD_LSB
PADS_BANK0_GPIO2_OD_MSB
PADS_BANK0_GPIO2_OD_RESET
PADS_BANK0_GPIO2_OFFSET
PADS_BANK0_GPIO2_PDE_ACCESS
PADS_BANK0_GPIO2_PDE_BITS
PADS_BANK0_GPIO2_PDE_LSB
PADS_BANK0_GPIO2_PDE_MSB
PADS_BANK0_GPIO2_PDE_RESET
PADS_BANK0_GPIO2_PUE_ACCESS
PADS_BANK0_GPIO2_PUE_BITS
PADS_BANK0_GPIO2_PUE_LSB
PADS_BANK0_GPIO2_PUE_MSB
PADS_BANK0_GPIO2_PUE_RESET
PADS_BANK0_GPIO2_RESET
PADS_BANK0_GPIO2_SCHMITT_ACCESS
PADS_BANK0_GPIO2_SCHMITT_BITS
PADS_BANK0_GPIO2_SCHMITT_LSB
PADS_BANK0_GPIO2_SCHMITT_MSB
PADS_BANK0_GPIO2_SCHMITT_RESET
PADS_BANK0_GPIO2_SLEWFAST_ACCESS
PADS_BANK0_GPIO2_SLEWFAST_BITS
PADS_BANK0_GPIO2_SLEWFAST_LSB
PADS_BANK0_GPIO2_SLEWFAST_MSB
PADS_BANK0_GPIO2_SLEWFAST_RESET
PADS_BANK0_GPIO3_BITS
PADS_BANK0_GPIO3_DRIVE_ACCESS
PADS_BANK0_GPIO3_DRIVE_BITS
PADS_BANK0_GPIO3_DRIVE_LSB
PADS_BANK0_GPIO3_DRIVE_MSB
PADS_BANK0_GPIO3_DRIVE_RESET
PADS_BANK0_GPIO3_DRIVE_VALUE_2MA
PADS_BANK0_GPIO3_DRIVE_VALUE_4MA
PADS_BANK0_GPIO3_DRIVE_VALUE_8MA
PADS_BANK0_GPIO3_DRIVE_VALUE_12MA
PADS_BANK0_GPIO3_IE_ACCESS
PADS_BANK0_GPIO3_IE_BITS
PADS_BANK0_GPIO3_IE_LSB
PADS_BANK0_GPIO3_IE_MSB
PADS_BANK0_GPIO3_IE_RESET
PADS_BANK0_GPIO3_OD_ACCESS
PADS_BANK0_GPIO3_OD_BITS
PADS_BANK0_GPIO3_OD_LSB
PADS_BANK0_GPIO3_OD_MSB
PADS_BANK0_GPIO3_OD_RESET
PADS_BANK0_GPIO3_OFFSET
PADS_BANK0_GPIO3_PDE_ACCESS
PADS_BANK0_GPIO3_PDE_BITS
PADS_BANK0_GPIO3_PDE_LSB
PADS_BANK0_GPIO3_PDE_MSB
PADS_BANK0_GPIO3_PDE_RESET
PADS_BANK0_GPIO3_PUE_ACCESS
PADS_BANK0_GPIO3_PUE_BITS
PADS_BANK0_GPIO3_PUE_LSB
PADS_BANK0_GPIO3_PUE_MSB
PADS_BANK0_GPIO3_PUE_RESET
PADS_BANK0_GPIO3_RESET
PADS_BANK0_GPIO3_SCHMITT_ACCESS
PADS_BANK0_GPIO3_SCHMITT_BITS
PADS_BANK0_GPIO3_SCHMITT_LSB
PADS_BANK0_GPIO3_SCHMITT_MSB
PADS_BANK0_GPIO3_SCHMITT_RESET
PADS_BANK0_GPIO3_SLEWFAST_ACCESS
PADS_BANK0_GPIO3_SLEWFAST_BITS
PADS_BANK0_GPIO3_SLEWFAST_LSB
PADS_BANK0_GPIO3_SLEWFAST_MSB
PADS_BANK0_GPIO3_SLEWFAST_RESET
PADS_BANK0_GPIO4_BITS
PADS_BANK0_GPIO4_DRIVE_ACCESS
PADS_BANK0_GPIO4_DRIVE_BITS
PADS_BANK0_GPIO4_DRIVE_LSB
PADS_BANK0_GPIO4_DRIVE_MSB
PADS_BANK0_GPIO4_DRIVE_RESET
PADS_BANK0_GPIO4_DRIVE_VALUE_2MA
PADS_BANK0_GPIO4_DRIVE_VALUE_4MA
PADS_BANK0_GPIO4_DRIVE_VALUE_8MA
PADS_BANK0_GPIO4_DRIVE_VALUE_12MA
PADS_BANK0_GPIO4_IE_ACCESS
PADS_BANK0_GPIO4_IE_BITS
PADS_BANK0_GPIO4_IE_LSB
PADS_BANK0_GPIO4_IE_MSB
PADS_BANK0_GPIO4_IE_RESET
PADS_BANK0_GPIO4_OD_ACCESS
PADS_BANK0_GPIO4_OD_BITS
PADS_BANK0_GPIO4_OD_LSB
PADS_BANK0_GPIO4_OD_MSB
PADS_BANK0_GPIO4_OD_RESET
PADS_BANK0_GPIO4_OFFSET
PADS_BANK0_GPIO4_PDE_ACCESS
PADS_BANK0_GPIO4_PDE_BITS
PADS_BANK0_GPIO4_PDE_LSB
PADS_BANK0_GPIO4_PDE_MSB
PADS_BANK0_GPIO4_PDE_RESET
PADS_BANK0_GPIO4_PUE_ACCESS
PADS_BANK0_GPIO4_PUE_BITS
PADS_BANK0_GPIO4_PUE_LSB
PADS_BANK0_GPIO4_PUE_MSB
PADS_BANK0_GPIO4_PUE_RESET
PADS_BANK0_GPIO4_RESET
PADS_BANK0_GPIO4_SCHMITT_ACCESS
PADS_BANK0_GPIO4_SCHMITT_BITS
PADS_BANK0_GPIO4_SCHMITT_LSB
PADS_BANK0_GPIO4_SCHMITT_MSB
PADS_BANK0_GPIO4_SCHMITT_RESET
PADS_BANK0_GPIO4_SLEWFAST_ACCESS
PADS_BANK0_GPIO4_SLEWFAST_BITS
PADS_BANK0_GPIO4_SLEWFAST_LSB
PADS_BANK0_GPIO4_SLEWFAST_MSB
PADS_BANK0_GPIO4_SLEWFAST_RESET
PADS_BANK0_GPIO5_BITS
PADS_BANK0_GPIO5_DRIVE_ACCESS
PADS_BANK0_GPIO5_DRIVE_BITS
PADS_BANK0_GPIO5_DRIVE_LSB
PADS_BANK0_GPIO5_DRIVE_MSB
PADS_BANK0_GPIO5_DRIVE_RESET
PADS_BANK0_GPIO5_DRIVE_VALUE_2MA
PADS_BANK0_GPIO5_DRIVE_VALUE_4MA
PADS_BANK0_GPIO5_DRIVE_VALUE_8MA
PADS_BANK0_GPIO5_DRIVE_VALUE_12MA
PADS_BANK0_GPIO5_IE_ACCESS
PADS_BANK0_GPIO5_IE_BITS
PADS_BANK0_GPIO5_IE_LSB
PADS_BANK0_GPIO5_IE_MSB
PADS_BANK0_GPIO5_IE_RESET
PADS_BANK0_GPIO5_OD_ACCESS
PADS_BANK0_GPIO5_OD_BITS
PADS_BANK0_GPIO5_OD_LSB
PADS_BANK0_GPIO5_OD_MSB
PADS_BANK0_GPIO5_OD_RESET
PADS_BANK0_GPIO5_OFFSET
PADS_BANK0_GPIO5_PDE_ACCESS
PADS_BANK0_GPIO5_PDE_BITS
PADS_BANK0_GPIO5_PDE_LSB
PADS_BANK0_GPIO5_PDE_MSB
PADS_BANK0_GPIO5_PDE_RESET
PADS_BANK0_GPIO5_PUE_ACCESS
PADS_BANK0_GPIO5_PUE_BITS
PADS_BANK0_GPIO5_PUE_LSB
PADS_BANK0_GPIO5_PUE_MSB
PADS_BANK0_GPIO5_PUE_RESET
PADS_BANK0_GPIO5_RESET
PADS_BANK0_GPIO5_SCHMITT_ACCESS
PADS_BANK0_GPIO5_SCHMITT_BITS
PADS_BANK0_GPIO5_SCHMITT_LSB
PADS_BANK0_GPIO5_SCHMITT_MSB
PADS_BANK0_GPIO5_SCHMITT_RESET
PADS_BANK0_GPIO5_SLEWFAST_ACCESS
PADS_BANK0_GPIO5_SLEWFAST_BITS
PADS_BANK0_GPIO5_SLEWFAST_LSB
PADS_BANK0_GPIO5_SLEWFAST_MSB
PADS_BANK0_GPIO5_SLEWFAST_RESET
PADS_BANK0_GPIO6_BITS
PADS_BANK0_GPIO6_DRIVE_ACCESS
PADS_BANK0_GPIO6_DRIVE_BITS
PADS_BANK0_GPIO6_DRIVE_LSB
PADS_BANK0_GPIO6_DRIVE_MSB
PADS_BANK0_GPIO6_DRIVE_RESET
PADS_BANK0_GPIO6_DRIVE_VALUE_2MA
PADS_BANK0_GPIO6_DRIVE_VALUE_4MA
PADS_BANK0_GPIO6_DRIVE_VALUE_8MA
PADS_BANK0_GPIO6_DRIVE_VALUE_12MA
PADS_BANK0_GPIO6_IE_ACCESS
PADS_BANK0_GPIO6_IE_BITS
PADS_BANK0_GPIO6_IE_LSB
PADS_BANK0_GPIO6_IE_MSB
PADS_BANK0_GPIO6_IE_RESET
PADS_BANK0_GPIO6_OD_ACCESS
PADS_BANK0_GPIO6_OD_BITS
PADS_BANK0_GPIO6_OD_LSB
PADS_BANK0_GPIO6_OD_MSB
PADS_BANK0_GPIO6_OD_RESET
PADS_BANK0_GPIO6_OFFSET
PADS_BANK0_GPIO6_PDE_ACCESS
PADS_BANK0_GPIO6_PDE_BITS
PADS_BANK0_GPIO6_PDE_LSB
PADS_BANK0_GPIO6_PDE_MSB
PADS_BANK0_GPIO6_PDE_RESET
PADS_BANK0_GPIO6_PUE_ACCESS
PADS_BANK0_GPIO6_PUE_BITS
PADS_BANK0_GPIO6_PUE_LSB
PADS_BANK0_GPIO6_PUE_MSB
PADS_BANK0_GPIO6_PUE_RESET
PADS_BANK0_GPIO6_RESET
PADS_BANK0_GPIO6_SCHMITT_ACCESS
PADS_BANK0_GPIO6_SCHMITT_BITS
PADS_BANK0_GPIO6_SCHMITT_LSB
PADS_BANK0_GPIO6_SCHMITT_MSB
PADS_BANK0_GPIO6_SCHMITT_RESET
PADS_BANK0_GPIO6_SLEWFAST_ACCESS
PADS_BANK0_GPIO6_SLEWFAST_BITS
PADS_BANK0_GPIO6_SLEWFAST_LSB
PADS_BANK0_GPIO6_SLEWFAST_MSB
PADS_BANK0_GPIO6_SLEWFAST_RESET
PADS_BANK0_GPIO7_BITS
PADS_BANK0_GPIO7_DRIVE_ACCESS
PADS_BANK0_GPIO7_DRIVE_BITS
PADS_BANK0_GPIO7_DRIVE_LSB
PADS_BANK0_GPIO7_DRIVE_MSB
PADS_BANK0_GPIO7_DRIVE_RESET
PADS_BANK0_GPIO7_DRIVE_VALUE_2MA
PADS_BANK0_GPIO7_DRIVE_VALUE_4MA
PADS_BANK0_GPIO7_DRIVE_VALUE_8MA
PADS_BANK0_GPIO7_DRIVE_VALUE_12MA
PADS_BANK0_GPIO7_IE_ACCESS
PADS_BANK0_GPIO7_IE_BITS
PADS_BANK0_GPIO7_IE_LSB
PADS_BANK0_GPIO7_IE_MSB
PADS_BANK0_GPIO7_IE_RESET
PADS_BANK0_GPIO7_OD_ACCESS
PADS_BANK0_GPIO7_OD_BITS
PADS_BANK0_GPIO7_OD_LSB
PADS_BANK0_GPIO7_OD_MSB
PADS_BANK0_GPIO7_OD_RESET
PADS_BANK0_GPIO7_OFFSET
PADS_BANK0_GPIO7_PDE_ACCESS
PADS_BANK0_GPIO7_PDE_BITS
PADS_BANK0_GPIO7_PDE_LSB
PADS_BANK0_GPIO7_PDE_MSB
PADS_BANK0_GPIO7_PDE_RESET
PADS_BANK0_GPIO7_PUE_ACCESS
PADS_BANK0_GPIO7_PUE_BITS
PADS_BANK0_GPIO7_PUE_LSB
PADS_BANK0_GPIO7_PUE_MSB
PADS_BANK0_GPIO7_PUE_RESET
PADS_BANK0_GPIO7_RESET
PADS_BANK0_GPIO7_SCHMITT_ACCESS
PADS_BANK0_GPIO7_SCHMITT_BITS
PADS_BANK0_GPIO7_SCHMITT_LSB
PADS_BANK0_GPIO7_SCHMITT_MSB
PADS_BANK0_GPIO7_SCHMITT_RESET
PADS_BANK0_GPIO7_SLEWFAST_ACCESS
PADS_BANK0_GPIO7_SLEWFAST_BITS
PADS_BANK0_GPIO7_SLEWFAST_LSB
PADS_BANK0_GPIO7_SLEWFAST_MSB
PADS_BANK0_GPIO7_SLEWFAST_RESET
PADS_BANK0_GPIO8_BITS
PADS_BANK0_GPIO8_DRIVE_ACCESS
PADS_BANK0_GPIO8_DRIVE_BITS
PADS_BANK0_GPIO8_DRIVE_LSB
PADS_BANK0_GPIO8_DRIVE_MSB
PADS_BANK0_GPIO8_DRIVE_RESET
PADS_BANK0_GPIO8_DRIVE_VALUE_2MA
PADS_BANK0_GPIO8_DRIVE_VALUE_4MA
PADS_BANK0_GPIO8_DRIVE_VALUE_8MA
PADS_BANK0_GPIO8_DRIVE_VALUE_12MA
PADS_BANK0_GPIO8_IE_ACCESS
PADS_BANK0_GPIO8_IE_BITS
PADS_BANK0_GPIO8_IE_LSB
PADS_BANK0_GPIO8_IE_MSB
PADS_BANK0_GPIO8_IE_RESET
PADS_BANK0_GPIO8_OD_ACCESS
PADS_BANK0_GPIO8_OD_BITS
PADS_BANK0_GPIO8_OD_LSB
PADS_BANK0_GPIO8_OD_MSB
PADS_BANK0_GPIO8_OD_RESET
PADS_BANK0_GPIO8_OFFSET
PADS_BANK0_GPIO8_PDE_ACCESS
PADS_BANK0_GPIO8_PDE_BITS
PADS_BANK0_GPIO8_PDE_LSB
PADS_BANK0_GPIO8_PDE_MSB
PADS_BANK0_GPIO8_PDE_RESET
PADS_BANK0_GPIO8_PUE_ACCESS
PADS_BANK0_GPIO8_PUE_BITS
PADS_BANK0_GPIO8_PUE_LSB
PADS_BANK0_GPIO8_PUE_MSB
PADS_BANK0_GPIO8_PUE_RESET
PADS_BANK0_GPIO8_RESET
PADS_BANK0_GPIO8_SCHMITT_ACCESS
PADS_BANK0_GPIO8_SCHMITT_BITS
PADS_BANK0_GPIO8_SCHMITT_LSB
PADS_BANK0_GPIO8_SCHMITT_MSB
PADS_BANK0_GPIO8_SCHMITT_RESET
PADS_BANK0_GPIO8_SLEWFAST_ACCESS
PADS_BANK0_GPIO8_SLEWFAST_BITS
PADS_BANK0_GPIO8_SLEWFAST_LSB
PADS_BANK0_GPIO8_SLEWFAST_MSB
PADS_BANK0_GPIO8_SLEWFAST_RESET
PADS_BANK0_GPIO9_BITS
PADS_BANK0_GPIO9_DRIVE_ACCESS
PADS_BANK0_GPIO9_DRIVE_BITS
PADS_BANK0_GPIO9_DRIVE_LSB
PADS_BANK0_GPIO9_DRIVE_MSB
PADS_BANK0_GPIO9_DRIVE_RESET
PADS_BANK0_GPIO9_DRIVE_VALUE_2MA
PADS_BANK0_GPIO9_DRIVE_VALUE_4MA
PADS_BANK0_GPIO9_DRIVE_VALUE_8MA
PADS_BANK0_GPIO9_DRIVE_VALUE_12MA
PADS_BANK0_GPIO9_IE_ACCESS
PADS_BANK0_GPIO9_IE_BITS
PADS_BANK0_GPIO9_IE_LSB
PADS_BANK0_GPIO9_IE_MSB
PADS_BANK0_GPIO9_IE_RESET
PADS_BANK0_GPIO9_OD_ACCESS
PADS_BANK0_GPIO9_OD_BITS
PADS_BANK0_GPIO9_OD_LSB
PADS_BANK0_GPIO9_OD_MSB
PADS_BANK0_GPIO9_OD_RESET
PADS_BANK0_GPIO9_OFFSET
PADS_BANK0_GPIO9_PDE_ACCESS
PADS_BANK0_GPIO9_PDE_BITS
PADS_BANK0_GPIO9_PDE_LSB
PADS_BANK0_GPIO9_PDE_MSB
PADS_BANK0_GPIO9_PDE_RESET
PADS_BANK0_GPIO9_PUE_ACCESS
PADS_BANK0_GPIO9_PUE_BITS
PADS_BANK0_GPIO9_PUE_LSB
PADS_BANK0_GPIO9_PUE_MSB
PADS_BANK0_GPIO9_PUE_RESET
PADS_BANK0_GPIO9_RESET
PADS_BANK0_GPIO9_SCHMITT_ACCESS
PADS_BANK0_GPIO9_SCHMITT_BITS
PADS_BANK0_GPIO9_SCHMITT_LSB
PADS_BANK0_GPIO9_SCHMITT_MSB
PADS_BANK0_GPIO9_SCHMITT_RESET
PADS_BANK0_GPIO9_SLEWFAST_ACCESS
PADS_BANK0_GPIO9_SLEWFAST_BITS
PADS_BANK0_GPIO9_SLEWFAST_LSB
PADS_BANK0_GPIO9_SLEWFAST_MSB
PADS_BANK0_GPIO9_SLEWFAST_RESET
PADS_BANK0_GPIO10_BITS
PADS_BANK0_GPIO10_DRIVE_ACCESS
PADS_BANK0_GPIO10_DRIVE_BITS
PADS_BANK0_GPIO10_DRIVE_LSB
PADS_BANK0_GPIO10_DRIVE_MSB
PADS_BANK0_GPIO10_DRIVE_RESET
PADS_BANK0_GPIO10_DRIVE_VALUE_2MA
PADS_BANK0_GPIO10_DRIVE_VALUE_4MA
PADS_BANK0_GPIO10_DRIVE_VALUE_8MA
PADS_BANK0_GPIO10_DRIVE_VALUE_12MA
PADS_BANK0_GPIO10_IE_ACCESS
PADS_BANK0_GPIO10_IE_BITS
PADS_BANK0_GPIO10_IE_LSB
PADS_BANK0_GPIO10_IE_MSB
PADS_BANK0_GPIO10_IE_RESET
PADS_BANK0_GPIO10_OD_ACCESS
PADS_BANK0_GPIO10_OD_BITS
PADS_BANK0_GPIO10_OD_LSB
PADS_BANK0_GPIO10_OD_MSB
PADS_BANK0_GPIO10_OD_RESET
PADS_BANK0_GPIO10_OFFSET
PADS_BANK0_GPIO10_PDE_ACCESS
PADS_BANK0_GPIO10_PDE_BITS
PADS_BANK0_GPIO10_PDE_LSB
PADS_BANK0_GPIO10_PDE_MSB
PADS_BANK0_GPIO10_PDE_RESET
PADS_BANK0_GPIO10_PUE_ACCESS
PADS_BANK0_GPIO10_PUE_BITS
PADS_BANK0_GPIO10_PUE_LSB
PADS_BANK0_GPIO10_PUE_MSB
PADS_BANK0_GPIO10_PUE_RESET
PADS_BANK0_GPIO10_RESET
PADS_BANK0_GPIO10_SCHMITT_ACCESS
PADS_BANK0_GPIO10_SCHMITT_BITS
PADS_BANK0_GPIO10_SCHMITT_LSB
PADS_BANK0_GPIO10_SCHMITT_MSB
PADS_BANK0_GPIO10_SCHMITT_RESET
PADS_BANK0_GPIO10_SLEWFAST_ACCESS
PADS_BANK0_GPIO10_SLEWFAST_BITS
PADS_BANK0_GPIO10_SLEWFAST_LSB
PADS_BANK0_GPIO10_SLEWFAST_MSB
PADS_BANK0_GPIO10_SLEWFAST_RESET
PADS_BANK0_GPIO11_BITS
PADS_BANK0_GPIO11_DRIVE_ACCESS
PADS_BANK0_GPIO11_DRIVE_BITS
PADS_BANK0_GPIO11_DRIVE_LSB
PADS_BANK0_GPIO11_DRIVE_MSB
PADS_BANK0_GPIO11_DRIVE_RESET
PADS_BANK0_GPIO11_DRIVE_VALUE_2MA
PADS_BANK0_GPIO11_DRIVE_VALUE_4MA
PADS_BANK0_GPIO11_DRIVE_VALUE_8MA
PADS_BANK0_GPIO11_DRIVE_VALUE_12MA
PADS_BANK0_GPIO11_IE_ACCESS
PADS_BANK0_GPIO11_IE_BITS
PADS_BANK0_GPIO11_IE_LSB
PADS_BANK0_GPIO11_IE_MSB
PADS_BANK0_GPIO11_IE_RESET
PADS_BANK0_GPIO11_OD_ACCESS
PADS_BANK0_GPIO11_OD_BITS
PADS_BANK0_GPIO11_OD_LSB
PADS_BANK0_GPIO11_OD_MSB
PADS_BANK0_GPIO11_OD_RESET
PADS_BANK0_GPIO11_OFFSET
PADS_BANK0_GPIO11_PDE_ACCESS
PADS_BANK0_GPIO11_PDE_BITS
PADS_BANK0_GPIO11_PDE_LSB
PADS_BANK0_GPIO11_PDE_MSB
PADS_BANK0_GPIO11_PDE_RESET
PADS_BANK0_GPIO11_PUE_ACCESS
PADS_BANK0_GPIO11_PUE_BITS
PADS_BANK0_GPIO11_PUE_LSB
PADS_BANK0_GPIO11_PUE_MSB
PADS_BANK0_GPIO11_PUE_RESET
PADS_BANK0_GPIO11_RESET
PADS_BANK0_GPIO11_SCHMITT_ACCESS
PADS_BANK0_GPIO11_SCHMITT_BITS
PADS_BANK0_GPIO11_SCHMITT_LSB
PADS_BANK0_GPIO11_SCHMITT_MSB
PADS_BANK0_GPIO11_SCHMITT_RESET
PADS_BANK0_GPIO11_SLEWFAST_ACCESS
PADS_BANK0_GPIO11_SLEWFAST_BITS
PADS_BANK0_GPIO11_SLEWFAST_LSB
PADS_BANK0_GPIO11_SLEWFAST_MSB
PADS_BANK0_GPIO11_SLEWFAST_RESET
PADS_BANK0_GPIO12_BITS
PADS_BANK0_GPIO12_DRIVE_ACCESS
PADS_BANK0_GPIO12_DRIVE_BITS
PADS_BANK0_GPIO12_DRIVE_LSB
PADS_BANK0_GPIO12_DRIVE_MSB
PADS_BANK0_GPIO12_DRIVE_RESET
PADS_BANK0_GPIO12_DRIVE_VALUE_2MA
PADS_BANK0_GPIO12_DRIVE_VALUE_4MA
PADS_BANK0_GPIO12_DRIVE_VALUE_8MA
PADS_BANK0_GPIO12_DRIVE_VALUE_12MA
PADS_BANK0_GPIO12_IE_ACCESS
PADS_BANK0_GPIO12_IE_BITS
PADS_BANK0_GPIO12_IE_LSB
PADS_BANK0_GPIO12_IE_MSB
PADS_BANK0_GPIO12_IE_RESET
PADS_BANK0_GPIO12_OD_ACCESS
PADS_BANK0_GPIO12_OD_BITS
PADS_BANK0_GPIO12_OD_LSB
PADS_BANK0_GPIO12_OD_MSB
PADS_BANK0_GPIO12_OD_RESET
PADS_BANK0_GPIO12_OFFSET
PADS_BANK0_GPIO12_PDE_ACCESS
PADS_BANK0_GPIO12_PDE_BITS
PADS_BANK0_GPIO12_PDE_LSB
PADS_BANK0_GPIO12_PDE_MSB
PADS_BANK0_GPIO12_PDE_RESET
PADS_BANK0_GPIO12_PUE_ACCESS
PADS_BANK0_GPIO12_PUE_BITS
PADS_BANK0_GPIO12_PUE_LSB
PADS_BANK0_GPIO12_PUE_MSB
PADS_BANK0_GPIO12_PUE_RESET
PADS_BANK0_GPIO12_RESET
PADS_BANK0_GPIO12_SCHMITT_ACCESS
PADS_BANK0_GPIO12_SCHMITT_BITS
PADS_BANK0_GPIO12_SCHMITT_LSB
PADS_BANK0_GPIO12_SCHMITT_MSB
PADS_BANK0_GPIO12_SCHMITT_RESET
PADS_BANK0_GPIO12_SLEWFAST_ACCESS
PADS_BANK0_GPIO12_SLEWFAST_BITS
PADS_BANK0_GPIO12_SLEWFAST_LSB
PADS_BANK0_GPIO12_SLEWFAST_MSB
PADS_BANK0_GPIO12_SLEWFAST_RESET
PADS_BANK0_GPIO13_BITS
PADS_BANK0_GPIO13_DRIVE_ACCESS
PADS_BANK0_GPIO13_DRIVE_BITS
PADS_BANK0_GPIO13_DRIVE_LSB
PADS_BANK0_GPIO13_DRIVE_MSB
PADS_BANK0_GPIO13_DRIVE_RESET
PADS_BANK0_GPIO13_DRIVE_VALUE_2MA
PADS_BANK0_GPIO13_DRIVE_VALUE_4MA
PADS_BANK0_GPIO13_DRIVE_VALUE_8MA
PADS_BANK0_GPIO13_DRIVE_VALUE_12MA
PADS_BANK0_GPIO13_IE_ACCESS
PADS_BANK0_GPIO13_IE_BITS
PADS_BANK0_GPIO13_IE_LSB
PADS_BANK0_GPIO13_IE_MSB
PADS_BANK0_GPIO13_IE_RESET
PADS_BANK0_GPIO13_OD_ACCESS
PADS_BANK0_GPIO13_OD_BITS
PADS_BANK0_GPIO13_OD_LSB
PADS_BANK0_GPIO13_OD_MSB
PADS_BANK0_GPIO13_OD_RESET
PADS_BANK0_GPIO13_OFFSET
PADS_BANK0_GPIO13_PDE_ACCESS
PADS_BANK0_GPIO13_PDE_BITS
PADS_BANK0_GPIO13_PDE_LSB
PADS_BANK0_GPIO13_PDE_MSB
PADS_BANK0_GPIO13_PDE_RESET
PADS_BANK0_GPIO13_PUE_ACCESS
PADS_BANK0_GPIO13_PUE_BITS
PADS_BANK0_GPIO13_PUE_LSB
PADS_BANK0_GPIO13_PUE_MSB
PADS_BANK0_GPIO13_PUE_RESET
PADS_BANK0_GPIO13_RESET
PADS_BANK0_GPIO13_SCHMITT_ACCESS
PADS_BANK0_GPIO13_SCHMITT_BITS
PADS_BANK0_GPIO13_SCHMITT_LSB
PADS_BANK0_GPIO13_SCHMITT_MSB
PADS_BANK0_GPIO13_SCHMITT_RESET
PADS_BANK0_GPIO13_SLEWFAST_ACCESS
PADS_BANK0_GPIO13_SLEWFAST_BITS
PADS_BANK0_GPIO13_SLEWFAST_LSB
PADS_BANK0_GPIO13_SLEWFAST_MSB
PADS_BANK0_GPIO13_SLEWFAST_RESET
PADS_BANK0_GPIO14_BITS
PADS_BANK0_GPIO14_DRIVE_ACCESS
PADS_BANK0_GPIO14_DRIVE_BITS
PADS_BANK0_GPIO14_DRIVE_LSB
PADS_BANK0_GPIO14_DRIVE_MSB
PADS_BANK0_GPIO14_DRIVE_RESET
PADS_BANK0_GPIO14_DRIVE_VALUE_2MA
PADS_BANK0_GPIO14_DRIVE_VALUE_4MA
PADS_BANK0_GPIO14_DRIVE_VALUE_8MA
PADS_BANK0_GPIO14_DRIVE_VALUE_12MA
PADS_BANK0_GPIO14_IE_ACCESS
PADS_BANK0_GPIO14_IE_BITS
PADS_BANK0_GPIO14_IE_LSB
PADS_BANK0_GPIO14_IE_MSB
PADS_BANK0_GPIO14_IE_RESET
PADS_BANK0_GPIO14_OD_ACCESS
PADS_BANK0_GPIO14_OD_BITS
PADS_BANK0_GPIO14_OD_LSB
PADS_BANK0_GPIO14_OD_MSB
PADS_BANK0_GPIO14_OD_RESET
PADS_BANK0_GPIO14_OFFSET
PADS_BANK0_GPIO14_PDE_ACCESS
PADS_BANK0_GPIO14_PDE_BITS
PADS_BANK0_GPIO14_PDE_LSB
PADS_BANK0_GPIO14_PDE_MSB
PADS_BANK0_GPIO14_PDE_RESET
PADS_BANK0_GPIO14_PUE_ACCESS
PADS_BANK0_GPIO14_PUE_BITS
PADS_BANK0_GPIO14_PUE_LSB
PADS_BANK0_GPIO14_PUE_MSB
PADS_BANK0_GPIO14_PUE_RESET
PADS_BANK0_GPIO14_RESET
PADS_BANK0_GPIO14_SCHMITT_ACCESS
PADS_BANK0_GPIO14_SCHMITT_BITS
PADS_BANK0_GPIO14_SCHMITT_LSB
PADS_BANK0_GPIO14_SCHMITT_MSB
PADS_BANK0_GPIO14_SCHMITT_RESET
PADS_BANK0_GPIO14_SLEWFAST_ACCESS
PADS_BANK0_GPIO14_SLEWFAST_BITS
PADS_BANK0_GPIO14_SLEWFAST_LSB
PADS_BANK0_GPIO14_SLEWFAST_MSB
PADS_BANK0_GPIO14_SLEWFAST_RESET
PADS_BANK0_GPIO15_BITS
PADS_BANK0_GPIO15_DRIVE_ACCESS
PADS_BANK0_GPIO15_DRIVE_BITS
PADS_BANK0_GPIO15_DRIVE_LSB
PADS_BANK0_GPIO15_DRIVE_MSB
PADS_BANK0_GPIO15_DRIVE_RESET
PADS_BANK0_GPIO15_DRIVE_VALUE_2MA
PADS_BANK0_GPIO15_DRIVE_VALUE_4MA
PADS_BANK0_GPIO15_DRIVE_VALUE_8MA
PADS_BANK0_GPIO15_DRIVE_VALUE_12MA
PADS_BANK0_GPIO15_IE_ACCESS
PADS_BANK0_GPIO15_IE_BITS
PADS_BANK0_GPIO15_IE_LSB
PADS_BANK0_GPIO15_IE_MSB
PADS_BANK0_GPIO15_IE_RESET
PADS_BANK0_GPIO15_OD_ACCESS
PADS_BANK0_GPIO15_OD_BITS
PADS_BANK0_GPIO15_OD_LSB
PADS_BANK0_GPIO15_OD_MSB
PADS_BANK0_GPIO15_OD_RESET
PADS_BANK0_GPIO15_OFFSET
PADS_BANK0_GPIO15_PDE_ACCESS
PADS_BANK0_GPIO15_PDE_BITS
PADS_BANK0_GPIO15_PDE_LSB
PADS_BANK0_GPIO15_PDE_MSB
PADS_BANK0_GPIO15_PDE_RESET
PADS_BANK0_GPIO15_PUE_ACCESS
PADS_BANK0_GPIO15_PUE_BITS
PADS_BANK0_GPIO15_PUE_LSB
PADS_BANK0_GPIO15_PUE_MSB
PADS_BANK0_GPIO15_PUE_RESET
PADS_BANK0_GPIO15_RESET
PADS_BANK0_GPIO15_SCHMITT_ACCESS
PADS_BANK0_GPIO15_SCHMITT_BITS
PADS_BANK0_GPIO15_SCHMITT_LSB
PADS_BANK0_GPIO15_SCHMITT_MSB
PADS_BANK0_GPIO15_SCHMITT_RESET
PADS_BANK0_GPIO15_SLEWFAST_ACCESS
PADS_BANK0_GPIO15_SLEWFAST_BITS
PADS_BANK0_GPIO15_SLEWFAST_LSB
PADS_BANK0_GPIO15_SLEWFAST_MSB
PADS_BANK0_GPIO15_SLEWFAST_RESET
PADS_BANK0_GPIO16_BITS
PADS_BANK0_GPIO16_DRIVE_ACCESS
PADS_BANK0_GPIO16_DRIVE_BITS
PADS_BANK0_GPIO16_DRIVE_LSB
PADS_BANK0_GPIO16_DRIVE_MSB
PADS_BANK0_GPIO16_DRIVE_RESET
PADS_BANK0_GPIO16_DRIVE_VALUE_2MA
PADS_BANK0_GPIO16_DRIVE_VALUE_4MA
PADS_BANK0_GPIO16_DRIVE_VALUE_8MA
PADS_BANK0_GPIO16_DRIVE_VALUE_12MA
PADS_BANK0_GPIO16_IE_ACCESS
PADS_BANK0_GPIO16_IE_BITS
PADS_BANK0_GPIO16_IE_LSB
PADS_BANK0_GPIO16_IE_MSB
PADS_BANK0_GPIO16_IE_RESET
PADS_BANK0_GPIO16_OD_ACCESS
PADS_BANK0_GPIO16_OD_BITS
PADS_BANK0_GPIO16_OD_LSB
PADS_BANK0_GPIO16_OD_MSB
PADS_BANK0_GPIO16_OD_RESET
PADS_BANK0_GPIO16_OFFSET
PADS_BANK0_GPIO16_PDE_ACCESS
PADS_BANK0_GPIO16_PDE_BITS
PADS_BANK0_GPIO16_PDE_LSB
PADS_BANK0_GPIO16_PDE_MSB
PADS_BANK0_GPIO16_PDE_RESET
PADS_BANK0_GPIO16_PUE_ACCESS
PADS_BANK0_GPIO16_PUE_BITS
PADS_BANK0_GPIO16_PUE_LSB
PADS_BANK0_GPIO16_PUE_MSB
PADS_BANK0_GPIO16_PUE_RESET
PADS_BANK0_GPIO16_RESET
PADS_BANK0_GPIO16_SCHMITT_ACCESS
PADS_BANK0_GPIO16_SCHMITT_BITS
PADS_BANK0_GPIO16_SCHMITT_LSB
PADS_BANK0_GPIO16_SCHMITT_MSB
PADS_BANK0_GPIO16_SCHMITT_RESET
PADS_BANK0_GPIO16_SLEWFAST_ACCESS
PADS_BANK0_GPIO16_SLEWFAST_BITS
PADS_BANK0_GPIO16_SLEWFAST_LSB
PADS_BANK0_GPIO16_SLEWFAST_MSB
PADS_BANK0_GPIO16_SLEWFAST_RESET
PADS_BANK0_GPIO17_BITS
PADS_BANK0_GPIO17_DRIVE_ACCESS
PADS_BANK0_GPIO17_DRIVE_BITS
PADS_BANK0_GPIO17_DRIVE_LSB
PADS_BANK0_GPIO17_DRIVE_MSB
PADS_BANK0_GPIO17_DRIVE_RESET
PADS_BANK0_GPIO17_DRIVE_VALUE_2MA
PADS_BANK0_GPIO17_DRIVE_VALUE_4MA
PADS_BANK0_GPIO17_DRIVE_VALUE_8MA
PADS_BANK0_GPIO17_DRIVE_VALUE_12MA
PADS_BANK0_GPIO17_IE_ACCESS
PADS_BANK0_GPIO17_IE_BITS
PADS_BANK0_GPIO17_IE_LSB
PADS_BANK0_GPIO17_IE_MSB
PADS_BANK0_GPIO17_IE_RESET
PADS_BANK0_GPIO17_OD_ACCESS
PADS_BANK0_GPIO17_OD_BITS
PADS_BANK0_GPIO17_OD_LSB
PADS_BANK0_GPIO17_OD_MSB
PADS_BANK0_GPIO17_OD_RESET
PADS_BANK0_GPIO17_OFFSET
PADS_BANK0_GPIO17_PDE_ACCESS
PADS_BANK0_GPIO17_PDE_BITS
PADS_BANK0_GPIO17_PDE_LSB
PADS_BANK0_GPIO17_PDE_MSB
PADS_BANK0_GPIO17_PDE_RESET
PADS_BANK0_GPIO17_PUE_ACCESS
PADS_BANK0_GPIO17_PUE_BITS
PADS_BANK0_GPIO17_PUE_LSB
PADS_BANK0_GPIO17_PUE_MSB
PADS_BANK0_GPIO17_PUE_RESET
PADS_BANK0_GPIO17_RESET
PADS_BANK0_GPIO17_SCHMITT_ACCESS
PADS_BANK0_GPIO17_SCHMITT_BITS
PADS_BANK0_GPIO17_SCHMITT_LSB
PADS_BANK0_GPIO17_SCHMITT_MSB
PADS_BANK0_GPIO17_SCHMITT_RESET
PADS_BANK0_GPIO17_SLEWFAST_ACCESS
PADS_BANK0_GPIO17_SLEWFAST_BITS
PADS_BANK0_GPIO17_SLEWFAST_LSB
PADS_BANK0_GPIO17_SLEWFAST_MSB
PADS_BANK0_GPIO17_SLEWFAST_RESET
PADS_BANK0_GPIO18_BITS
PADS_BANK0_GPIO18_DRIVE_ACCESS
PADS_BANK0_GPIO18_DRIVE_BITS
PADS_BANK0_GPIO18_DRIVE_LSB
PADS_BANK0_GPIO18_DRIVE_MSB
PADS_BANK0_GPIO18_DRIVE_RESET
PADS_BANK0_GPIO18_DRIVE_VALUE_2MA
PADS_BANK0_GPIO18_DRIVE_VALUE_4MA
PADS_BANK0_GPIO18_DRIVE_VALUE_8MA
PADS_BANK0_GPIO18_DRIVE_VALUE_12MA
PADS_BANK0_GPIO18_IE_ACCESS
PADS_BANK0_GPIO18_IE_BITS
PADS_BANK0_GPIO18_IE_LSB
PADS_BANK0_GPIO18_IE_MSB
PADS_BANK0_GPIO18_IE_RESET
PADS_BANK0_GPIO18_OD_ACCESS
PADS_BANK0_GPIO18_OD_BITS
PADS_BANK0_GPIO18_OD_LSB
PADS_BANK0_GPIO18_OD_MSB
PADS_BANK0_GPIO18_OD_RESET
PADS_BANK0_GPIO18_OFFSET
PADS_BANK0_GPIO18_PDE_ACCESS
PADS_BANK0_GPIO18_PDE_BITS
PADS_BANK0_GPIO18_PDE_LSB
PADS_BANK0_GPIO18_PDE_MSB
PADS_BANK0_GPIO18_PDE_RESET
PADS_BANK0_GPIO18_PUE_ACCESS
PADS_BANK0_GPIO18_PUE_BITS
PADS_BANK0_GPIO18_PUE_LSB
PADS_BANK0_GPIO18_PUE_MSB
PADS_BANK0_GPIO18_PUE_RESET
PADS_BANK0_GPIO18_RESET
PADS_BANK0_GPIO18_SCHMITT_ACCESS
PADS_BANK0_GPIO18_SCHMITT_BITS
PADS_BANK0_GPIO18_SCHMITT_LSB
PADS_BANK0_GPIO18_SCHMITT_MSB
PADS_BANK0_GPIO18_SCHMITT_RESET
PADS_BANK0_GPIO18_SLEWFAST_ACCESS
PADS_BANK0_GPIO18_SLEWFAST_BITS
PADS_BANK0_GPIO18_SLEWFAST_LSB
PADS_BANK0_GPIO18_SLEWFAST_MSB
PADS_BANK0_GPIO18_SLEWFAST_RESET
PADS_BANK0_GPIO19_BITS
PADS_BANK0_GPIO19_DRIVE_ACCESS
PADS_BANK0_GPIO19_DRIVE_BITS
PADS_BANK0_GPIO19_DRIVE_LSB
PADS_BANK0_GPIO19_DRIVE_MSB
PADS_BANK0_GPIO19_DRIVE_RESET
PADS_BANK0_GPIO19_DRIVE_VALUE_2MA
PADS_BANK0_GPIO19_DRIVE_VALUE_4MA
PADS_BANK0_GPIO19_DRIVE_VALUE_8MA
PADS_BANK0_GPIO19_DRIVE_VALUE_12MA
PADS_BANK0_GPIO19_IE_ACCESS
PADS_BANK0_GPIO19_IE_BITS
PADS_BANK0_GPIO19_IE_LSB
PADS_BANK0_GPIO19_IE_MSB
PADS_BANK0_GPIO19_IE_RESET
PADS_BANK0_GPIO19_OD_ACCESS
PADS_BANK0_GPIO19_OD_BITS
PADS_BANK0_GPIO19_OD_LSB
PADS_BANK0_GPIO19_OD_MSB
PADS_BANK0_GPIO19_OD_RESET
PADS_BANK0_GPIO19_OFFSET
PADS_BANK0_GPIO19_PDE_ACCESS
PADS_BANK0_GPIO19_PDE_BITS
PADS_BANK0_GPIO19_PDE_LSB
PADS_BANK0_GPIO19_PDE_MSB
PADS_BANK0_GPIO19_PDE_RESET
PADS_BANK0_GPIO19_PUE_ACCESS
PADS_BANK0_GPIO19_PUE_BITS
PADS_BANK0_GPIO19_PUE_LSB
PADS_BANK0_GPIO19_PUE_MSB
PADS_BANK0_GPIO19_PUE_RESET
PADS_BANK0_GPIO19_RESET
PADS_BANK0_GPIO19_SCHMITT_ACCESS
PADS_BANK0_GPIO19_SCHMITT_BITS
PADS_BANK0_GPIO19_SCHMITT_LSB
PADS_BANK0_GPIO19_SCHMITT_MSB
PADS_BANK0_GPIO19_SCHMITT_RESET
PADS_BANK0_GPIO19_SLEWFAST_ACCESS
PADS_BANK0_GPIO19_SLEWFAST_BITS
PADS_BANK0_GPIO19_SLEWFAST_LSB
PADS_BANK0_GPIO19_SLEWFAST_MSB
PADS_BANK0_GPIO19_SLEWFAST_RESET
PADS_BANK0_GPIO20_BITS
PADS_BANK0_GPIO20_DRIVE_ACCESS
PADS_BANK0_GPIO20_DRIVE_BITS
PADS_BANK0_GPIO20_DRIVE_LSB
PADS_BANK0_GPIO20_DRIVE_MSB
PADS_BANK0_GPIO20_DRIVE_RESET
PADS_BANK0_GPIO20_DRIVE_VALUE_2MA
PADS_BANK0_GPIO20_DRIVE_VALUE_4MA
PADS_BANK0_GPIO20_DRIVE_VALUE_8MA
PADS_BANK0_GPIO20_DRIVE_VALUE_12MA
PADS_BANK0_GPIO20_IE_ACCESS
PADS_BANK0_GPIO20_IE_BITS
PADS_BANK0_GPIO20_IE_LSB
PADS_BANK0_GPIO20_IE_MSB
PADS_BANK0_GPIO20_IE_RESET
PADS_BANK0_GPIO20_OD_ACCESS
PADS_BANK0_GPIO20_OD_BITS
PADS_BANK0_GPIO20_OD_LSB
PADS_BANK0_GPIO20_OD_MSB
PADS_BANK0_GPIO20_OD_RESET
PADS_BANK0_GPIO20_OFFSET
PADS_BANK0_GPIO20_PDE_ACCESS
PADS_BANK0_GPIO20_PDE_BITS
PADS_BANK0_GPIO20_PDE_LSB
PADS_BANK0_GPIO20_PDE_MSB
PADS_BANK0_GPIO20_PDE_RESET
PADS_BANK0_GPIO20_PUE_ACCESS
PADS_BANK0_GPIO20_PUE_BITS
PADS_BANK0_GPIO20_PUE_LSB
PADS_BANK0_GPIO20_PUE_MSB
PADS_BANK0_GPIO20_PUE_RESET
PADS_BANK0_GPIO20_RESET
PADS_BANK0_GPIO20_SCHMITT_ACCESS
PADS_BANK0_GPIO20_SCHMITT_BITS
PADS_BANK0_GPIO20_SCHMITT_LSB
PADS_BANK0_GPIO20_SCHMITT_MSB
PADS_BANK0_GPIO20_SCHMITT_RESET
PADS_BANK0_GPIO20_SLEWFAST_ACCESS
PADS_BANK0_GPIO20_SLEWFAST_BITS
PADS_BANK0_GPIO20_SLEWFAST_LSB
PADS_BANK0_GPIO20_SLEWFAST_MSB
PADS_BANK0_GPIO20_SLEWFAST_RESET
PADS_BANK0_GPIO21_BITS
PADS_BANK0_GPIO21_DRIVE_ACCESS
PADS_BANK0_GPIO21_DRIVE_BITS
PADS_BANK0_GPIO21_DRIVE_LSB
PADS_BANK0_GPIO21_DRIVE_MSB
PADS_BANK0_GPIO21_DRIVE_RESET
PADS_BANK0_GPIO21_DRIVE_VALUE_2MA
PADS_BANK0_GPIO21_DRIVE_VALUE_4MA
PADS_BANK0_GPIO21_DRIVE_VALUE_8MA
PADS_BANK0_GPIO21_DRIVE_VALUE_12MA
PADS_BANK0_GPIO21_IE_ACCESS
PADS_BANK0_GPIO21_IE_BITS
PADS_BANK0_GPIO21_IE_LSB
PADS_BANK0_GPIO21_IE_MSB
PADS_BANK0_GPIO21_IE_RESET
PADS_BANK0_GPIO21_OD_ACCESS
PADS_BANK0_GPIO21_OD_BITS
PADS_BANK0_GPIO21_OD_LSB
PADS_BANK0_GPIO21_OD_MSB
PADS_BANK0_GPIO21_OD_RESET
PADS_BANK0_GPIO21_OFFSET
PADS_BANK0_GPIO21_PDE_ACCESS
PADS_BANK0_GPIO21_PDE_BITS
PADS_BANK0_GPIO21_PDE_LSB
PADS_BANK0_GPIO21_PDE_MSB
PADS_BANK0_GPIO21_PDE_RESET
PADS_BANK0_GPIO21_PUE_ACCESS
PADS_BANK0_GPIO21_PUE_BITS
PADS_BANK0_GPIO21_PUE_LSB
PADS_BANK0_GPIO21_PUE_MSB
PADS_BANK0_GPIO21_PUE_RESET
PADS_BANK0_GPIO21_RESET
PADS_BANK0_GPIO21_SCHMITT_ACCESS
PADS_BANK0_GPIO21_SCHMITT_BITS
PADS_BANK0_GPIO21_SCHMITT_LSB
PADS_BANK0_GPIO21_SCHMITT_MSB
PADS_BANK0_GPIO21_SCHMITT_RESET
PADS_BANK0_GPIO21_SLEWFAST_ACCESS
PADS_BANK0_GPIO21_SLEWFAST_BITS
PADS_BANK0_GPIO21_SLEWFAST_LSB
PADS_BANK0_GPIO21_SLEWFAST_MSB
PADS_BANK0_GPIO21_SLEWFAST_RESET
PADS_BANK0_GPIO22_BITS
PADS_BANK0_GPIO22_DRIVE_ACCESS
PADS_BANK0_GPIO22_DRIVE_BITS
PADS_BANK0_GPIO22_DRIVE_LSB
PADS_BANK0_GPIO22_DRIVE_MSB
PADS_BANK0_GPIO22_DRIVE_RESET
PADS_BANK0_GPIO22_DRIVE_VALUE_2MA
PADS_BANK0_GPIO22_DRIVE_VALUE_4MA
PADS_BANK0_GPIO22_DRIVE_VALUE_8MA
PADS_BANK0_GPIO22_DRIVE_VALUE_12MA
PADS_BANK0_GPIO22_IE_ACCESS
PADS_BANK0_GPIO22_IE_BITS
PADS_BANK0_GPIO22_IE_LSB
PADS_BANK0_GPIO22_IE_MSB
PADS_BANK0_GPIO22_IE_RESET
PADS_BANK0_GPIO22_OD_ACCESS
PADS_BANK0_GPIO22_OD_BITS
PADS_BANK0_GPIO22_OD_LSB
PADS_BANK0_GPIO22_OD_MSB
PADS_BANK0_GPIO22_OD_RESET
PADS_BANK0_GPIO22_OFFSET
PADS_BANK0_GPIO22_PDE_ACCESS
PADS_BANK0_GPIO22_PDE_BITS
PADS_BANK0_GPIO22_PDE_LSB
PADS_BANK0_GPIO22_PDE_MSB
PADS_BANK0_GPIO22_PDE_RESET
PADS_BANK0_GPIO22_PUE_ACCESS
PADS_BANK0_GPIO22_PUE_BITS
PADS_BANK0_GPIO22_PUE_LSB
PADS_BANK0_GPIO22_PUE_MSB
PADS_BANK0_GPIO22_PUE_RESET
PADS_BANK0_GPIO22_RESET
PADS_BANK0_GPIO22_SCHMITT_ACCESS
PADS_BANK0_GPIO22_SCHMITT_BITS
PADS_BANK0_GPIO22_SCHMITT_LSB
PADS_BANK0_GPIO22_SCHMITT_MSB
PADS_BANK0_GPIO22_SCHMITT_RESET
PADS_BANK0_GPIO22_SLEWFAST_ACCESS
PADS_BANK0_GPIO22_SLEWFAST_BITS
PADS_BANK0_GPIO22_SLEWFAST_LSB
PADS_BANK0_GPIO22_SLEWFAST_MSB
PADS_BANK0_GPIO22_SLEWFAST_RESET
PADS_BANK0_GPIO23_BITS
PADS_BANK0_GPIO23_DRIVE_ACCESS
PADS_BANK0_GPIO23_DRIVE_BITS
PADS_BANK0_GPIO23_DRIVE_LSB
PADS_BANK0_GPIO23_DRIVE_MSB
PADS_BANK0_GPIO23_DRIVE_RESET
PADS_BANK0_GPIO23_DRIVE_VALUE_2MA
PADS_BANK0_GPIO23_DRIVE_VALUE_4MA
PADS_BANK0_GPIO23_DRIVE_VALUE_8MA
PADS_BANK0_GPIO23_DRIVE_VALUE_12MA
PADS_BANK0_GPIO23_IE_ACCESS
PADS_BANK0_GPIO23_IE_BITS
PADS_BANK0_GPIO23_IE_LSB
PADS_BANK0_GPIO23_IE_MSB
PADS_BANK0_GPIO23_IE_RESET
PADS_BANK0_GPIO23_OD_ACCESS
PADS_BANK0_GPIO23_OD_BITS
PADS_BANK0_GPIO23_OD_LSB
PADS_BANK0_GPIO23_OD_MSB
PADS_BANK0_GPIO23_OD_RESET
PADS_BANK0_GPIO23_OFFSET
PADS_BANK0_GPIO23_PDE_ACCESS
PADS_BANK0_GPIO23_PDE_BITS
PADS_BANK0_GPIO23_PDE_LSB
PADS_BANK0_GPIO23_PDE_MSB
PADS_BANK0_GPIO23_PDE_RESET
PADS_BANK0_GPIO23_PUE_ACCESS
PADS_BANK0_GPIO23_PUE_BITS
PADS_BANK0_GPIO23_PUE_LSB
PADS_BANK0_GPIO23_PUE_MSB
PADS_BANK0_GPIO23_PUE_RESET
PADS_BANK0_GPIO23_RESET
PADS_BANK0_GPIO23_SCHMITT_ACCESS
PADS_BANK0_GPIO23_SCHMITT_BITS
PADS_BANK0_GPIO23_SCHMITT_LSB
PADS_BANK0_GPIO23_SCHMITT_MSB
PADS_BANK0_GPIO23_SCHMITT_RESET
PADS_BANK0_GPIO23_SLEWFAST_ACCESS
PADS_BANK0_GPIO23_SLEWFAST_BITS
PADS_BANK0_GPIO23_SLEWFAST_LSB
PADS_BANK0_GPIO23_SLEWFAST_MSB
PADS_BANK0_GPIO23_SLEWFAST_RESET
PADS_BANK0_GPIO24_BITS
PADS_BANK0_GPIO24_DRIVE_ACCESS
PADS_BANK0_GPIO24_DRIVE_BITS
PADS_BANK0_GPIO24_DRIVE_LSB
PADS_BANK0_GPIO24_DRIVE_MSB
PADS_BANK0_GPIO24_DRIVE_RESET
PADS_BANK0_GPIO24_DRIVE_VALUE_2MA
PADS_BANK0_GPIO24_DRIVE_VALUE_4MA
PADS_BANK0_GPIO24_DRIVE_VALUE_8MA
PADS_BANK0_GPIO24_DRIVE_VALUE_12MA
PADS_BANK0_GPIO24_IE_ACCESS
PADS_BANK0_GPIO24_IE_BITS
PADS_BANK0_GPIO24_IE_LSB
PADS_BANK0_GPIO24_IE_MSB
PADS_BANK0_GPIO24_IE_RESET
PADS_BANK0_GPIO24_OD_ACCESS
PADS_BANK0_GPIO24_OD_BITS
PADS_BANK0_GPIO24_OD_LSB
PADS_BANK0_GPIO24_OD_MSB
PADS_BANK0_GPIO24_OD_RESET
PADS_BANK0_GPIO24_OFFSET
PADS_BANK0_GPIO24_PDE_ACCESS
PADS_BANK0_GPIO24_PDE_BITS
PADS_BANK0_GPIO24_PDE_LSB
PADS_BANK0_GPIO24_PDE_MSB
PADS_BANK0_GPIO24_PDE_RESET
PADS_BANK0_GPIO24_PUE_ACCESS
PADS_BANK0_GPIO24_PUE_BITS
PADS_BANK0_GPIO24_PUE_LSB
PADS_BANK0_GPIO24_PUE_MSB
PADS_BANK0_GPIO24_PUE_RESET
PADS_BANK0_GPIO24_RESET
PADS_BANK0_GPIO24_SCHMITT_ACCESS
PADS_BANK0_GPIO24_SCHMITT_BITS
PADS_BANK0_GPIO24_SCHMITT_LSB
PADS_BANK0_GPIO24_SCHMITT_MSB
PADS_BANK0_GPIO24_SCHMITT_RESET
PADS_BANK0_GPIO24_SLEWFAST_ACCESS
PADS_BANK0_GPIO24_SLEWFAST_BITS
PADS_BANK0_GPIO24_SLEWFAST_LSB
PADS_BANK0_GPIO24_SLEWFAST_MSB
PADS_BANK0_GPIO24_SLEWFAST_RESET
PADS_BANK0_GPIO25_BITS
PADS_BANK0_GPIO25_DRIVE_ACCESS
PADS_BANK0_GPIO25_DRIVE_BITS
PADS_BANK0_GPIO25_DRIVE_LSB
PADS_BANK0_GPIO25_DRIVE_MSB
PADS_BANK0_GPIO25_DRIVE_RESET
PADS_BANK0_GPIO25_DRIVE_VALUE_2MA
PADS_BANK0_GPIO25_DRIVE_VALUE_4MA
PADS_BANK0_GPIO25_DRIVE_VALUE_8MA
PADS_BANK0_GPIO25_DRIVE_VALUE_12MA
PADS_BANK0_GPIO25_IE_ACCESS
PADS_BANK0_GPIO25_IE_BITS
PADS_BANK0_GPIO25_IE_LSB
PADS_BANK0_GPIO25_IE_MSB
PADS_BANK0_GPIO25_IE_RESET
PADS_BANK0_GPIO25_OD_ACCESS
PADS_BANK0_GPIO25_OD_BITS
PADS_BANK0_GPIO25_OD_LSB
PADS_BANK0_GPIO25_OD_MSB
PADS_BANK0_GPIO25_OD_RESET
PADS_BANK0_GPIO25_OFFSET
PADS_BANK0_GPIO25_PDE_ACCESS
PADS_BANK0_GPIO25_PDE_BITS
PADS_BANK0_GPIO25_PDE_LSB
PADS_BANK0_GPIO25_PDE_MSB
PADS_BANK0_GPIO25_PDE_RESET
PADS_BANK0_GPIO25_PUE_ACCESS
PADS_BANK0_GPIO25_PUE_BITS
PADS_BANK0_GPIO25_PUE_LSB
PADS_BANK0_GPIO25_PUE_MSB
PADS_BANK0_GPIO25_PUE_RESET
PADS_BANK0_GPIO25_RESET
PADS_BANK0_GPIO25_SCHMITT_ACCESS
PADS_BANK0_GPIO25_SCHMITT_BITS
PADS_BANK0_GPIO25_SCHMITT_LSB
PADS_BANK0_GPIO25_SCHMITT_MSB
PADS_BANK0_GPIO25_SCHMITT_RESET
PADS_BANK0_GPIO25_SLEWFAST_ACCESS
PADS_BANK0_GPIO25_SLEWFAST_BITS
PADS_BANK0_GPIO25_SLEWFAST_LSB
PADS_BANK0_GPIO25_SLEWFAST_MSB
PADS_BANK0_GPIO25_SLEWFAST_RESET
PADS_BANK0_GPIO26_BITS
PADS_BANK0_GPIO26_DRIVE_ACCESS
PADS_BANK0_GPIO26_DRIVE_BITS
PADS_BANK0_GPIO26_DRIVE_LSB
PADS_BANK0_GPIO26_DRIVE_MSB
PADS_BANK0_GPIO26_DRIVE_RESET
PADS_BANK0_GPIO26_DRIVE_VALUE_2MA
PADS_BANK0_GPIO26_DRIVE_VALUE_4MA
PADS_BANK0_GPIO26_DRIVE_VALUE_8MA
PADS_BANK0_GPIO26_DRIVE_VALUE_12MA
PADS_BANK0_GPIO26_IE_ACCESS
PADS_BANK0_GPIO26_IE_BITS
PADS_BANK0_GPIO26_IE_LSB
PADS_BANK0_GPIO26_IE_MSB
PADS_BANK0_GPIO26_IE_RESET
PADS_BANK0_GPIO26_OD_ACCESS
PADS_BANK0_GPIO26_OD_BITS
PADS_BANK0_GPIO26_OD_LSB
PADS_BANK0_GPIO26_OD_MSB
PADS_BANK0_GPIO26_OD_RESET
PADS_BANK0_GPIO26_OFFSET
PADS_BANK0_GPIO26_PDE_ACCESS
PADS_BANK0_GPIO26_PDE_BITS
PADS_BANK0_GPIO26_PDE_LSB
PADS_BANK0_GPIO26_PDE_MSB
PADS_BANK0_GPIO26_PDE_RESET
PADS_BANK0_GPIO26_PUE_ACCESS
PADS_BANK0_GPIO26_PUE_BITS
PADS_BANK0_GPIO26_PUE_LSB
PADS_BANK0_GPIO26_PUE_MSB
PADS_BANK0_GPIO26_PUE_RESET
PADS_BANK0_GPIO26_RESET
PADS_BANK0_GPIO26_SCHMITT_ACCESS
PADS_BANK0_GPIO26_SCHMITT_BITS
PADS_BANK0_GPIO26_SCHMITT_LSB
PADS_BANK0_GPIO26_SCHMITT_MSB
PADS_BANK0_GPIO26_SCHMITT_RESET
PADS_BANK0_GPIO26_SLEWFAST_ACCESS
PADS_BANK0_GPIO26_SLEWFAST_BITS
PADS_BANK0_GPIO26_SLEWFAST_LSB
PADS_BANK0_GPIO26_SLEWFAST_MSB
PADS_BANK0_GPIO26_SLEWFAST_RESET
PADS_BANK0_GPIO27_BITS
PADS_BANK0_GPIO27_DRIVE_ACCESS
PADS_BANK0_GPIO27_DRIVE_BITS
PADS_BANK0_GPIO27_DRIVE_LSB
PADS_BANK0_GPIO27_DRIVE_MSB
PADS_BANK0_GPIO27_DRIVE_RESET
PADS_BANK0_GPIO27_DRIVE_VALUE_2MA
PADS_BANK0_GPIO27_DRIVE_VALUE_4MA
PADS_BANK0_GPIO27_DRIVE_VALUE_8MA
PADS_BANK0_GPIO27_DRIVE_VALUE_12MA
PADS_BANK0_GPIO27_IE_ACCESS
PADS_BANK0_GPIO27_IE_BITS
PADS_BANK0_GPIO27_IE_LSB
PADS_BANK0_GPIO27_IE_MSB
PADS_BANK0_GPIO27_IE_RESET
PADS_BANK0_GPIO27_OD_ACCESS
PADS_BANK0_GPIO27_OD_BITS
PADS_BANK0_GPIO27_OD_LSB
PADS_BANK0_GPIO27_OD_MSB
PADS_BANK0_GPIO27_OD_RESET
PADS_BANK0_GPIO27_OFFSET
PADS_BANK0_GPIO27_PDE_ACCESS
PADS_BANK0_GPIO27_PDE_BITS
PADS_BANK0_GPIO27_PDE_LSB
PADS_BANK0_GPIO27_PDE_MSB
PADS_BANK0_GPIO27_PDE_RESET
PADS_BANK0_GPIO27_PUE_ACCESS
PADS_BANK0_GPIO27_PUE_BITS
PADS_BANK0_GPIO27_PUE_LSB
PADS_BANK0_GPIO27_PUE_MSB
PADS_BANK0_GPIO27_PUE_RESET
PADS_BANK0_GPIO27_RESET
PADS_BANK0_GPIO27_SCHMITT_ACCESS
PADS_BANK0_GPIO27_SCHMITT_BITS
PADS_BANK0_GPIO27_SCHMITT_LSB
PADS_BANK0_GPIO27_SCHMITT_MSB
PADS_BANK0_GPIO27_SCHMITT_RESET
PADS_BANK0_GPIO27_SLEWFAST_ACCESS
PADS_BANK0_GPIO27_SLEWFAST_BITS
PADS_BANK0_GPIO27_SLEWFAST_LSB
PADS_BANK0_GPIO27_SLEWFAST_MSB
PADS_BANK0_GPIO27_SLEWFAST_RESET
PADS_BANK0_GPIO28_BITS
PADS_BANK0_GPIO28_DRIVE_ACCESS
PADS_BANK0_GPIO28_DRIVE_BITS
PADS_BANK0_GPIO28_DRIVE_LSB
PADS_BANK0_GPIO28_DRIVE_MSB
PADS_BANK0_GPIO28_DRIVE_RESET
PADS_BANK0_GPIO28_DRIVE_VALUE_2MA
PADS_BANK0_GPIO28_DRIVE_VALUE_4MA
PADS_BANK0_GPIO28_DRIVE_VALUE_8MA
PADS_BANK0_GPIO28_DRIVE_VALUE_12MA
PADS_BANK0_GPIO28_IE_ACCESS
PADS_BANK0_GPIO28_IE_BITS
PADS_BANK0_GPIO28_IE_LSB
PADS_BANK0_GPIO28_IE_MSB
PADS_BANK0_GPIO28_IE_RESET
PADS_BANK0_GPIO28_OD_ACCESS
PADS_BANK0_GPIO28_OD_BITS
PADS_BANK0_GPIO28_OD_LSB
PADS_BANK0_GPIO28_OD_MSB
PADS_BANK0_GPIO28_OD_RESET
PADS_BANK0_GPIO28_OFFSET
PADS_BANK0_GPIO28_PDE_ACCESS
PADS_BANK0_GPIO28_PDE_BITS
PADS_BANK0_GPIO28_PDE_LSB
PADS_BANK0_GPIO28_PDE_MSB
PADS_BANK0_GPIO28_PDE_RESET
PADS_BANK0_GPIO28_PUE_ACCESS
PADS_BANK0_GPIO28_PUE_BITS
PADS_BANK0_GPIO28_PUE_LSB
PADS_BANK0_GPIO28_PUE_MSB
PADS_BANK0_GPIO28_PUE_RESET
PADS_BANK0_GPIO28_RESET
PADS_BANK0_GPIO28_SCHMITT_ACCESS
PADS_BANK0_GPIO28_SCHMITT_BITS
PADS_BANK0_GPIO28_SCHMITT_LSB
PADS_BANK0_GPIO28_SCHMITT_MSB
PADS_BANK0_GPIO28_SCHMITT_RESET
PADS_BANK0_GPIO28_SLEWFAST_ACCESS
PADS_BANK0_GPIO28_SLEWFAST_BITS
PADS_BANK0_GPIO28_SLEWFAST_LSB
PADS_BANK0_GPIO28_SLEWFAST_MSB
PADS_BANK0_GPIO28_SLEWFAST_RESET
PADS_BANK0_GPIO29_BITS
PADS_BANK0_GPIO29_DRIVE_ACCESS
PADS_BANK0_GPIO29_DRIVE_BITS
PADS_BANK0_GPIO29_DRIVE_LSB
PADS_BANK0_GPIO29_DRIVE_MSB
PADS_BANK0_GPIO29_DRIVE_RESET
PADS_BANK0_GPIO29_DRIVE_VALUE_2MA
PADS_BANK0_GPIO29_DRIVE_VALUE_4MA
PADS_BANK0_GPIO29_DRIVE_VALUE_8MA
PADS_BANK0_GPIO29_DRIVE_VALUE_12MA
PADS_BANK0_GPIO29_IE_ACCESS
PADS_BANK0_GPIO29_IE_BITS
PADS_BANK0_GPIO29_IE_LSB
PADS_BANK0_GPIO29_IE_MSB
PADS_BANK0_GPIO29_IE_RESET
PADS_BANK0_GPIO29_OD_ACCESS
PADS_BANK0_GPIO29_OD_BITS
PADS_BANK0_GPIO29_OD_LSB
PADS_BANK0_GPIO29_OD_MSB
PADS_BANK0_GPIO29_OD_RESET
PADS_BANK0_GPIO29_OFFSET
PADS_BANK0_GPIO29_PDE_ACCESS
PADS_BANK0_GPIO29_PDE_BITS
PADS_BANK0_GPIO29_PDE_LSB
PADS_BANK0_GPIO29_PDE_MSB
PADS_BANK0_GPIO29_PDE_RESET
PADS_BANK0_GPIO29_PUE_ACCESS
PADS_BANK0_GPIO29_PUE_BITS
PADS_BANK0_GPIO29_PUE_LSB
PADS_BANK0_GPIO29_PUE_MSB
PADS_BANK0_GPIO29_PUE_RESET
PADS_BANK0_GPIO29_RESET
PADS_BANK0_GPIO29_SCHMITT_ACCESS
PADS_BANK0_GPIO29_SCHMITT_BITS
PADS_BANK0_GPIO29_SCHMITT_LSB
PADS_BANK0_GPIO29_SCHMITT_MSB
PADS_BANK0_GPIO29_SCHMITT_RESET
PADS_BANK0_GPIO29_SLEWFAST_ACCESS
PADS_BANK0_GPIO29_SLEWFAST_BITS
PADS_BANK0_GPIO29_SLEWFAST_LSB
PADS_BANK0_GPIO29_SLEWFAST_MSB
PADS_BANK0_GPIO29_SLEWFAST_RESET
PADS_BANK0_SWCLK_BITS
PADS_BANK0_SWCLK_DRIVE_ACCESS
PADS_BANK0_SWCLK_DRIVE_BITS
PADS_BANK0_SWCLK_DRIVE_LSB
PADS_BANK0_SWCLK_DRIVE_MSB
PADS_BANK0_SWCLK_DRIVE_RESET
PADS_BANK0_SWCLK_DRIVE_VALUE_2MA
PADS_BANK0_SWCLK_DRIVE_VALUE_4MA
PADS_BANK0_SWCLK_DRIVE_VALUE_8MA
PADS_BANK0_SWCLK_DRIVE_VALUE_12MA
PADS_BANK0_SWCLK_IE_ACCESS
PADS_BANK0_SWCLK_IE_BITS
PADS_BANK0_SWCLK_IE_LSB
PADS_BANK0_SWCLK_IE_MSB
PADS_BANK0_SWCLK_IE_RESET
PADS_BANK0_SWCLK_OD_ACCESS
PADS_BANK0_SWCLK_OD_BITS
PADS_BANK0_SWCLK_OD_LSB
PADS_BANK0_SWCLK_OD_MSB
PADS_BANK0_SWCLK_OD_RESET
PADS_BANK0_SWCLK_OFFSET
PADS_BANK0_SWCLK_PDE_ACCESS
PADS_BANK0_SWCLK_PDE_BITS
PADS_BANK0_SWCLK_PDE_LSB
PADS_BANK0_SWCLK_PDE_MSB
PADS_BANK0_SWCLK_PDE_RESET
PADS_BANK0_SWCLK_PUE_ACCESS
PADS_BANK0_SWCLK_PUE_BITS
PADS_BANK0_SWCLK_PUE_LSB
PADS_BANK0_SWCLK_PUE_MSB
PADS_BANK0_SWCLK_PUE_RESET
PADS_BANK0_SWCLK_RESET
PADS_BANK0_SWCLK_SCHMITT_ACCESS
PADS_BANK0_SWCLK_SCHMITT_BITS
PADS_BANK0_SWCLK_SCHMITT_LSB
PADS_BANK0_SWCLK_SCHMITT_MSB
PADS_BANK0_SWCLK_SCHMITT_RESET
PADS_BANK0_SWCLK_SLEWFAST_ACCESS
PADS_BANK0_SWCLK_SLEWFAST_BITS
PADS_BANK0_SWCLK_SLEWFAST_LSB
PADS_BANK0_SWCLK_SLEWFAST_MSB
PADS_BANK0_SWCLK_SLEWFAST_RESET
PADS_BANK0_SWD_BITS
PADS_BANK0_SWD_DRIVE_ACCESS
PADS_BANK0_SWD_DRIVE_BITS
PADS_BANK0_SWD_DRIVE_LSB
PADS_BANK0_SWD_DRIVE_MSB
PADS_BANK0_SWD_DRIVE_RESET
PADS_BANK0_SWD_DRIVE_VALUE_2MA
PADS_BANK0_SWD_DRIVE_VALUE_4MA
PADS_BANK0_SWD_DRIVE_VALUE_8MA
PADS_BANK0_SWD_DRIVE_VALUE_12MA
PADS_BANK0_SWD_IE_ACCESS
PADS_BANK0_SWD_IE_BITS
PADS_BANK0_SWD_IE_LSB
PADS_BANK0_SWD_IE_MSB
PADS_BANK0_SWD_IE_RESET
PADS_BANK0_SWD_OD_ACCESS
PADS_BANK0_SWD_OD_BITS
PADS_BANK0_SWD_OD_LSB
PADS_BANK0_SWD_OD_MSB
PADS_BANK0_SWD_OD_RESET
PADS_BANK0_SWD_OFFSET
PADS_BANK0_SWD_PDE_ACCESS
PADS_BANK0_SWD_PDE_BITS
PADS_BANK0_SWD_PDE_LSB
PADS_BANK0_SWD_PDE_MSB
PADS_BANK0_SWD_PDE_RESET
PADS_BANK0_SWD_PUE_ACCESS
PADS_BANK0_SWD_PUE_BITS
PADS_BANK0_SWD_PUE_LSB
PADS_BANK0_SWD_PUE_MSB
PADS_BANK0_SWD_PUE_RESET
PADS_BANK0_SWD_RESET
PADS_BANK0_SWD_SCHMITT_ACCESS
PADS_BANK0_SWD_SCHMITT_BITS
PADS_BANK0_SWD_SCHMITT_LSB
PADS_BANK0_SWD_SCHMITT_MSB
PADS_BANK0_SWD_SCHMITT_RESET
PADS_BANK0_SWD_SLEWFAST_ACCESS
PADS_BANK0_SWD_SLEWFAST_BITS
PADS_BANK0_SWD_SLEWFAST_LSB
PADS_BANK0_SWD_SLEWFAST_MSB
PADS_BANK0_SWD_SLEWFAST_RESET
PADS_BANK0_VOLTAGE_SELECT_ACCESS
PADS_BANK0_VOLTAGE_SELECT_BITS
PADS_BANK0_VOLTAGE_SELECT_LSB
PADS_BANK0_VOLTAGE_SELECT_MSB
PADS_BANK0_VOLTAGE_SELECT_OFFSET
PADS_BANK0_VOLTAGE_SELECT_RESET
PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8
PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3
PADS_QSPI_BASE
PARAM_ASSERTIONS_DISABLE_ALL
PARAM_ASSERTIONS_ENABLED_GPIO
PARAM_ASSERTIONS_ENABLED_TIME
PARAM_ASSERTIONS_ENABLED_TIMER
PARAM_ASSERTIONS_ENABLED_UART
PARAM_ASSERTIONS_ENABLE_ALL
PICO_DEBUG_PIN_BASE
PICO_DEBUG_PIN_COUNT
PICO_DEFAULT_LED_PIN
PICO_DEFAULT_UART
PICO_DEFAULT_UART_BAUD_RATE
PICO_DEFAULT_UART_RX_PIN
PICO_DEFAULT_UART_TX_PIN
PICO_DOUBLE_SUPPORT_ROM_V1
PICO_ERROR_GENERIC
PICO_ERROR_NONE
PICO_ERROR_NO_DATA
PICO_ERROR_TIMEOUT
PICO_FLASH_SIZE_BYTES
PICO_FLASH_SPI_CLKDIV
PICO_FLOAT_SUPPORT_ROM_V1
PICO_HEAP_SIZE
PICO_NO_RAM_VECTOR_TABLE
PICO_OK
PICO_SDK_VERSION_MAJOR
PICO_SDK_VERSION_MINOR
PICO_SDK_VERSION_REVISION
PICO_SDK_VERSION_STRING
PICO_SMPS_MODE_PIN
PICO_STACK_SIZE
PICO_STDIO_DEFAULT_CRLF
PICO_STDIO_ENABLE_CRLF_SUPPORT
PICO_STDIO_STACK_BUFFER_SIZE
PICO_STDOUT_MUTEX
PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS
PICO_TIME_SLEEP_OVERHEAD_ADJUST_US
PICO_UART_DEFAULT_CRLF
PICO_UART_ENABLE_CRLF_SUPPORT
PIO0_BASE
PIO1_BASE
PIO_INSTRUCTION_COUNT
PLL_SYS_BASE
PLL_USB_BASE
PPB_BASE
PSM_BASE
PWM_BASE
REG_ALIAS_CLR_BITS
REG_ALIAS_RW_BITS
REG_ALIAS_SET_BITS
REG_ALIAS_XOR_BITS
RESETS_BASE
ROM_BASE
ROSC_BASE
RSIZE_MAX
RTC_BASE
SIG_ATOMIC_MAX
SIG_ATOMIC_MIN
SIO_BASE
SIO_CPUID_ACCESS
SIO_CPUID_BITS
SIO_CPUID_LSB
SIO_CPUID_MSB
SIO_CPUID_OFFSET
SIO_CPUID_RESET
SIO_DIV_CSR_BITS
SIO_DIV_CSR_DIRTY_ACCESS
SIO_DIV_CSR_DIRTY_BITS
SIO_DIV_CSR_DIRTY_LSB
SIO_DIV_CSR_DIRTY_MSB
SIO_DIV_CSR_DIRTY_RESET
SIO_DIV_CSR_OFFSET
SIO_DIV_CSR_READY_ACCESS
SIO_DIV_CSR_READY_BITS
SIO_DIV_CSR_READY_LSB
SIO_DIV_CSR_READY_MSB
SIO_DIV_CSR_READY_RESET
SIO_DIV_CSR_RESET
SIO_DIV_QUOTIENT_ACCESS
SIO_DIV_QUOTIENT_BITS
SIO_DIV_QUOTIENT_LSB
SIO_DIV_QUOTIENT_MSB
SIO_DIV_QUOTIENT_OFFSET
SIO_DIV_QUOTIENT_RESET
SIO_DIV_REMAINDER_ACCESS
SIO_DIV_REMAINDER_BITS
SIO_DIV_REMAINDER_LSB
SIO_DIV_REMAINDER_MSB
SIO_DIV_REMAINDER_OFFSET
SIO_DIV_REMAINDER_RESET
SIO_DIV_SDIVIDEND_ACCESS
SIO_DIV_SDIVIDEND_BITS
SIO_DIV_SDIVIDEND_LSB
SIO_DIV_SDIVIDEND_MSB
SIO_DIV_SDIVIDEND_OFFSET
SIO_DIV_SDIVIDEND_RESET
SIO_DIV_SDIVISOR_ACCESS
SIO_DIV_SDIVISOR_BITS
SIO_DIV_SDIVISOR_LSB
SIO_DIV_SDIVISOR_MSB
SIO_DIV_SDIVISOR_OFFSET
SIO_DIV_SDIVISOR_RESET
SIO_DIV_UDIVIDEND_ACCESS
SIO_DIV_UDIVIDEND_BITS
SIO_DIV_UDIVIDEND_LSB
SIO_DIV_UDIVIDEND_MSB
SIO_DIV_UDIVIDEND_OFFSET
SIO_DIV_UDIVIDEND_RESET
SIO_DIV_UDIVISOR_ACCESS
SIO_DIV_UDIVISOR_BITS
SIO_DIV_UDIVISOR_LSB
SIO_DIV_UDIVISOR_MSB
SIO_DIV_UDIVISOR_OFFSET
SIO_DIV_UDIVISOR_RESET
SIO_FIFO_RD_ACCESS
SIO_FIFO_RD_BITS
SIO_FIFO_RD_LSB
SIO_FIFO_RD_MSB
SIO_FIFO_RD_OFFSET
SIO_FIFO_RD_RESET
SIO_FIFO_ST_BITS
SIO_FIFO_ST_OFFSET
SIO_FIFO_ST_RDY_ACCESS
SIO_FIFO_ST_RDY_BITS
SIO_FIFO_ST_RDY_LSB
SIO_FIFO_ST_RDY_MSB
SIO_FIFO_ST_RDY_RESET
SIO_FIFO_ST_RESET
SIO_FIFO_ST_ROE_ACCESS
SIO_FIFO_ST_ROE_BITS
SIO_FIFO_ST_ROE_LSB
SIO_FIFO_ST_ROE_MSB
SIO_FIFO_ST_ROE_RESET
SIO_FIFO_ST_VLD_ACCESS
SIO_FIFO_ST_VLD_BITS
SIO_FIFO_ST_VLD_LSB
SIO_FIFO_ST_VLD_MSB
SIO_FIFO_ST_VLD_RESET
SIO_FIFO_ST_WOF_ACCESS
SIO_FIFO_ST_WOF_BITS
SIO_FIFO_ST_WOF_LSB
SIO_FIFO_ST_WOF_MSB
SIO_FIFO_ST_WOF_RESET
SIO_FIFO_WR_ACCESS
SIO_FIFO_WR_BITS
SIO_FIFO_WR_LSB
SIO_FIFO_WR_MSB
SIO_FIFO_WR_OFFSET
SIO_FIFO_WR_RESET
SIO_GPIO_HI_IN_ACCESS
SIO_GPIO_HI_IN_BITS
SIO_GPIO_HI_IN_LSB
SIO_GPIO_HI_IN_MSB
SIO_GPIO_HI_IN_OFFSET
SIO_GPIO_HI_IN_RESET
SIO_GPIO_HI_OE_ACCESS
SIO_GPIO_HI_OE_BITS
SIO_GPIO_HI_OE_CLR_ACCESS
SIO_GPIO_HI_OE_CLR_BITS
SIO_GPIO_HI_OE_CLR_LSB
SIO_GPIO_HI_OE_CLR_MSB
SIO_GPIO_HI_OE_CLR_OFFSET
SIO_GPIO_HI_OE_CLR_RESET
SIO_GPIO_HI_OE_LSB
SIO_GPIO_HI_OE_MSB
SIO_GPIO_HI_OE_OFFSET
SIO_GPIO_HI_OE_RESET
SIO_GPIO_HI_OE_SET_ACCESS
SIO_GPIO_HI_OE_SET_BITS
SIO_GPIO_HI_OE_SET_LSB
SIO_GPIO_HI_OE_SET_MSB
SIO_GPIO_HI_OE_SET_OFFSET
SIO_GPIO_HI_OE_SET_RESET
SIO_GPIO_HI_OE_XOR_ACCESS
SIO_GPIO_HI_OE_XOR_BITS
SIO_GPIO_HI_OE_XOR_LSB
SIO_GPIO_HI_OE_XOR_MSB
SIO_GPIO_HI_OE_XOR_OFFSET
SIO_GPIO_HI_OE_XOR_RESET
SIO_GPIO_HI_OUT_ACCESS
SIO_GPIO_HI_OUT_BITS
SIO_GPIO_HI_OUT_CLR_ACCESS
SIO_GPIO_HI_OUT_CLR_BITS
SIO_GPIO_HI_OUT_CLR_LSB
SIO_GPIO_HI_OUT_CLR_MSB
SIO_GPIO_HI_OUT_CLR_OFFSET
SIO_GPIO_HI_OUT_CLR_RESET
SIO_GPIO_HI_OUT_LSB
SIO_GPIO_HI_OUT_MSB
SIO_GPIO_HI_OUT_OFFSET
SIO_GPIO_HI_OUT_RESET
SIO_GPIO_HI_OUT_SET_ACCESS
SIO_GPIO_HI_OUT_SET_BITS
SIO_GPIO_HI_OUT_SET_LSB
SIO_GPIO_HI_OUT_SET_MSB
SIO_GPIO_HI_OUT_SET_OFFSET
SIO_GPIO_HI_OUT_SET_RESET
SIO_GPIO_HI_OUT_XOR_ACCESS
SIO_GPIO_HI_OUT_XOR_BITS
SIO_GPIO_HI_OUT_XOR_LSB
SIO_GPIO_HI_OUT_XOR_MSB
SIO_GPIO_HI_OUT_XOR_OFFSET
SIO_GPIO_HI_OUT_XOR_RESET
SIO_GPIO_IN_ACCESS
SIO_GPIO_IN_BITS
SIO_GPIO_IN_LSB
SIO_GPIO_IN_MSB
SIO_GPIO_IN_OFFSET
SIO_GPIO_IN_RESET
SIO_GPIO_OE_ACCESS
SIO_GPIO_OE_BITS
SIO_GPIO_OE_CLR_ACCESS
SIO_GPIO_OE_CLR_BITS
SIO_GPIO_OE_CLR_LSB
SIO_GPIO_OE_CLR_MSB
SIO_GPIO_OE_CLR_OFFSET
SIO_GPIO_OE_CLR_RESET
SIO_GPIO_OE_LSB
SIO_GPIO_OE_MSB
SIO_GPIO_OE_OFFSET
SIO_GPIO_OE_RESET
SIO_GPIO_OE_SET_ACCESS
SIO_GPIO_OE_SET_BITS
SIO_GPIO_OE_SET_LSB
SIO_GPIO_OE_SET_MSB
SIO_GPIO_OE_SET_OFFSET
SIO_GPIO_OE_SET_RESET
SIO_GPIO_OE_XOR_ACCESS
SIO_GPIO_OE_XOR_BITS
SIO_GPIO_OE_XOR_LSB
SIO_GPIO_OE_XOR_MSB
SIO_GPIO_OE_XOR_OFFSET
SIO_GPIO_OE_XOR_RESET
SIO_GPIO_OUT_ACCESS
SIO_GPIO_OUT_BITS
SIO_GPIO_OUT_CLR_ACCESS
SIO_GPIO_OUT_CLR_BITS
SIO_GPIO_OUT_CLR_LSB
SIO_GPIO_OUT_CLR_MSB
SIO_GPIO_OUT_CLR_OFFSET
SIO_GPIO_OUT_CLR_RESET
SIO_GPIO_OUT_LSB
SIO_GPIO_OUT_MSB
SIO_GPIO_OUT_OFFSET
SIO_GPIO_OUT_RESET
SIO_GPIO_OUT_SET_ACCESS
SIO_GPIO_OUT_SET_BITS
SIO_GPIO_OUT_SET_LSB
SIO_GPIO_OUT_SET_MSB
SIO_GPIO_OUT_SET_OFFSET
SIO_GPIO_OUT_SET_RESET
SIO_GPIO_OUT_XOR_ACCESS
SIO_GPIO_OUT_XOR_BITS
SIO_GPIO_OUT_XOR_LSB
SIO_GPIO_OUT_XOR_MSB
SIO_GPIO_OUT_XOR_OFFSET
SIO_GPIO_OUT_XOR_RESET
SIO_INTERP0_ACCUM0_ACCESS
SIO_INTERP0_ACCUM0_ADD_ACCESS
SIO_INTERP0_ACCUM0_ADD_BITS
SIO_INTERP0_ACCUM0_ADD_LSB
SIO_INTERP0_ACCUM0_ADD_MSB
SIO_INTERP0_ACCUM0_ADD_OFFSET
SIO_INTERP0_ACCUM0_ADD_RESET
SIO_INTERP0_ACCUM0_BITS
SIO_INTERP0_ACCUM0_LSB
SIO_INTERP0_ACCUM0_MSB
SIO_INTERP0_ACCUM0_OFFSET
SIO_INTERP0_ACCUM0_RESET
SIO_INTERP0_ACCUM1_ACCESS
SIO_INTERP0_ACCUM1_ADD_ACCESS
SIO_INTERP0_ACCUM1_ADD_BITS
SIO_INTERP0_ACCUM1_ADD_LSB
SIO_INTERP0_ACCUM1_ADD_MSB
SIO_INTERP0_ACCUM1_ADD_OFFSET
SIO_INTERP0_ACCUM1_ADD_RESET
SIO_INTERP0_ACCUM1_BITS
SIO_INTERP0_ACCUM1_LSB
SIO_INTERP0_ACCUM1_MSB
SIO_INTERP0_ACCUM1_OFFSET
SIO_INTERP0_ACCUM1_RESET
SIO_INTERP0_BASE0_ACCESS
SIO_INTERP0_BASE0_BITS
SIO_INTERP0_BASE0_LSB
SIO_INTERP0_BASE0_MSB
SIO_INTERP0_BASE0_OFFSET
SIO_INTERP0_BASE0_RESET
SIO_INTERP0_BASE1_ACCESS
SIO_INTERP0_BASE1_BITS
SIO_INTERP0_BASE1_LSB
SIO_INTERP0_BASE1_MSB
SIO_INTERP0_BASE1_OFFSET
SIO_INTERP0_BASE1_RESET
SIO_INTERP0_BASE2_ACCESS
SIO_INTERP0_BASE2_BITS
SIO_INTERP0_BASE2_LSB
SIO_INTERP0_BASE2_MSB
SIO_INTERP0_BASE2_OFFSET
SIO_INTERP0_BASE2_RESET
SIO_INTERP0_BASE_1AND0_ACCESS
SIO_INTERP0_BASE_1AND0_BITS
SIO_INTERP0_BASE_1AND0_LSB
SIO_INTERP0_BASE_1AND0_MSB
SIO_INTERP0_BASE_1AND0_OFFSET
SIO_INTERP0_BASE_1AND0_RESET
SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS
SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS
SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB
SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB
SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET
SIO_INTERP0_CTRL_LANE0_BITS
SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS
SIO_INTERP0_CTRL_LANE0_BLEND_BITS
SIO_INTERP0_CTRL_LANE0_BLEND_LSB
SIO_INTERP0_CTRL_LANE0_BLEND_MSB
SIO_INTERP0_CTRL_LANE0_BLEND_RESET
SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS
SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS
SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB
SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB
SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET
SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS
SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS
SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB
SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB
SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET
SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS
SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS
SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB
SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB
SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET
SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS
SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS
SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB
SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB
SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET
SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS
SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS
SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB
SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB
SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET
SIO_INTERP0_CTRL_LANE0_OFFSET
SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS
SIO_INTERP0_CTRL_LANE0_OVERF0_BITS
SIO_INTERP0_CTRL_LANE0_OVERF0_LSB
SIO_INTERP0_CTRL_LANE0_OVERF0_MSB
SIO_INTERP0_CTRL_LANE0_OVERF0_RESET
SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS
SIO_INTERP0_CTRL_LANE0_OVERF1_BITS
SIO_INTERP0_CTRL_LANE0_OVERF1_LSB
SIO_INTERP0_CTRL_LANE0_OVERF1_MSB
SIO_INTERP0_CTRL_LANE0_OVERF1_RESET
SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS
SIO_INTERP0_CTRL_LANE0_OVERF_BITS
SIO_INTERP0_CTRL_LANE0_OVERF_LSB
SIO_INTERP0_CTRL_LANE0_OVERF_MSB
SIO_INTERP0_CTRL_LANE0_OVERF_RESET
SIO_INTERP0_CTRL_LANE0_RESET
SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS
SIO_INTERP0_CTRL_LANE0_SHIFT_BITS
SIO_INTERP0_CTRL_LANE0_SHIFT_LSB
SIO_INTERP0_CTRL_LANE0_SHIFT_MSB
SIO_INTERP0_CTRL_LANE0_SHIFT_RESET
SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS
SIO_INTERP0_CTRL_LANE0_SIGNED_BITS
SIO_INTERP0_CTRL_LANE0_SIGNED_LSB
SIO_INTERP0_CTRL_LANE0_SIGNED_MSB
SIO_INTERP0_CTRL_LANE0_SIGNED_RESET
SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS
SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS
SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB
SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB
SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET
SIO_INTERP0_CTRL_LANE1_BITS
SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS
SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS
SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB
SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB
SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET
SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS
SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS
SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB
SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB
SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET
SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS
SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS
SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB
SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB
SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET
SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS
SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS
SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB
SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB
SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET
SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS
SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS
SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB
SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB
SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET
SIO_INTERP0_CTRL_LANE1_OFFSET
SIO_INTERP0_CTRL_LANE1_RESET
SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS
SIO_INTERP0_CTRL_LANE1_SHIFT_BITS
SIO_INTERP0_CTRL_LANE1_SHIFT_LSB
SIO_INTERP0_CTRL_LANE1_SHIFT_MSB
SIO_INTERP0_CTRL_LANE1_SHIFT_RESET
SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS
SIO_INTERP0_CTRL_LANE1_SIGNED_BITS
SIO_INTERP0_CTRL_LANE1_SIGNED_LSB
SIO_INTERP0_CTRL_LANE1_SIGNED_MSB
SIO_INTERP0_CTRL_LANE1_SIGNED_RESET
SIO_INTERP0_PEEK_FULL_ACCESS
SIO_INTERP0_PEEK_FULL_BITS
SIO_INTERP0_PEEK_FULL_LSB
SIO_INTERP0_PEEK_FULL_MSB
SIO_INTERP0_PEEK_FULL_OFFSET
SIO_INTERP0_PEEK_FULL_RESET
SIO_INTERP0_PEEK_LANE0_ACCESS
SIO_INTERP0_PEEK_LANE0_BITS
SIO_INTERP0_PEEK_LANE0_LSB
SIO_INTERP0_PEEK_LANE0_MSB
SIO_INTERP0_PEEK_LANE0_OFFSET
SIO_INTERP0_PEEK_LANE0_RESET
SIO_INTERP0_PEEK_LANE1_ACCESS
SIO_INTERP0_PEEK_LANE1_BITS
SIO_INTERP0_PEEK_LANE1_LSB
SIO_INTERP0_PEEK_LANE1_MSB
SIO_INTERP0_PEEK_LANE1_OFFSET
SIO_INTERP0_PEEK_LANE1_RESET
SIO_INTERP0_POP_FULL_ACCESS
SIO_INTERP0_POP_FULL_BITS
SIO_INTERP0_POP_FULL_LSB
SIO_INTERP0_POP_FULL_MSB
SIO_INTERP0_POP_FULL_OFFSET
SIO_INTERP0_POP_FULL_RESET
SIO_INTERP0_POP_LANE0_ACCESS
SIO_INTERP0_POP_LANE0_BITS
SIO_INTERP0_POP_LANE0_LSB
SIO_INTERP0_POP_LANE0_MSB
SIO_INTERP0_POP_LANE0_OFFSET
SIO_INTERP0_POP_LANE0_RESET
SIO_INTERP0_POP_LANE1_ACCESS
SIO_INTERP0_POP_LANE1_BITS
SIO_INTERP0_POP_LANE1_LSB
SIO_INTERP0_POP_LANE1_MSB
SIO_INTERP0_POP_LANE1_OFFSET
SIO_INTERP0_POP_LANE1_RESET
SIO_INTERP1_ACCUM0_ACCESS
SIO_INTERP1_ACCUM0_ADD_ACCESS
SIO_INTERP1_ACCUM0_ADD_BITS
SIO_INTERP1_ACCUM0_ADD_LSB
SIO_INTERP1_ACCUM0_ADD_MSB
SIO_INTERP1_ACCUM0_ADD_OFFSET
SIO_INTERP1_ACCUM0_ADD_RESET
SIO_INTERP1_ACCUM0_BITS
SIO_INTERP1_ACCUM0_LSB
SIO_INTERP1_ACCUM0_MSB
SIO_INTERP1_ACCUM0_OFFSET
SIO_INTERP1_ACCUM0_RESET
SIO_INTERP1_ACCUM1_ACCESS
SIO_INTERP1_ACCUM1_ADD_ACCESS
SIO_INTERP1_ACCUM1_ADD_BITS
SIO_INTERP1_ACCUM1_ADD_LSB
SIO_INTERP1_ACCUM1_ADD_MSB
SIO_INTERP1_ACCUM1_ADD_OFFSET
SIO_INTERP1_ACCUM1_ADD_RESET
SIO_INTERP1_ACCUM1_BITS
SIO_INTERP1_ACCUM1_LSB
SIO_INTERP1_ACCUM1_MSB
SIO_INTERP1_ACCUM1_OFFSET
SIO_INTERP1_ACCUM1_RESET
SIO_INTERP1_BASE0_ACCESS
SIO_INTERP1_BASE0_BITS
SIO_INTERP1_BASE0_LSB
SIO_INTERP1_BASE0_MSB
SIO_INTERP1_BASE0_OFFSET
SIO_INTERP1_BASE0_RESET
SIO_INTERP1_BASE1_ACCESS
SIO_INTERP1_BASE1_BITS
SIO_INTERP1_BASE1_LSB
SIO_INTERP1_BASE1_MSB
SIO_INTERP1_BASE1_OFFSET
SIO_INTERP1_BASE1_RESET
SIO_INTERP1_BASE2_ACCESS
SIO_INTERP1_BASE2_BITS
SIO_INTERP1_BASE2_LSB
SIO_INTERP1_BASE2_MSB
SIO_INTERP1_BASE2_OFFSET
SIO_INTERP1_BASE2_RESET
SIO_INTERP1_BASE_1AND0_ACCESS
SIO_INTERP1_BASE_1AND0_BITS
SIO_INTERP1_BASE_1AND0_LSB
SIO_INTERP1_BASE_1AND0_MSB
SIO_INTERP1_BASE_1AND0_OFFSET
SIO_INTERP1_BASE_1AND0_RESET
SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS
SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS
SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB
SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB
SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET
SIO_INTERP1_CTRL_LANE0_BITS
SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS
SIO_INTERP1_CTRL_LANE0_CLAMP_BITS
SIO_INTERP1_CTRL_LANE0_CLAMP_LSB
SIO_INTERP1_CTRL_LANE0_CLAMP_MSB
SIO_INTERP1_CTRL_LANE0_CLAMP_RESET
SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS
SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS
SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB
SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB
SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET
SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS
SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS
SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB
SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB
SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET
SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS
SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS
SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB
SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB
SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET
SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS
SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS
SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB
SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB
SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET
SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS
SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS
SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB
SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB
SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET
SIO_INTERP1_CTRL_LANE0_OFFSET
SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS
SIO_INTERP1_CTRL_LANE0_OVERF0_BITS
SIO_INTERP1_CTRL_LANE0_OVERF0_LSB
SIO_INTERP1_CTRL_LANE0_OVERF0_MSB
SIO_INTERP1_CTRL_LANE0_OVERF0_RESET
SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS
SIO_INTERP1_CTRL_LANE0_OVERF1_BITS
SIO_INTERP1_CTRL_LANE0_OVERF1_LSB
SIO_INTERP1_CTRL_LANE0_OVERF1_MSB
SIO_INTERP1_CTRL_LANE0_OVERF1_RESET
SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS
SIO_INTERP1_CTRL_LANE0_OVERF_BITS
SIO_INTERP1_CTRL_LANE0_OVERF_LSB
SIO_INTERP1_CTRL_LANE0_OVERF_MSB
SIO_INTERP1_CTRL_LANE0_OVERF_RESET
SIO_INTERP1_CTRL_LANE0_RESET
SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS
SIO_INTERP1_CTRL_LANE0_SHIFT_BITS
SIO_INTERP1_CTRL_LANE0_SHIFT_LSB
SIO_INTERP1_CTRL_LANE0_SHIFT_MSB
SIO_INTERP1_CTRL_LANE0_SHIFT_RESET
SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS
SIO_INTERP1_CTRL_LANE0_SIGNED_BITS
SIO_INTERP1_CTRL_LANE0_SIGNED_LSB
SIO_INTERP1_CTRL_LANE0_SIGNED_MSB
SIO_INTERP1_CTRL_LANE0_SIGNED_RESET
SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS
SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS
SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB
SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB
SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET
SIO_INTERP1_CTRL_LANE1_BITS
SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS
SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS
SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB
SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB
SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET
SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS
SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS
SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB
SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB
SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET
SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS
SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS
SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB
SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB
SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET
SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS
SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS
SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB
SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB
SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET
SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS
SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS
SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB
SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB
SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET
SIO_INTERP1_CTRL_LANE1_OFFSET
SIO_INTERP1_CTRL_LANE1_RESET
SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS
SIO_INTERP1_CTRL_LANE1_SHIFT_BITS
SIO_INTERP1_CTRL_LANE1_SHIFT_LSB
SIO_INTERP1_CTRL_LANE1_SHIFT_MSB
SIO_INTERP1_CTRL_LANE1_SHIFT_RESET
SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS
SIO_INTERP1_CTRL_LANE1_SIGNED_BITS
SIO_INTERP1_CTRL_LANE1_SIGNED_LSB
SIO_INTERP1_CTRL_LANE1_SIGNED_MSB
SIO_INTERP1_CTRL_LANE1_SIGNED_RESET
SIO_INTERP1_PEEK_FULL_ACCESS
SIO_INTERP1_PEEK_FULL_BITS
SIO_INTERP1_PEEK_FULL_LSB
SIO_INTERP1_PEEK_FULL_MSB
SIO_INTERP1_PEEK_FULL_OFFSET
SIO_INTERP1_PEEK_FULL_RESET
SIO_INTERP1_PEEK_LANE0_ACCESS
SIO_INTERP1_PEEK_LANE0_BITS
SIO_INTERP1_PEEK_LANE0_LSB
SIO_INTERP1_PEEK_LANE0_MSB
SIO_INTERP1_PEEK_LANE0_OFFSET
SIO_INTERP1_PEEK_LANE0_RESET
SIO_INTERP1_PEEK_LANE1_ACCESS
SIO_INTERP1_PEEK_LANE1_BITS
SIO_INTERP1_PEEK_LANE1_LSB
SIO_INTERP1_PEEK_LANE1_MSB
SIO_INTERP1_PEEK_LANE1_OFFSET
SIO_INTERP1_PEEK_LANE1_RESET
SIO_INTERP1_POP_FULL_ACCESS
SIO_INTERP1_POP_FULL_BITS
SIO_INTERP1_POP_FULL_LSB
SIO_INTERP1_POP_FULL_MSB
SIO_INTERP1_POP_FULL_OFFSET
SIO_INTERP1_POP_FULL_RESET
SIO_INTERP1_POP_LANE0_ACCESS
SIO_INTERP1_POP_LANE0_BITS
SIO_INTERP1_POP_LANE0_LSB
SIO_INTERP1_POP_LANE0_MSB
SIO_INTERP1_POP_LANE0_OFFSET
SIO_INTERP1_POP_LANE0_RESET
SIO_INTERP1_POP_LANE1_ACCESS
SIO_INTERP1_POP_LANE1_BITS
SIO_INTERP1_POP_LANE1_LSB
SIO_INTERP1_POP_LANE1_MSB
SIO_INTERP1_POP_LANE1_OFFSET
SIO_INTERP1_POP_LANE1_RESET
SIO_SPINLOCK0_ACCESS
SIO_SPINLOCK0_BITS
SIO_SPINLOCK0_LSB
SIO_SPINLOCK0_MSB
SIO_SPINLOCK0_OFFSET
SIO_SPINLOCK0_RESET
SIO_SPINLOCK1_ACCESS
SIO_SPINLOCK1_BITS
SIO_SPINLOCK1_LSB
SIO_SPINLOCK1_MSB
SIO_SPINLOCK1_OFFSET
SIO_SPINLOCK1_RESET
SIO_SPINLOCK2_ACCESS
SIO_SPINLOCK2_BITS
SIO_SPINLOCK2_LSB
SIO_SPINLOCK2_MSB
SIO_SPINLOCK2_OFFSET
SIO_SPINLOCK2_RESET
SIO_SPINLOCK3_ACCESS
SIO_SPINLOCK3_BITS
SIO_SPINLOCK3_LSB
SIO_SPINLOCK3_MSB
SIO_SPINLOCK3_OFFSET
SIO_SPINLOCK3_RESET
SIO_SPINLOCK4_ACCESS
SIO_SPINLOCK4_BITS
SIO_SPINLOCK4_LSB
SIO_SPINLOCK4_MSB
SIO_SPINLOCK4_OFFSET
SIO_SPINLOCK4_RESET
SIO_SPINLOCK5_ACCESS
SIO_SPINLOCK5_BITS
SIO_SPINLOCK5_LSB
SIO_SPINLOCK5_MSB
SIO_SPINLOCK5_OFFSET
SIO_SPINLOCK5_RESET
SIO_SPINLOCK6_ACCESS
SIO_SPINLOCK6_BITS
SIO_SPINLOCK6_LSB
SIO_SPINLOCK6_MSB
SIO_SPINLOCK6_OFFSET
SIO_SPINLOCK6_RESET
SIO_SPINLOCK7_ACCESS
SIO_SPINLOCK7_BITS
SIO_SPINLOCK7_LSB
SIO_SPINLOCK7_MSB
SIO_SPINLOCK7_OFFSET
SIO_SPINLOCK7_RESET
SIO_SPINLOCK8_ACCESS
SIO_SPINLOCK8_BITS
SIO_SPINLOCK8_LSB
SIO_SPINLOCK8_MSB
SIO_SPINLOCK8_OFFSET
SIO_SPINLOCK8_RESET
SIO_SPINLOCK9_ACCESS
SIO_SPINLOCK9_BITS
SIO_SPINLOCK9_LSB
SIO_SPINLOCK9_MSB
SIO_SPINLOCK9_OFFSET
SIO_SPINLOCK9_RESET
SIO_SPINLOCK10_ACCESS
SIO_SPINLOCK10_BITS
SIO_SPINLOCK10_LSB
SIO_SPINLOCK10_MSB
SIO_SPINLOCK10_OFFSET
SIO_SPINLOCK10_RESET
SIO_SPINLOCK11_ACCESS
SIO_SPINLOCK11_BITS
SIO_SPINLOCK11_LSB
SIO_SPINLOCK11_MSB
SIO_SPINLOCK11_OFFSET
SIO_SPINLOCK11_RESET
SIO_SPINLOCK12_ACCESS
SIO_SPINLOCK12_BITS
SIO_SPINLOCK12_LSB
SIO_SPINLOCK12_MSB
SIO_SPINLOCK12_OFFSET
SIO_SPINLOCK12_RESET
SIO_SPINLOCK13_ACCESS
SIO_SPINLOCK13_BITS
SIO_SPINLOCK13_LSB
SIO_SPINLOCK13_MSB
SIO_SPINLOCK13_OFFSET
SIO_SPINLOCK13_RESET
SIO_SPINLOCK14_ACCESS
SIO_SPINLOCK14_BITS
SIO_SPINLOCK14_LSB
SIO_SPINLOCK14_MSB
SIO_SPINLOCK14_OFFSET
SIO_SPINLOCK14_RESET
SIO_SPINLOCK15_ACCESS
SIO_SPINLOCK15_BITS
SIO_SPINLOCK15_LSB
SIO_SPINLOCK15_MSB
SIO_SPINLOCK15_OFFSET
SIO_SPINLOCK15_RESET
SIO_SPINLOCK16_ACCESS
SIO_SPINLOCK16_BITS
SIO_SPINLOCK16_LSB
SIO_SPINLOCK16_MSB
SIO_SPINLOCK16_OFFSET
SIO_SPINLOCK16_RESET
SIO_SPINLOCK17_ACCESS
SIO_SPINLOCK17_BITS
SIO_SPINLOCK17_LSB
SIO_SPINLOCK17_MSB
SIO_SPINLOCK17_OFFSET
SIO_SPINLOCK17_RESET
SIO_SPINLOCK18_ACCESS
SIO_SPINLOCK18_BITS
SIO_SPINLOCK18_LSB
SIO_SPINLOCK18_MSB
SIO_SPINLOCK18_OFFSET
SIO_SPINLOCK18_RESET
SIO_SPINLOCK19_ACCESS
SIO_SPINLOCK19_BITS
SIO_SPINLOCK19_LSB
SIO_SPINLOCK19_MSB
SIO_SPINLOCK19_OFFSET
SIO_SPINLOCK19_RESET
SIO_SPINLOCK20_ACCESS
SIO_SPINLOCK20_BITS
SIO_SPINLOCK20_LSB
SIO_SPINLOCK20_MSB
SIO_SPINLOCK20_OFFSET
SIO_SPINLOCK20_RESET
SIO_SPINLOCK21_ACCESS
SIO_SPINLOCK21_BITS
SIO_SPINLOCK21_LSB
SIO_SPINLOCK21_MSB
SIO_SPINLOCK21_OFFSET
SIO_SPINLOCK21_RESET
SIO_SPINLOCK22_ACCESS
SIO_SPINLOCK22_BITS
SIO_SPINLOCK22_LSB
SIO_SPINLOCK22_MSB
SIO_SPINLOCK22_OFFSET
SIO_SPINLOCK22_RESET
SIO_SPINLOCK23_ACCESS
SIO_SPINLOCK23_BITS
SIO_SPINLOCK23_LSB
SIO_SPINLOCK23_MSB
SIO_SPINLOCK23_OFFSET
SIO_SPINLOCK23_RESET
SIO_SPINLOCK24_ACCESS
SIO_SPINLOCK24_BITS
SIO_SPINLOCK24_LSB
SIO_SPINLOCK24_MSB
SIO_SPINLOCK24_OFFSET
SIO_SPINLOCK24_RESET
SIO_SPINLOCK25_ACCESS
SIO_SPINLOCK25_BITS
SIO_SPINLOCK25_LSB
SIO_SPINLOCK25_MSB
SIO_SPINLOCK25_OFFSET
SIO_SPINLOCK25_RESET
SIO_SPINLOCK26_ACCESS
SIO_SPINLOCK26_BITS
SIO_SPINLOCK26_LSB
SIO_SPINLOCK26_MSB
SIO_SPINLOCK26_OFFSET
SIO_SPINLOCK26_RESET
SIO_SPINLOCK27_ACCESS
SIO_SPINLOCK27_BITS
SIO_SPINLOCK27_LSB
SIO_SPINLOCK27_MSB
SIO_SPINLOCK27_OFFSET
SIO_SPINLOCK27_RESET
SIO_SPINLOCK28_ACCESS
SIO_SPINLOCK28_BITS
SIO_SPINLOCK28_LSB
SIO_SPINLOCK28_MSB
SIO_SPINLOCK28_OFFSET
SIO_SPINLOCK28_RESET
SIO_SPINLOCK29_ACCESS
SIO_SPINLOCK29_BITS
SIO_SPINLOCK29_LSB
SIO_SPINLOCK29_MSB
SIO_SPINLOCK29_OFFSET
SIO_SPINLOCK29_RESET
SIO_SPINLOCK30_ACCESS
SIO_SPINLOCK30_BITS
SIO_SPINLOCK30_LSB
SIO_SPINLOCK30_MSB
SIO_SPINLOCK30_OFFSET
SIO_SPINLOCK30_RESET
SIO_SPINLOCK31_ACCESS
SIO_SPINLOCK31_BITS
SIO_SPINLOCK31_LSB
SIO_SPINLOCK31_MSB
SIO_SPINLOCK31_OFFSET
SIO_SPINLOCK31_RESET
SIO_SPINLOCK_ST_ACCESS
SIO_SPINLOCK_ST_BITS
SIO_SPINLOCK_ST_LSB
SIO_SPINLOCK_ST_MSB
SIO_SPINLOCK_ST_OFFSET
SIO_SPINLOCK_ST_RESET
SIZE_MAX
SPI0_BASE
SPI1_BASE
SRAM0_BASE
SRAM1_BASE
SRAM2_BASE
SRAM3_BASE
SRAM4_BASE
SRAM5_BASE
SRAM_BASE
SRAM_END
SRAM_STRIPED_BASE
SRAM_STRIPED_END
SYSCFG_BASE
SYSINFO_BASE
TBMAN_BASE
TIMER_ALARM0_ACCESS
TIMER_ALARM0_BITS
TIMER_ALARM0_LSB
TIMER_ALARM0_MSB
TIMER_ALARM0_OFFSET
TIMER_ALARM0_RESET
TIMER_ALARM1_ACCESS
TIMER_ALARM1_BITS
TIMER_ALARM1_LSB
TIMER_ALARM1_MSB
TIMER_ALARM1_OFFSET
TIMER_ALARM1_RESET
TIMER_ALARM2_ACCESS
TIMER_ALARM2_BITS
TIMER_ALARM2_LSB
TIMER_ALARM2_MSB
TIMER_ALARM2_OFFSET
TIMER_ALARM2_RESET
TIMER_ALARM3_ACCESS
TIMER_ALARM3_BITS
TIMER_ALARM3_LSB
TIMER_ALARM3_MSB
TIMER_ALARM3_OFFSET
TIMER_ALARM3_RESET
TIMER_ARMED_ACCESS
TIMER_ARMED_BITS
TIMER_ARMED_LSB
TIMER_ARMED_MSB
TIMER_ARMED_OFFSET
TIMER_ARMED_RESET
TIMER_BASE
TIMER_DBGPAUSE_BITS
TIMER_DBGPAUSE_DBG0_ACCESS
TIMER_DBGPAUSE_DBG0_BITS
TIMER_DBGPAUSE_DBG0_LSB
TIMER_DBGPAUSE_DBG0_MSB
TIMER_DBGPAUSE_DBG0_RESET
TIMER_DBGPAUSE_DBG1_ACCESS
TIMER_DBGPAUSE_DBG1_BITS
TIMER_DBGPAUSE_DBG1_LSB
TIMER_DBGPAUSE_DBG1_MSB
TIMER_DBGPAUSE_DBG1_RESET
TIMER_DBGPAUSE_OFFSET
TIMER_DBGPAUSE_RESET
TIMER_INTE_ALARM_0_ACCESS
TIMER_INTE_ALARM_0_BITS
TIMER_INTE_ALARM_0_LSB
TIMER_INTE_ALARM_0_MSB
TIMER_INTE_ALARM_0_RESET
TIMER_INTE_ALARM_1_ACCESS
TIMER_INTE_ALARM_1_BITS
TIMER_INTE_ALARM_1_LSB
TIMER_INTE_ALARM_1_MSB
TIMER_INTE_ALARM_1_RESET
TIMER_INTE_ALARM_2_ACCESS
TIMER_INTE_ALARM_2_BITS
TIMER_INTE_ALARM_2_LSB
TIMER_INTE_ALARM_2_MSB
TIMER_INTE_ALARM_2_RESET
TIMER_INTE_ALARM_3_ACCESS
TIMER_INTE_ALARM_3_BITS
TIMER_INTE_ALARM_3_LSB
TIMER_INTE_ALARM_3_MSB
TIMER_INTE_ALARM_3_RESET
TIMER_INTE_BITS
TIMER_INTE_OFFSET
TIMER_INTE_RESET
TIMER_INTF_ALARM_0_ACCESS
TIMER_INTF_ALARM_0_BITS
TIMER_INTF_ALARM_0_LSB
TIMER_INTF_ALARM_0_MSB
TIMER_INTF_ALARM_0_RESET
TIMER_INTF_ALARM_1_ACCESS
TIMER_INTF_ALARM_1_BITS
TIMER_INTF_ALARM_1_LSB
TIMER_INTF_ALARM_1_MSB
TIMER_INTF_ALARM_1_RESET
TIMER_INTF_ALARM_2_ACCESS
TIMER_INTF_ALARM_2_BITS
TIMER_INTF_ALARM_2_LSB
TIMER_INTF_ALARM_2_MSB
TIMER_INTF_ALARM_2_RESET
TIMER_INTF_ALARM_3_ACCESS
TIMER_INTF_ALARM_3_BITS
TIMER_INTF_ALARM_3_LSB
TIMER_INTF_ALARM_3_MSB
TIMER_INTF_ALARM_3_RESET
TIMER_INTF_BITS
TIMER_INTF_OFFSET
TIMER_INTF_RESET
TIMER_INTR_ALARM_0_ACCESS
TIMER_INTR_ALARM_0_BITS
TIMER_INTR_ALARM_0_LSB
TIMER_INTR_ALARM_0_MSB
TIMER_INTR_ALARM_0_RESET
TIMER_INTR_ALARM_1_ACCESS
TIMER_INTR_ALARM_1_BITS
TIMER_INTR_ALARM_1_LSB
TIMER_INTR_ALARM_1_MSB
TIMER_INTR_ALARM_1_RESET
TIMER_INTR_ALARM_2_ACCESS
TIMER_INTR_ALARM_2_BITS
TIMER_INTR_ALARM_2_LSB
TIMER_INTR_ALARM_2_MSB
TIMER_INTR_ALARM_2_RESET
TIMER_INTR_ALARM_3_ACCESS
TIMER_INTR_ALARM_3_BITS
TIMER_INTR_ALARM_3_LSB
TIMER_INTR_ALARM_3_MSB
TIMER_INTR_ALARM_3_RESET
TIMER_INTR_BITS
TIMER_INTR_OFFSET
TIMER_INTR_RESET
TIMER_INTS_ALARM_0_ACCESS
TIMER_INTS_ALARM_0_BITS
TIMER_INTS_ALARM_0_LSB
TIMER_INTS_ALARM_0_MSB
TIMER_INTS_ALARM_0_RESET
TIMER_INTS_ALARM_1_ACCESS
TIMER_INTS_ALARM_1_BITS
TIMER_INTS_ALARM_1_LSB
TIMER_INTS_ALARM_1_MSB
TIMER_INTS_ALARM_1_RESET
TIMER_INTS_ALARM_2_ACCESS
TIMER_INTS_ALARM_2_BITS
TIMER_INTS_ALARM_2_LSB
TIMER_INTS_ALARM_2_MSB
TIMER_INTS_ALARM_2_RESET
TIMER_INTS_ALARM_3_ACCESS
TIMER_INTS_ALARM_3_BITS
TIMER_INTS_ALARM_3_LSB
TIMER_INTS_ALARM_3_MSB
TIMER_INTS_ALARM_3_RESET
TIMER_INTS_BITS
TIMER_INTS_OFFSET
TIMER_INTS_RESET
TIMER_PAUSE_ACCESS
TIMER_PAUSE_BITS
TIMER_PAUSE_LSB
TIMER_PAUSE_MSB
TIMER_PAUSE_OFFSET
TIMER_PAUSE_RESET
TIMER_TIMEHR_ACCESS
TIMER_TIMEHR_BITS
TIMER_TIMEHR_LSB
TIMER_TIMEHR_MSB
TIMER_TIMEHR_OFFSET
TIMER_TIMEHR_RESET
TIMER_TIMEHW_ACCESS
TIMER_TIMEHW_BITS
TIMER_TIMEHW_LSB
TIMER_TIMEHW_MSB
TIMER_TIMEHW_OFFSET
TIMER_TIMEHW_RESET
TIMER_TIMELR_ACCESS
TIMER_TIMELR_BITS
TIMER_TIMELR_LSB
TIMER_TIMELR_MSB
TIMER_TIMELR_OFFSET
TIMER_TIMELR_RESET
TIMER_TIMELW_ACCESS
TIMER_TIMELW_BITS
TIMER_TIMELW_LSB
TIMER_TIMELW_MSB
TIMER_TIMELW_OFFSET
TIMER_TIMELW_RESET
TIMER_TIMERAWH_ACCESS
TIMER_TIMERAWH_BITS
TIMER_TIMERAWH_LSB
TIMER_TIMERAWH_MSB
TIMER_TIMERAWH_OFFSET
TIMER_TIMERAWH_RESET
TIMER_TIMERAWL_ACCESS
TIMER_TIMERAWL_BITS
TIMER_TIMERAWL_LSB
TIMER_TIMERAWL_MSB
TIMER_TIMERAWL_OFFSET
TIMER_TIMERAWL_RESET
UART0_BASE
UART1_BASE
UART_UARTCR_BITS
UART_UARTCR_CTSEN_ACCESS
UART_UARTCR_CTSEN_BITS
UART_UARTCR_CTSEN_LSB
UART_UARTCR_CTSEN_MSB
UART_UARTCR_CTSEN_RESET
UART_UARTCR_DTR_ACCESS
UART_UARTCR_DTR_BITS
UART_UARTCR_DTR_LSB
UART_UARTCR_DTR_MSB
UART_UARTCR_DTR_RESET
UART_UARTCR_LBE_ACCESS
UART_UARTCR_LBE_BITS
UART_UARTCR_LBE_LSB
UART_UARTCR_LBE_MSB
UART_UARTCR_LBE_RESET
UART_UARTCR_OFFSET
UART_UARTCR_OUT1_ACCESS
UART_UARTCR_OUT1_BITS
UART_UARTCR_OUT1_LSB
UART_UARTCR_OUT1_MSB
UART_UARTCR_OUT1_RESET
UART_UARTCR_OUT2_ACCESS
UART_UARTCR_OUT2_BITS
UART_UARTCR_OUT2_LSB
UART_UARTCR_OUT2_MSB
UART_UARTCR_OUT2_RESET
UART_UARTCR_RESET
UART_UARTCR_RTSEN_ACCESS
UART_UARTCR_RTSEN_BITS
UART_UARTCR_RTSEN_LSB
UART_UARTCR_RTSEN_MSB
UART_UARTCR_RTSEN_RESET
UART_UARTCR_RTS_ACCESS
UART_UARTCR_RTS_BITS
UART_UARTCR_RTS_LSB
UART_UARTCR_RTS_MSB
UART_UARTCR_RTS_RESET
UART_UARTCR_RXE_ACCESS
UART_UARTCR_RXE_BITS
UART_UARTCR_RXE_LSB
UART_UARTCR_RXE_MSB
UART_UARTCR_RXE_RESET
UART_UARTCR_SIREN_ACCESS
UART_UARTCR_SIREN_BITS
UART_UARTCR_SIREN_LSB
UART_UARTCR_SIREN_MSB
UART_UARTCR_SIREN_RESET
UART_UARTCR_SIRLP_ACCESS
UART_UARTCR_SIRLP_BITS
UART_UARTCR_SIRLP_LSB
UART_UARTCR_SIRLP_MSB
UART_UARTCR_SIRLP_RESET
UART_UARTCR_TXE_ACCESS
UART_UARTCR_TXE_BITS
UART_UARTCR_TXE_LSB
UART_UARTCR_TXE_MSB
UART_UARTCR_TXE_RESET
UART_UARTCR_UARTEN_ACCESS
UART_UARTCR_UARTEN_BITS
UART_UARTCR_UARTEN_LSB
UART_UARTCR_UARTEN_MSB
UART_UARTCR_UARTEN_RESET
UART_UARTDMACR_BITS
UART_UARTDMACR_DMAONERR_ACCESS
UART_UARTDMACR_DMAONERR_BITS
UART_UARTDMACR_DMAONERR_LSB
UART_UARTDMACR_DMAONERR_MSB
UART_UARTDMACR_DMAONERR_RESET
UART_UARTDMACR_OFFSET
UART_UARTDMACR_RESET
UART_UARTDMACR_RXDMAE_ACCESS
UART_UARTDMACR_RXDMAE_BITS
UART_UARTDMACR_RXDMAE_LSB
UART_UARTDMACR_RXDMAE_MSB
UART_UARTDMACR_RXDMAE_RESET
UART_UARTDMACR_TXDMAE_ACCESS
UART_UARTDMACR_TXDMAE_BITS
UART_UARTDMACR_TXDMAE_LSB
UART_UARTDMACR_TXDMAE_MSB
UART_UARTDMACR_TXDMAE_RESET
UART_UARTDR_BE_ACCESS
UART_UARTDR_BE_BITS
UART_UARTDR_BE_LSB
UART_UARTDR_BE_MSB
UART_UARTDR_BE_RESET
UART_UARTDR_BITS
UART_UARTDR_DATA_ACCESS
UART_UARTDR_DATA_BITS
UART_UARTDR_DATA_LSB
UART_UARTDR_DATA_MSB
UART_UARTDR_DATA_RESET
UART_UARTDR_FE_ACCESS
UART_UARTDR_FE_BITS
UART_UARTDR_FE_LSB
UART_UARTDR_FE_MSB
UART_UARTDR_FE_RESET
UART_UARTDR_OE_ACCESS
UART_UARTDR_OE_BITS
UART_UARTDR_OE_LSB
UART_UARTDR_OE_MSB
UART_UARTDR_OE_RESET
UART_UARTDR_OFFSET
UART_UARTDR_PE_ACCESS
UART_UARTDR_PE_BITS
UART_UARTDR_PE_LSB
UART_UARTDR_PE_MSB
UART_UARTDR_PE_RESET
UART_UARTDR_RESET
UART_UARTFBRD_BAUD_DIVFRAC_ACCESS
UART_UARTFBRD_BAUD_DIVFRAC_BITS
UART_UARTFBRD_BAUD_DIVFRAC_LSB
UART_UARTFBRD_BAUD_DIVFRAC_MSB
UART_UARTFBRD_BAUD_DIVFRAC_RESET
UART_UARTFBRD_BITS
UART_UARTFBRD_OFFSET
UART_UARTFBRD_RESET
UART_UARTFR_BITS
UART_UARTFR_BUSY_ACCESS
UART_UARTFR_BUSY_BITS
UART_UARTFR_BUSY_LSB
UART_UARTFR_BUSY_MSB
UART_UARTFR_BUSY_RESET
UART_UARTFR_CTS_ACCESS
UART_UARTFR_CTS_BITS
UART_UARTFR_CTS_LSB
UART_UARTFR_CTS_MSB
UART_UARTFR_CTS_RESET
UART_UARTFR_DCD_ACCESS
UART_UARTFR_DCD_BITS
UART_UARTFR_DCD_LSB
UART_UARTFR_DCD_MSB
UART_UARTFR_DCD_RESET
UART_UARTFR_DSR_ACCESS
UART_UARTFR_DSR_BITS
UART_UARTFR_DSR_LSB
UART_UARTFR_DSR_MSB
UART_UARTFR_DSR_RESET
UART_UARTFR_OFFSET
UART_UARTFR_RESET
UART_UARTFR_RI_ACCESS
UART_UARTFR_RI_BITS
UART_UARTFR_RI_LSB
UART_UARTFR_RI_MSB
UART_UARTFR_RI_RESET
UART_UARTFR_RXFE_ACCESS
UART_UARTFR_RXFE_BITS
UART_UARTFR_RXFE_LSB
UART_UARTFR_RXFE_MSB
UART_UARTFR_RXFE_RESET
UART_UARTFR_RXFF_ACCESS
UART_UARTFR_RXFF_BITS
UART_UARTFR_RXFF_LSB
UART_UARTFR_RXFF_MSB
UART_UARTFR_RXFF_RESET
UART_UARTFR_TXFE_ACCESS
UART_UARTFR_TXFE_BITS
UART_UARTFR_TXFE_LSB
UART_UARTFR_TXFE_MSB
UART_UARTFR_TXFE_RESET
UART_UARTFR_TXFF_ACCESS
UART_UARTFR_TXFF_BITS
UART_UARTFR_TXFF_LSB
UART_UARTFR_TXFF_MSB
UART_UARTFR_TXFF_RESET
UART_UARTIBRD_BAUD_DIVINT_ACCESS
UART_UARTIBRD_BAUD_DIVINT_BITS
UART_UARTIBRD_BAUD_DIVINT_LSB
UART_UARTIBRD_BAUD_DIVINT_MSB
UART_UARTIBRD_BAUD_DIVINT_RESET
UART_UARTIBRD_BITS
UART_UARTIBRD_OFFSET
UART_UARTIBRD_RESET
UART_UARTICR_BEIC_ACCESS
UART_UARTICR_BEIC_BITS
UART_UARTICR_BEIC_LSB
UART_UARTICR_BEIC_MSB
UART_UARTICR_BEIC_RESET
UART_UARTICR_BITS
UART_UARTICR_CTSMIC_ACCESS
UART_UARTICR_CTSMIC_BITS
UART_UARTICR_CTSMIC_LSB
UART_UARTICR_CTSMIC_MSB
UART_UARTICR_CTSMIC_RESET
UART_UARTICR_DCDMIC_ACCESS
UART_UARTICR_DCDMIC_BITS
UART_UARTICR_DCDMIC_LSB
UART_UARTICR_DCDMIC_MSB
UART_UARTICR_DCDMIC_RESET
UART_UARTICR_DSRMIC_ACCESS
UART_UARTICR_DSRMIC_BITS
UART_UARTICR_DSRMIC_LSB
UART_UARTICR_DSRMIC_MSB
UART_UARTICR_DSRMIC_RESET
UART_UARTICR_FEIC_ACCESS
UART_UARTICR_FEIC_BITS
UART_UARTICR_FEIC_LSB
UART_UARTICR_FEIC_MSB
UART_UARTICR_FEIC_RESET
UART_UARTICR_OEIC_ACCESS
UART_UARTICR_OEIC_BITS
UART_UARTICR_OEIC_LSB
UART_UARTICR_OEIC_MSB
UART_UARTICR_OEIC_RESET
UART_UARTICR_OFFSET
UART_UARTICR_PEIC_ACCESS
UART_UARTICR_PEIC_BITS
UART_UARTICR_PEIC_LSB
UART_UARTICR_PEIC_MSB
UART_UARTICR_PEIC_RESET
UART_UARTICR_RESET
UART_UARTICR_RIMIC_ACCESS
UART_UARTICR_RIMIC_BITS
UART_UARTICR_RIMIC_LSB
UART_UARTICR_RIMIC_MSB
UART_UARTICR_RIMIC_RESET
UART_UARTICR_RTIC_ACCESS
UART_UARTICR_RTIC_BITS
UART_UARTICR_RTIC_LSB
UART_UARTICR_RTIC_MSB
UART_UARTICR_RTIC_RESET
UART_UARTICR_RXIC_ACCESS
UART_UARTICR_RXIC_BITS
UART_UARTICR_RXIC_LSB
UART_UARTICR_RXIC_MSB
UART_UARTICR_RXIC_RESET
UART_UARTICR_TXIC_ACCESS
UART_UARTICR_TXIC_BITS
UART_UARTICR_TXIC_LSB
UART_UARTICR_TXIC_MSB
UART_UARTICR_TXIC_RESET
UART_UARTIFLS_BITS
UART_UARTIFLS_OFFSET
UART_UARTIFLS_RESET
UART_UARTIFLS_RXIFLSEL_ACCESS
UART_UARTIFLS_RXIFLSEL_BITS
UART_UARTIFLS_RXIFLSEL_LSB
UART_UARTIFLS_RXIFLSEL_MSB
UART_UARTIFLS_RXIFLSEL_RESET
UART_UARTIFLS_TXIFLSEL_ACCESS
UART_UARTIFLS_TXIFLSEL_BITS
UART_UARTIFLS_TXIFLSEL_LSB
UART_UARTIFLS_TXIFLSEL_MSB
UART_UARTIFLS_TXIFLSEL_RESET
UART_UARTILPR_BITS
UART_UARTILPR_ILPDVSR_ACCESS
UART_UARTILPR_ILPDVSR_BITS
UART_UARTILPR_ILPDVSR_LSB
UART_UARTILPR_ILPDVSR_MSB
UART_UARTILPR_ILPDVSR_RESET
UART_UARTILPR_OFFSET
UART_UARTILPR_RESET
UART_UARTIMSC_BEIM_ACCESS
UART_UARTIMSC_BEIM_BITS
UART_UARTIMSC_BEIM_LSB
UART_UARTIMSC_BEIM_MSB
UART_UARTIMSC_BEIM_RESET
UART_UARTIMSC_BITS
UART_UARTIMSC_CTSMIM_ACCESS
UART_UARTIMSC_CTSMIM_BITS
UART_UARTIMSC_CTSMIM_LSB
UART_UARTIMSC_CTSMIM_MSB
UART_UARTIMSC_CTSMIM_RESET
UART_UARTIMSC_DCDMIM_ACCESS
UART_UARTIMSC_DCDMIM_BITS
UART_UARTIMSC_DCDMIM_LSB
UART_UARTIMSC_DCDMIM_MSB
UART_UARTIMSC_DCDMIM_RESET
UART_UARTIMSC_DSRMIM_ACCESS
UART_UARTIMSC_DSRMIM_BITS
UART_UARTIMSC_DSRMIM_LSB
UART_UARTIMSC_DSRMIM_MSB
UART_UARTIMSC_DSRMIM_RESET
UART_UARTIMSC_FEIM_ACCESS
UART_UARTIMSC_FEIM_BITS
UART_UARTIMSC_FEIM_LSB
UART_UARTIMSC_FEIM_MSB
UART_UARTIMSC_FEIM_RESET
UART_UARTIMSC_OEIM_ACCESS
UART_UARTIMSC_OEIM_BITS
UART_UARTIMSC_OEIM_LSB
UART_UARTIMSC_OEIM_MSB
UART_UARTIMSC_OEIM_RESET
UART_UARTIMSC_OFFSET
UART_UARTIMSC_PEIM_ACCESS
UART_UARTIMSC_PEIM_BITS
UART_UARTIMSC_PEIM_LSB
UART_UARTIMSC_PEIM_MSB
UART_UARTIMSC_PEIM_RESET
UART_UARTIMSC_RESET
UART_UARTIMSC_RIMIM_ACCESS
UART_UARTIMSC_RIMIM_BITS
UART_UARTIMSC_RIMIM_LSB
UART_UARTIMSC_RIMIM_MSB
UART_UARTIMSC_RIMIM_RESET
UART_UARTIMSC_RTIM_ACCESS
UART_UARTIMSC_RTIM_BITS
UART_UARTIMSC_RTIM_LSB
UART_UARTIMSC_RTIM_MSB
UART_UARTIMSC_RTIM_RESET
UART_UARTIMSC_RXIM_ACCESS
UART_UARTIMSC_RXIM_BITS
UART_UARTIMSC_RXIM_LSB
UART_UARTIMSC_RXIM_MSB
UART_UARTIMSC_RXIM_RESET
UART_UARTIMSC_TXIM_ACCESS
UART_UARTIMSC_TXIM_BITS
UART_UARTIMSC_TXIM_LSB
UART_UARTIMSC_TXIM_MSB
UART_UARTIMSC_TXIM_RESET
UART_UARTLCR_H_BITS
UART_UARTLCR_H_BRK_ACCESS
UART_UARTLCR_H_BRK_BITS
UART_UARTLCR_H_BRK_LSB
UART_UARTLCR_H_BRK_MSB
UART_UARTLCR_H_BRK_RESET
UART_UARTLCR_H_EPS_ACCESS
UART_UARTLCR_H_EPS_BITS
UART_UARTLCR_H_EPS_LSB
UART_UARTLCR_H_EPS_MSB
UART_UARTLCR_H_EPS_RESET
UART_UARTLCR_H_FEN_ACCESS
UART_UARTLCR_H_FEN_BITS
UART_UARTLCR_H_FEN_LSB
UART_UARTLCR_H_FEN_MSB
UART_UARTLCR_H_FEN_RESET
UART_UARTLCR_H_OFFSET
UART_UARTLCR_H_PEN_ACCESS
UART_UARTLCR_H_PEN_BITS
UART_UARTLCR_H_PEN_LSB
UART_UARTLCR_H_PEN_MSB
UART_UARTLCR_H_PEN_RESET
UART_UARTLCR_H_RESET
UART_UARTLCR_H_SPS_ACCESS
UART_UARTLCR_H_SPS_BITS
UART_UARTLCR_H_SPS_LSB
UART_UARTLCR_H_SPS_MSB
UART_UARTLCR_H_SPS_RESET
UART_UARTLCR_H_STP2_ACCESS
UART_UARTLCR_H_STP2_BITS
UART_UARTLCR_H_STP2_LSB
UART_UARTLCR_H_STP2_MSB
UART_UARTLCR_H_STP2_RESET
UART_UARTLCR_H_WLEN_ACCESS
UART_UARTLCR_H_WLEN_BITS
UART_UARTLCR_H_WLEN_LSB
UART_UARTLCR_H_WLEN_MSB
UART_UARTLCR_H_WLEN_RESET
UART_UARTMIS_BEMIS_ACCESS
UART_UARTMIS_BEMIS_BITS
UART_UARTMIS_BEMIS_LSB
UART_UARTMIS_BEMIS_MSB
UART_UARTMIS_BEMIS_RESET
UART_UARTMIS_BITS
UART_UARTMIS_CTSMMIS_ACCESS
UART_UARTMIS_CTSMMIS_BITS
UART_UARTMIS_CTSMMIS_LSB
UART_UARTMIS_CTSMMIS_MSB
UART_UARTMIS_CTSMMIS_RESET
UART_UARTMIS_DCDMMIS_ACCESS
UART_UARTMIS_DCDMMIS_BITS
UART_UARTMIS_DCDMMIS_LSB
UART_UARTMIS_DCDMMIS_MSB
UART_UARTMIS_DCDMMIS_RESET
UART_UARTMIS_DSRMMIS_ACCESS
UART_UARTMIS_DSRMMIS_BITS
UART_UARTMIS_DSRMMIS_LSB
UART_UARTMIS_DSRMMIS_MSB
UART_UARTMIS_DSRMMIS_RESET
UART_UARTMIS_FEMIS_ACCESS
UART_UARTMIS_FEMIS_BITS
UART_UARTMIS_FEMIS_LSB
UART_UARTMIS_FEMIS_MSB
UART_UARTMIS_FEMIS_RESET
UART_UARTMIS_OEMIS_ACCESS
UART_UARTMIS_OEMIS_BITS
UART_UARTMIS_OEMIS_LSB
UART_UARTMIS_OEMIS_MSB
UART_UARTMIS_OEMIS_RESET
UART_UARTMIS_OFFSET
UART_UARTMIS_PEMIS_ACCESS
UART_UARTMIS_PEMIS_BITS
UART_UARTMIS_PEMIS_LSB
UART_UARTMIS_PEMIS_MSB
UART_UARTMIS_PEMIS_RESET
UART_UARTMIS_RESET
UART_UARTMIS_RIMMIS_ACCESS
UART_UARTMIS_RIMMIS_BITS
UART_UARTMIS_RIMMIS_LSB
UART_UARTMIS_RIMMIS_MSB
UART_UARTMIS_RIMMIS_RESET
UART_UARTMIS_RTMIS_ACCESS
UART_UARTMIS_RTMIS_BITS
UART_UARTMIS_RTMIS_LSB
UART_UARTMIS_RTMIS_MSB
UART_UARTMIS_RTMIS_RESET
UART_UARTMIS_RXMIS_ACCESS
UART_UARTMIS_RXMIS_BITS
UART_UARTMIS_RXMIS_LSB
UART_UARTMIS_RXMIS_MSB
UART_UARTMIS_RXMIS_RESET
UART_UARTMIS_TXMIS_ACCESS
UART_UARTMIS_TXMIS_BITS
UART_UARTMIS_TXMIS_LSB
UART_UARTMIS_TXMIS_MSB
UART_UARTMIS_TXMIS_RESET
UART_UARTPCELLID0_BITS
UART_UARTPCELLID0_OFFSET
UART_UARTPCELLID0_RESET
UART_UARTPCELLID0_UARTPCELLID0_ACCESS
UART_UARTPCELLID0_UARTPCELLID0_BITS
UART_UARTPCELLID0_UARTPCELLID0_LSB
UART_UARTPCELLID0_UARTPCELLID0_MSB
UART_UARTPCELLID0_UARTPCELLID0_RESET
UART_UARTPCELLID1_BITS
UART_UARTPCELLID1_OFFSET
UART_UARTPCELLID1_RESET
UART_UARTPCELLID1_UARTPCELLID1_ACCESS
UART_UARTPCELLID1_UARTPCELLID1_BITS
UART_UARTPCELLID1_UARTPCELLID1_LSB
UART_UARTPCELLID1_UARTPCELLID1_MSB
UART_UARTPCELLID1_UARTPCELLID1_RESET
UART_UARTPCELLID2_BITS
UART_UARTPCELLID2_OFFSET
UART_UARTPCELLID2_RESET
UART_UARTPCELLID2_UARTPCELLID2_ACCESS
UART_UARTPCELLID2_UARTPCELLID2_BITS
UART_UARTPCELLID2_UARTPCELLID2_LSB
UART_UARTPCELLID2_UARTPCELLID2_MSB
UART_UARTPCELLID2_UARTPCELLID2_RESET
UART_UARTPCELLID3_BITS
UART_UARTPCELLID3_OFFSET
UART_UARTPCELLID3_RESET
UART_UARTPCELLID3_UARTPCELLID3_ACCESS
UART_UARTPCELLID3_UARTPCELLID3_BITS
UART_UARTPCELLID3_UARTPCELLID3_LSB
UART_UARTPCELLID3_UARTPCELLID3_MSB
UART_UARTPCELLID3_UARTPCELLID3_RESET
UART_UARTPERIPHID0_BITS
UART_UARTPERIPHID0_OFFSET
UART_UARTPERIPHID0_PARTNUMBER0_ACCESS
UART_UARTPERIPHID0_PARTNUMBER0_BITS
UART_UARTPERIPHID0_PARTNUMBER0_LSB
UART_UARTPERIPHID0_PARTNUMBER0_MSB
UART_UARTPERIPHID0_PARTNUMBER0_RESET
UART_UARTPERIPHID0_RESET
UART_UARTPERIPHID1_BITS
UART_UARTPERIPHID1_DESIGNER0_ACCESS
UART_UARTPERIPHID1_DESIGNER0_BITS
UART_UARTPERIPHID1_DESIGNER0_LSB
UART_UARTPERIPHID1_DESIGNER0_MSB
UART_UARTPERIPHID1_DESIGNER0_RESET
UART_UARTPERIPHID1_OFFSET
UART_UARTPERIPHID1_PARTNUMBER1_ACCESS
UART_UARTPERIPHID1_PARTNUMBER1_BITS
UART_UARTPERIPHID1_PARTNUMBER1_LSB
UART_UARTPERIPHID1_PARTNUMBER1_MSB
UART_UARTPERIPHID1_PARTNUMBER1_RESET
UART_UARTPERIPHID1_RESET
UART_UARTPERIPHID2_BITS
UART_UARTPERIPHID2_DESIGNER1_ACCESS
UART_UARTPERIPHID2_DESIGNER1_BITS
UART_UARTPERIPHID2_DESIGNER1_LSB
UART_UARTPERIPHID2_DESIGNER1_MSB
UART_UARTPERIPHID2_DESIGNER1_RESET
UART_UARTPERIPHID2_OFFSET
UART_UARTPERIPHID2_RESET
UART_UARTPERIPHID2_REVISION_ACCESS
UART_UARTPERIPHID2_REVISION_BITS
UART_UARTPERIPHID2_REVISION_LSB
UART_UARTPERIPHID2_REVISION_MSB
UART_UARTPERIPHID2_REVISION_RESET
UART_UARTPERIPHID3_BITS
UART_UARTPERIPHID3_CONFIGURATION_ACCESS
UART_UARTPERIPHID3_CONFIGURATION_BITS
UART_UARTPERIPHID3_CONFIGURATION_LSB
UART_UARTPERIPHID3_CONFIGURATION_MSB
UART_UARTPERIPHID3_CONFIGURATION_RESET
UART_UARTPERIPHID3_OFFSET
UART_UARTPERIPHID3_RESET
UART_UARTRIS_BERIS_ACCESS
UART_UARTRIS_BERIS_BITS
UART_UARTRIS_BERIS_LSB
UART_UARTRIS_BERIS_MSB
UART_UARTRIS_BERIS_RESET
UART_UARTRIS_BITS
UART_UARTRIS_CTSRMIS_ACCESS
UART_UARTRIS_CTSRMIS_BITS
UART_UARTRIS_CTSRMIS_LSB
UART_UARTRIS_CTSRMIS_MSB
UART_UARTRIS_CTSRMIS_RESET
UART_UARTRIS_DCDRMIS_ACCESS
UART_UARTRIS_DCDRMIS_BITS
UART_UARTRIS_DCDRMIS_LSB
UART_UARTRIS_DCDRMIS_MSB
UART_UARTRIS_DCDRMIS_RESET
UART_UARTRIS_DSRRMIS_ACCESS
UART_UARTRIS_DSRRMIS_BITS
UART_UARTRIS_DSRRMIS_LSB
UART_UARTRIS_DSRRMIS_MSB
UART_UARTRIS_DSRRMIS_RESET
UART_UARTRIS_FERIS_ACCESS
UART_UARTRIS_FERIS_BITS
UART_UARTRIS_FERIS_LSB
UART_UARTRIS_FERIS_MSB
UART_UARTRIS_FERIS_RESET
UART_UARTRIS_OERIS_ACCESS
UART_UARTRIS_OERIS_BITS
UART_UARTRIS_OERIS_LSB
UART_UARTRIS_OERIS_MSB
UART_UARTRIS_OERIS_RESET
UART_UARTRIS_OFFSET
UART_UARTRIS_PERIS_ACCESS
UART_UARTRIS_PERIS_BITS
UART_UARTRIS_PERIS_LSB
UART_UARTRIS_PERIS_MSB
UART_UARTRIS_PERIS_RESET
UART_UARTRIS_RESET
UART_UARTRIS_RIRMIS_ACCESS
UART_UARTRIS_RIRMIS_BITS
UART_UARTRIS_RIRMIS_LSB
UART_UARTRIS_RIRMIS_MSB
UART_UARTRIS_RIRMIS_RESET
UART_UARTRIS_RTRIS_ACCESS
UART_UARTRIS_RTRIS_BITS
UART_UARTRIS_RTRIS_LSB
UART_UARTRIS_RTRIS_MSB
UART_UARTRIS_RTRIS_RESET
UART_UARTRIS_RXRIS_ACCESS
UART_UARTRIS_RXRIS_BITS
UART_UARTRIS_RXRIS_LSB
UART_UARTRIS_RXRIS_MSB
UART_UARTRIS_RXRIS_RESET
UART_UARTRIS_TXRIS_ACCESS
UART_UARTRIS_TXRIS_BITS
UART_UARTRIS_TXRIS_LSB
UART_UARTRIS_TXRIS_MSB
UART_UARTRIS_TXRIS_RESET
UART_UARTRSR_BE_ACCESS
UART_UARTRSR_BE_BITS
UART_UARTRSR_BE_LSB
UART_UARTRSR_BE_MSB
UART_UARTRSR_BE_RESET
UART_UARTRSR_BITS
UART_UARTRSR_FE_ACCESS
UART_UARTRSR_FE_BITS
UART_UARTRSR_FE_LSB
UART_UARTRSR_FE_MSB
UART_UARTRSR_FE_RESET
UART_UARTRSR_OE_ACCESS
UART_UARTRSR_OE_BITS
UART_UARTRSR_OE_LSB
UART_UARTRSR_OE_MSB
UART_UARTRSR_OE_RESET
UART_UARTRSR_OFFSET
UART_UARTRSR_PE_ACCESS
UART_UARTRSR_PE_BITS
UART_UARTRSR_PE_LSB
UART_UARTRSR_PE_MSB
UART_UARTRSR_PE_RESET
UART_UARTRSR_RESET
UINT8_MAX
UINT16_MAX
UINT32_MAX
UINT64_MAX
UINTPTR_MAX
UINT_FAST8_MAX
UINT_FAST16_MAX
UINT_FAST32_MAX
UINT_FAST64_MAX
UINT_LEAST8_MAX
UINT_LEAST16_MAX
UINT_LEAST32_MAX
UINT_LEAST64_MAX
USBCTRL_BASE
USBCTRL_DPRAM_BASE
USBCTRL_REGS_BASE
VREG_AND_CHIP_RESET_BASE
WATCHDOG_BASE
WINT_MAX
WINT_MIN
XIP_AUX_BASE
XIP_BASE
XIP_CTRL_BASE
XIP_MAIN_BASE
XIP_NOALLOC_BASE
XIP_NOCACHE_BASE
XIP_NOCACHE_NOALLOC_BASE
XIP_SRAM_BASE
XIP_SRAM_END
XIP_SSI_BASE
XOSC_BASE
XOSC_MHZ
_DARWIN_FEATURE_64_BIT_INODE
_DARWIN_FEATURE_ONLY_UNIX_CONFORMANCE
_DARWIN_FEATURE_UNIX_CONFORMANCE
__DARWIN_64_BIT_INO_T
__DARWIN_C_ANSI
__DARWIN_C_FULL
__DARWIN_C_LEVEL
__DARWIN_NON_CANCELABLE
__DARWIN_NO_LONG_LONG
__DARWIN_ONLY_64_BIT_INO_T
__DARWIN_ONLY_UNIX_CONFORMANCE
__DARWIN_ONLY_VERS_1050
__DARWIN_SUF_64_BIT_INO_T
__DARWIN_SUF_1050
__DARWIN_SUF_EXTSN
__DARWIN_UNIX03
__DARWIN_VERS_1050
__PTHREAD_ATTR_SIZE__
__PTHREAD_CONDATTR_SIZE__
__PTHREAD_COND_SIZE__
__PTHREAD_MUTEXATTR_SIZE__
__PTHREAD_MUTEX_SIZE__
__PTHREAD_ONCE_SIZE__
__PTHREAD_RWLOCKATTR_SIZE__
__PTHREAD_RWLOCK_SIZE__
__PTHREAD_SIZE__
__STDC_WANT_LIB_EXT1__
__WORDSIZE
__bool_true_false_are_defined
false_
gpio_function_GPIO_FUNC_GPCK
gpio_function_GPIO_FUNC_I2C
gpio_function_GPIO_FUNC_NULL
gpio_function_GPIO_FUNC_PIO0
gpio_function_GPIO_FUNC_PIO1
gpio_function_GPIO_FUNC_PWM
gpio_function_GPIO_FUNC_SIO
gpio_function_GPIO_FUNC_SPI
gpio_function_GPIO_FUNC_UART
gpio_function_GPIO_FUNC_USB
gpio_function_GPIO_FUNC_XIP
gpio_irq_level_GPIO_IRQ_EDGE_FALL
gpio_irq_level_GPIO_IRQ_EDGE_RISE
gpio_irq_level_GPIO_IRQ_LEVEL_HIGH
gpio_irq_level_GPIO_IRQ_LEVEL_LOW
gpio_override_GPIO_OVERRIDE_HIGH

< drive high/enable output

gpio_override_GPIO_OVERRIDE_INVERT

< invert peripheral signal selected via \ref gpio_set_function

gpio_override_GPIO_OVERRIDE_LOW

< drive low/disable output

gpio_override_GPIO_OVERRIDE_NORMAL

< peripheral signal selected via \ref gpio_set_function

true_
uart_parity_t_UART_PARITY_EVEN
uart_parity_t_UART_PARITY_NONE
uart_parity_t_UART_PARITY_ODD

Statics

at_the_end_of_time
nil_time

Functions

__assert_rtn
alarm_pool_add_alarm_at

\brief Add an alarm callback to be called at a specific time \ingroup alarm

alarm_pool_add_repeating_timer_us

\brief Add a repeating timer that is called repeatedly at the specified interval in microseconds \ingroup repeating_timer

alarm_pool_cancel_alarm

\brief Cancel an alarm \ingroup alarm \param pool the alarm_pool containing the alarm \param alarm_id the alarm \return true if the alarm was cancelled, false if it didn't exist \sa alarm_id_t for a note on reuse of IDs

alarm_pool_create

\brief Create an alarm pool

alarm_pool_destroy

\brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm \ingroup alarm \param pool the pool \return the hardware alarm used by the pool

alarm_pool_get_default

\brief The default alarm pool used when alarms are added without specifying an alarm pool, and also used by the Pico SDK to support lower power sleeps and timeouts.

alarm_pool_hardware_alarm_num

\brief Return the hardware alarm used by an alarm pool \ingroup alarm \param pool the pool \return the hardware alarm used by the pool

alarm_pool_init_default

\brief Create the default alarm pool (if not already created or disabled) \ingroup alarm

best_effort_wfe_or_timeout

\brief Helper method for blocking on a timeout \ingroup sleep

busy_wait_until

\brief Busy wait wasting cycles until after the specified timestamp \ingroup hardware_timer

busy_wait_us

\brief Busy wait wasting cycles for the given (64 bit) number of microseconds \ingroup hardware_timer

busy_wait_us_32

\brief Busy wait wasting cycles for the given (32 bit) number of microseconds \ingroup hardware_timer

cancel_repeating_timer

\brief Cancel a repeating timer \ingroup repeating_timer \param timer the repeating timer to cancel \return true if the repeating timer was cancelled, false if it didn't exist \sa alarm_id_t for a note on reuse of IDs

check_sys_clock_khz

\brief Check if a given system clock frequency is valid/attainable \ingroup pico_stdlib

getchar_timeout_us

\brief Return a character from stdin if there is one available within a timeout \ingroup pico_stdio

gpio_acknowledge_irq

\brief Acknowledge a GPIO interrupt \ingroup hardware_gpio

gpio_clr_mask
gpio_debug_pins_init
gpio_get_function
gpio_init

\brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO) \ingroup hardware_gpio

gpio_init_mask

\brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO) \ingroup hardware_gpio

gpio_pull_up
gpio_put
gpio_set_dir
gpio_set_dir_in_masked
gpio_set_dir_masked
gpio_set_dir_out_masked
gpio_set_dormant_irq_enabled

\brief Enable dormant wake up interrupt for specified GPIO \ingroup hardware_gpio

gpio_set_function

\brief Select GPIO function \ingroup hardware_gpio

gpio_set_inover

\brief Select GPIO input override \ingroup hardware_gpio

gpio_set_input_enabled

\brief Enable GPIO input \ingroup hardware_gpio

gpio_set_irq_enabled

\brief Enable or disable interrupts for specified GPIO \ingroup hardware_gpio

gpio_set_irq_enabled_with_callback

\brief Enable interrupts for specified GPIO \ingroup hardware_gpio

gpio_set_mask
gpio_set_oeover

\brief Select GPIO output enable override \ingroup hardware_gpio

gpio_set_outover

\brief Set GPIO output override \ingroup hardware_gpio

gpio_set_pulls

\brief Select up and down pulls on specific GPIO \ingroup hardware_gpio

gpio_xor_mask
hardware_alarm_cancel

\brief Cancel an existing target (if any) for a given hardware_alarm

hardware_alarm_claim

\brief cooperatively claim the use of this hardware alarm_num \ingroup hardware_timer

hardware_alarm_set_callback

\brief Enable/Disable a callback for a hardware timer on this core \ingroup hardware_timer

hardware_alarm_set_target

\brief Set the current target for the specified hardware alarm

hardware_alarm_unclaim

\brief cooperatively release the claim on use of this hardware alarm_num \ingroup hardware_timer

panic
panic_unsupported
rp2040_chip_version
running_on_fpga
set_sys_clock_48mhz

\brief Initialise the system clock to 48MHz \ingroup pico_stdlib

set_sys_clock_pll

\brief Initialise the system clock \ingroup pico_stdlib

setup_default_uart

\brief Set up the default UART and assign it to the default GPIO's \ingroup pico_stdlib

sleep_ms

\brief Wait for the given number of milliseconds before returning \ingroup sleep

sleep_until

\brief Wait until after the given timestamp to return \ingroup sleep

sleep_us

\brief Wait for the given number of microseconds before returning \ingroup sleep

stdio_filter_driver

\brief Control limiting of output to a single driver \ingroup pico_stdio

stdio_flush

\brief Initialize all of the present standard stdio types that are linked into the binary. \ingroup pico_stdio

stdio_init_all

\brief Initialize all of the present standard stdio types that are linked into the binary. \ingroup pico_stdio

stdio_set_driver_enabled

\brief Adds or removes a driver from the list of active drivers used for input/output \ingroup pico_stdio

stdio_set_translate_crlf

\brief control conversion of line feeds to carriage return on transmissions \ingroup pico_stdio

time_us_64

\brief Return the current 64 bit timestamp value in microseconds \ingroup hardware_timer

uart_deinit

\brief DeInitialise a UART \ingroup hardware_uart

uart_init

\brief Initialise a UART \ingroup hardware_uart

uart_is_readable_within_us

\brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty \ingroup hardware_uart

uart_set_baudrate

\brief Set UART baud rate \ingroup hardware_uart

uart_set_translate_crlf

\brief Set CR/LF conversion on UART \ingroup hardware_uart

Type Definitions

__builtin_va_list
__darwin_blkcnt_t
__darwin_blksize_t
__darwin_clock_t
__darwin_ct_rune_t
__darwin_dev_t
__darwin_fsblkcnt_t
__darwin_fsfilcnt_t
__darwin_gid_t
__darwin_id_t
__darwin_ino64_t
__darwin_ino_t
__darwin_intptr_t
__darwin_mach_port_name_t
__darwin_mach_port_t
__darwin_mbstate_t
__darwin_mode_t
__darwin_natural_t
__darwin_off_t
__darwin_pid_t
__darwin_pthread_attr_t
__darwin_pthread_cond_t
__darwin_pthread_condattr_t
__darwin_pthread_key_t
__darwin_pthread_mutex_t
__darwin_pthread_mutexattr_t
__darwin_pthread_once_t
__darwin_pthread_rwlock_t
__darwin_pthread_rwlockattr_t
__darwin_pthread_t
__darwin_ptrdiff_t
__darwin_rune_t
__darwin_sigset_t
__darwin_size_t
__darwin_socklen_t
__darwin_ssize_t
__darwin_suseconds_t
__darwin_time_t
__darwin_uid_t
__darwin_useconds_t
__darwin_uuid_string_t
__darwin_uuid_t
__darwin_va_list
__darwin_wchar_t
__darwin_wint_t
__int8_t
__int16_t
__int32_t
__int64_t
__uint8_t
__uint16_t
__uint32_t
__uint64_t
_bindgen_ty_1

Common return codes from pico_sdk methods that return a status

alarm_callback_t

\brief User alarm callback \ingroup alarm \param id the alarm_id as returned when the alarm was added \param user_data the user data passed when the alarm was added \return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire \return >0 to reschedule the same alarm this many us from the time this method returns \return 0 to not reschedule the alarm

alarm_id_t

\brief The identifier for an alarm

alarm_pool_t
const_ioptr
gpio_function

\brief GPIO function definitions for use with function select \ingroup hardware_gpio \brief GPIO function selectors

gpio_irq_callback_t
gpio_irq_level

\brief GPIO Interrupt level definitions \ingroup hardware_gpio \brief GPIO Interrupt levels

gpio_override
hardware_alarm_callback_t

Callback function type for hardware alarms \ingroup hardware_timer

int_fast8_t
int_fast16_t
int_fast32_t
int_fast64_t
int_least8_t
int_least16_t
int_least32_t
int_least64_t
io_ro_8
io_ro_16
io_ro_32
io_rw_8
io_rw_16
io_rw_32
io_wo_8
io_wo_16
io_wo_32
ioptr
max_align_t
register_t
repeating_timer_callback_t

\brief Callback for a repeating timer \ingroup repeating_timer \param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user \return true to continue repeating, false to stop.

repeating_timer_t

\defgroup repeating_timer repeating_timer \ingroup pico_time \brief Repeating Timer functions for simple scheduling of repeated execution

rsize_t
stdio_driver_t
syscall_arg_t
u_int8_t
u_int16_t
u_int32_t
u_int64_t
uart_inst_t

\file hardware/uart.h \defgroup hardware_uart hardware_uart

uart_parity_t

\brief UART Parity enumeration \ingroup hardware_uart

uint
uint_fast8_t
uint_fast16_t
uint_fast32_t
uint_fast64_t
uint_least8_t
uint_least16_t
uint_least32_t
uint_least64_t
user_addr_t
user_long_t
user_off_t
user_size_t
user_ssize_t
user_time_t
user_ulong_t
wchar_t