Module rp2040::pio0::input_sync_bypass

There is a 2-flipflop synchronizer on each GPIO input, which protects\n PIO logic from metastabilities. This increases input delay, and for fast\n synchronous IO (e.g. SPI) these synchronizers may need to be bypassed.\n Each bit in this register corresponds to one GPIO.\n 0 -> input is synchronized (default)\n 1 -> synchronizer is bypassed\n If in doubt, leave this register as all zeroes.

Type Definitions

R	Reader of register INPUT_SYNC_BYPASS
W	Writer for register INPUT_SYNC_BYPASS