Module rp2040::xip_ssi

DW_apb_ssi has the following features:\n * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n * APB3 and APB4 protocol support.\n * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n * Programmable Dual/Quad/Octal SPI support in Master Mode.\n * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n * Programmable features:\n - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n * Configured features:\n - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n - 1 slave select output.\n - Hardware slave-select – Dedicated hardware slave-select line.\n - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - Interrupt polarity – active high interrupt lines.\n - Serial clock polarity – low serial-clock polarity directly after reset.\n - Serial clock phase – capture on first edge of serial-clock directly after reset.

Modules

baudr	Baud rate
ctrlr0	Control register 0
ctrlr1	Master Control register 1
dmacr	DMA control
dmardlr	DMA RX data level
dmatdlr	DMA TX data level
dr0	Data Register 0 (of 36)
icr	Interrupt clear
idr	Identification register
imr	Interrupt mask
isr	Interrupt status
msticr	Multi-master interrupt clear
mwcr	Microwire Control
risr	Raw interrupt status
rx_sample_dly	RX sample delay
rxflr	RX FIFO level
rxftlr	RX FIFO threshold level
rxoicr	RX FIFO overflow interrupt clear
rxuicr	RX FIFO underflow interrupt clear
ser	Slave enable
spi_ctrlr0	SPI control
sr	Status register
ssi_version_id	Version ID
ssienr	SSI Enable
txd_drive_edge	TX drive edge
txflr	TX FIFO level
txftlr	TX FIFO threshold level
txoicr	TX FIFO overflow interrupt clear

Structs

RegisterBlock

Register block

Type Definitions

BAUDR	Baud rate
CTRLR0	Control register 0
CTRLR1	Master Control register 1
DMACR	DMA control
DMARDLR	DMA RX data level
DMATDLR	DMA TX data level
DR0	Data Register 0 (of 36)
ICR	Interrupt clear
IDR	Identification register
IMR	Interrupt mask
ISR	Interrupt status
MSTICR	Multi-master interrupt clear
MWCR	Microwire Control
RISR	Raw interrupt status
RXFLR	RX FIFO level
RXFTLR	RX FIFO threshold level
RXOICR	RX FIFO overflow interrupt clear
RXUICR	RX FIFO underflow interrupt clear
RX_SAMPLE_DLY	RX sample delay
SER	Slave enable
SPI_CTRLR0	SPI control
SR	Status register
SSIENR	SSI Enable
SSI_VERSION_ID	Version ID
TXD_DRIVE_EDGE	TX drive edge
TXFLR	TX FIFO level
TXFTLR	TX FIFO threshold level
TXOICR	TX FIFO overflow interrupt clear