[−][src]Module rp2040::xip_ctrl
QSPI flash execute-in-place block
Modules
| ctr_acc | Cache Access counter\n A 32 bit saturating counter that increments upon each XIP access,\n whether the cache is hit or not. This includes noncacheable accesses.\n Write any value to clear. |
| ctr_hit | Cache Hit counter\n A 32 bit saturating counter that increments upon each cache hit,\n i.e. when an XIP access is serviced directly from cached data.\n Write any value to clear. |
| ctrl | Cache control |
| flush | Cache Flush control |
| stat | Cache Status |
| stream_addr | FIFO stream address |
| stream_ctr | FIFO stream control |
| stream_fifo | FIFO stream data\n Streamed data is buffered here, for retrieval by the system DMA.\n This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n the DMA to bus stalls caused by other XIP traffic. |
Structs
| RegisterBlock | Register block |
Type Definitions
| CTRL | Cache control |
| CTR_ACC | Cache Access counter\n A 32 bit saturating counter that increments upon each XIP access,\n whether the cache is hit or not. This includes noncacheable accesses.\n Write any value to clear. |
| CTR_HIT | Cache Hit counter\n A 32 bit saturating counter that increments upon each cache hit,\n i.e. when an XIP access is serviced directly from cached data.\n Write any value to clear. |
| FLUSH | Cache Flush control |
| STAT | Cache Status |
| STREAM_ADDR | FIFO stream address |
| STREAM_CTR | FIFO stream control |
| STREAM_FIFO | FIFO stream data\n Streamed data is buffered here, for retrieval by the system DMA.\n This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n the DMA to bus stalls caused by other XIP traffic. |