[−][src]Module rp2040::syscfg
Register block for various chip control signals
Modules
| dbgforce | Directly control the SWD debug port of either processor |
| mempowerdown | Control power downs to memories. Set high to power down memories.\n Use with extreme caution |
| proc0_nmi_mask | Processor core 0 NMI source mask\n Set a bit high to enable NMI from that IRQ |
| proc1_nmi_mask | Processor core 1 NMI source mask\n Set a bit high to enable NMI from that IRQ |
| proc_config | Configuration for processors |
| proc_in_sync_bypass | For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 0...29. |
| proc_in_sync_bypass_hi | For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 30...35 (the QSPI IOs). |
Structs
| RegisterBlock | Register block |
Type Definitions
| DBGFORCE | Directly control the SWD debug port of either processor |
| MEMPOWERDOWN | Control power downs to memories. Set high to power down memories.\n Use with extreme caution |
| PROC0_NMI_MASK | Processor core 0 NMI source mask\n Set a bit high to enable NMI from that IRQ |
| PROC1_NMI_MASK | Processor core 1 NMI source mask\n Set a bit high to enable NMI from that IRQ |
| PROC_CONFIG | Configuration for processors |
| PROC_IN_SYNC_BYPASS | For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 0...29. |
| PROC_IN_SYNC_BYPASS_HI | For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 30...35 (the QSPI IOs). |