Struct rp2040::SCB

pub struct SCB { /* fields omitted */ }

System Control Block

Implementations

impl SCB

pub fn vect_active() -> VectActive

Returns the active exception number

impl SCB

pub fn enable_icache(&mut self)

Enables I-cache if currently disabled.

This operation first invalidates the entire I-cache.

pub fn disable_icache(&mut self)

Disables I-cache if currently enabled.

This operation invalidates the entire I-cache after disabling.

pub fn icache_enabled() -> bool

Returns whether the I-cache is currently enabled.

pub fn invalidate_icache(&mut self)

Invalidates the entire I-cache.

pub fn enable_dcache(&mut self, cpuid: &mut CPUID)

Enables D-cache if currently disabled.

This operation first invalidates the entire D-cache, ensuring it does not contain stale values before being enabled.

pub fn disable_dcache(&mut self, cpuid: &mut CPUID)

Disables D-cache if currently enabled.

This operation subsequently cleans and invalidates the entire D-cache, ensuring all contents are safely written back to main memory after disabling.

pub fn dcache_enabled() -> bool

Returns whether the D-cache is currently enabled.

pub fn clean_dcache(&mut self, cpuid: &mut CPUID)

Cleans the entire D-cache.

This function causes everything in the D-cache to be written back to main memory, overwriting whatever is already there.

pub fn clean_invalidate_dcache(&mut self, cpuid: &mut CPUID)

Cleans and invalidates the entire D-cache.

This function causes everything in the D-cache to be written back to main memory, and then marks the entire D-cache as invalid, causing future reads to first fetch from main memory.

pub unsafe fn invalidate_dcache_by_address(&mut self, addr: usize, size: usize)

Invalidates D-cache by address.

• addr: The address to invalidate, which must be cache-line aligned.
• size: Number of bytes to invalidate, which must be a multiple of the cache line size.

Invalidates D-cache cache lines, starting from the first line containing addr, finishing once at least size bytes have been invalidated.

Invalidation causes the next read access to memory to be fetched from main memory instead of the cache.

Cache Line Sizes

Cache line sizes vary by core. For all Cortex-M7 cores, the cache line size is fixed to 32 bytes, which means addr must be 32-byte aligned and size must be a multiple of 32. At the time of writing, no other Cortex-M cores have data caches.

If addr is not cache-line aligned, or size is not a multiple of the cache line size, other data before or after the desired memory would also be invalidated, which can very easily cause memory corruption and undefined behaviour.

Safety

After invalidating, the next read of invalidated data will be from main memory. This may cause recent writes to be lost, potentially including writes that initialized objects. Therefore, this method may cause uninitialized memory or invalid values to be read, resulting in undefined behaviour. You must ensure that main memory contains valid and initialized values before invalidating.

addr must be aligned to the size of the cache lines, and size must be a multiple of the cache line size, otherwise this function will invalidate other memory, easily leading to memory corruption and undefined behaviour. This precondition is checked in debug builds using a debug_assert!(), but not checked in release builds to avoid a runtime-dependent panic!() call.

pub unsafe fn invalidate_dcache_by_ref<T>(&mut self, obj: &mut T)

Invalidates an object from the D-cache.

• obj: The object to invalidate.

Invalidates D-cache starting from the first cache line containing obj, continuing to invalidate cache lines until all of obj has been invalidated.

Invalidation causes the next read access to memory to be fetched from main memory instead of the cache.

Cache Line Sizes

Cache line sizes vary by core. For all Cortex-M7 cores, the cache line size is fixed to 32 bytes, which means obj must be 32-byte aligned, and its size must be a multiple of 32 bytes. At the time of writing, no other Cortex-M cores have data caches.

If obj is not cache-line aligned, or its size is not a multiple of the cache line size, other data before or after the desired memory would also be invalidated, which can very easily cause memory corruption and undefined behaviour.

Safety

After invalidating, obj will be read from main memory on next access. This may cause recent writes to obj to be lost, potentially including the write that initialized it. Therefore, this method may cause uninitialized memory or invalid values to be read, resulting in undefined behaviour. You must ensure that main memory contains a valid and initialized value for T before invalidating obj.

obj must be aligned to the size of the cache lines, and its size must be a multiple of the cache line size, otherwise this function will invalidate other memory, easily leading to memory corruption and undefined behaviour. This precondition is checked in debug builds using a debug_assert!(), but not checked in release builds to avoid a runtime-dependent panic!() call.

pub unsafe fn invalidate_dcache_by_slice<T>(&mut self, slice: &mut [T])

Invalidates a slice from the D-cache.

• slice: The slice to invalidate.

Invalidates D-cache starting from the first cache line containing members of slice, continuing to invalidate cache lines until all of slice has been invalidated.

Invalidation causes the next read access to memory to be fetched from main memory instead of the cache.

Cache Line Sizes

Cache line sizes vary by core. For all Cortex-M7 cores, the cache line size is fixed to 32 bytes, which means slice must be 32-byte aligned, and its size must be a multiple of 32 bytes. At the time of writing, no other Cortex-M cores have data caches.

If slice is not cache-line aligned, or its size is not a multiple of the cache line size, other data before or after the desired memory would also be invalidated, which can very easily cause memory corruption and undefined behaviour.

Safety

After invalidating, slice will be read from main memory on next access. This may cause recent writes to slice to be lost, potentially including the write that initialized it. Therefore, this method may cause uninitialized memory or invalid values to be read, resulting in undefined behaviour. You must ensure that main memory contains valid and initialized values for T before invalidating slice.

slice must be aligned to the size of the cache lines, and its size must be a multiple of the cache line size, otherwise this function will invalidate other memory, easily leading to memory corruption and undefined behaviour. This precondition is checked in debug builds using a debug_assert!(), but not checked in release builds to avoid a runtime-dependent panic!() call.

pub fn clean_dcache_by_address(&mut self, addr: usize, size: usize)

Cleans D-cache by address.

• addr: The address to start cleaning at.
• size: The number of bytes to clean.

Cleans D-cache cache lines, starting from the first line containing addr, finishing once at least size bytes have been invalidated.

Cleaning the cache causes whatever data is present in the cache to be immediately written to main memory, overwriting whatever was in main memory.

Cache Line Sizes

Cache line sizes vary by core. For all Cortex-M7 cores, the cache line size is fixed to 32 bytes, which means addr should generally be 32-byte aligned and size should be a multiple of 32. At the time of writing, no other Cortex-M cores have data caches.

If addr is not cache-line aligned, or size is not a multiple of the cache line size, other data before or after the desired memory will also be cleaned. From the point of view of the core executing this function, memory remains consistent, so this is not unsound, but is worth knowing about.

pub fn clean_dcache_by_ref<T>(&mut self, obj: &T)

Cleans an object from the D-cache.

• obj: The object to clean.

Cleans D-cache starting from the first cache line containing obj, continuing to clean cache lines until all of obj has been cleaned.

It is recommended that obj is both aligned to the cache line size and a multiple of the cache line size long, otherwise surrounding data will also be cleaned.

Cleaning the cache causes whatever data is present in the cache to be immediately written to main memory, overwriting whatever was in main memory.

pub fn clean_dcache_by_slice<T>(&mut self, slice: &[T])

Cleans a slice from D-cache.

• slice: The slice to clean.

Cleans D-cache starting from the first cache line containing members of slice, continuing to clean cache lines until all of slice has been cleaned.

It is recommended that slice is both aligned to the cache line size and a multiple of the cache line size long, otherwise surrounding data will also be cleaned.

Cleaning the cache causes whatever data is present in the cache to be immediately written to main memory, overwriting whatever was in main memory.

pub fn clean_invalidate_dcache_by_address(&mut self, addr: usize, size: usize)

Cleans and invalidates D-cache by address.

• addr: The address to clean and invalidate.
• size: The number of bytes to clean and invalidate.

Cleans and invalidates D-cache starting from the first cache line containing addr, finishing once at least size bytes have been cleaned and invalidated.

It is recommended that addr is aligned to the cache line size and size is a multiple of the cache line size, otherwise surrounding data will also be cleaned.

Cleaning and invalidating causes data in the D-cache to be written back to main memory, and then marks that data in the D-cache as invalid, causing future reads to first fetch from main memory.

impl SCB

pub fn set_sleepdeep(&mut self)

Set the SLEEPDEEP bit in the SCR register

pub fn clear_sleepdeep(&mut self)

Clear the SLEEPDEEP bit in the SCR register

impl SCB

pub fn set_sleeponexit(&mut self)

Set the SLEEPONEXIT bit in the SCR register

pub fn clear_sleeponexit(&mut self)

Clear the SLEEPONEXIT bit in the SCR register

impl SCB

pub fn sys_reset() -> !

Initiate a system reset request to reset the MCU

impl SCB

pub fn set_pendsv()

Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt

pub fn is_pendsv_pending() -> bool

Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending

pub fn clear_pendsv()

Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt

pub fn set_pendst()

Set the PENDSTSET bit in the ICSR register which will pend a SysTick interrupt

pub fn is_pendst_pending() -> bool

Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending

pub fn clear_pendst()

Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt

impl SCB

pub fn get_priority(system_handler: SystemHandler) -> u8

Returns the hardware priority of system_handler

NOTE: Hardware priority does not exactly match logical priority levels. See NVIC.get_priority for more details.

pub unsafe fn set_priority(&mut self, system_handler: SystemHandler, prio: u8)

Sets the hardware priority of system_handler to prio

NOTE: Hardware priority does not exactly match logical priority levels. See NVIC.get_priority for more details.

On ARMv6-M, updating a system handler priority requires a read-modify-write operation. On ARMv7-M, the operation is performed in a single, atomic write operation.

Unsafety

Changing priority levels can break priority-based critical sections (see register::basepri) and compromise memory safety.

pub fn enable(&mut self, exception: Exception)

Enable the exception

If the exception is enabled, when the exception is triggered, the exception handler will be executed instead of the HardFault handler. This function is only allowed on the following exceptions:

• MemoryManagement
• BusFault
• UsageFault
• SecureFault (can only be enabled from Secure state)

Calling this function with any other exception will do nothing.

pub fn disable(&mut self, exception: Exception)

Disable the exception

If the exception is disabled, when the exception is triggered, the HardFault handler will be executed instead of the exception handler. This function is only allowed on the following exceptions:

• MemoryManagement
• BusFault
• UsageFault
• SecureFault (can not be changed from Non-secure state)

Calling this function with any other exception will do nothing.

pub fn is_enabled(&self, exception: Exception) -> bool

Check if an exception is enabled

This function is only allowed on the following exception:

• MemoryManagement
• BusFault
• UsageFault
• SecureFault (can not be read from Non-secure state)

Calling this function with any other exception will read false.

impl SCB

pub const PTR: *const RegisterBlock

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Returns a pointer to the register block (to be deprecated in 0.7)

Trait Implementations

impl Deref for SCB

type Target = RegisterBlock

The resulting type after dereferencing.

pub fn deref(&self) -> &<SCB as Deref>::Target

Dereferences the value.

impl Send for SCB