Module rp2040::ppb

PPB

Modules

aircr	Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
ccr	The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.
cpuid	Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.
icsr	Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.
mpu_ctrl	Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
mpu_rasr	Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.
mpu_rbar	Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.
mpu_rnr	Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.
mpu_type	Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.
nvic_icer	Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
nvic_icpr	Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.
nvic_ipr0	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n These registers are only word-accessible
nvic_ipr1	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
nvic_ipr2	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
nvic_ipr3	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
nvic_ipr4	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
nvic_ipr5	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
nvic_ipr6	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
nvic_ipr7	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
nvic_iser	Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
nvic_ispr	The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.
scr	System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
shcsr	Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
shpr2	System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.
shpr3	System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
syst_calib	Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.
syst_csr	Use the SysTick Control and Status Register to enable the SysTick features.
syst_cvr	Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.
syst_rvr	Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
vtor	The VTOR holds the vector table offset address.

Structs

RegisterBlock

Register block

Type Definitions

AIRCR	Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
CCR	The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.
CPUID	Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.
ICSR	Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.
MPU_CTRL	Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
MPU_RASR	Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.
MPU_RBAR	Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.
MPU_RNR	Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.
MPU_TYPE	Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.
NVIC_ICER	Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
NVIC_ICPR	Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.
NVIC_IPR0	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n These registers are only word-accessible
NVIC_IPR1	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
NVIC_IPR2	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
NVIC_IPR3	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
NVIC_IPR4	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
NVIC_IPR5	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
NVIC_IPR6	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
NVIC_IPR7	Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
NVIC_ISER	Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
NVIC_ISPR	The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.
SCR	System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
SHCSR	Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
SHPR2	System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.
SHPR3	System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
SYST_CALIB	Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.
SYST_CSR	Use the SysTick Control and Status Register to enable the SysTick features.
SYST_CVR	Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.
SYST_RVR	Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
VTOR	The VTOR holds the vector table offset address.