[−][src]Module rp2040::pll_sys
PLL_SYS
Modules
| cs | Control and Status\n GENERAL CONSTRAINTS:\n Reference clock frequency min=5MHz, max=800MHz\n Feedback divider min=16, max=320\n VCO frequency min=400MHz, max=1600MHz |
| fbdiv_int | Feedback divisor\n (note: this PLL does not support fractional division) |
| prim | Controls the PLL post dividers for the primary output\n (note: this PLL does not have a secondary output)\n the primary output is driven from VCO divided by postdiv1*postdiv2 |
| pwr | Controls the PLL power modes. |
Structs
| RegisterBlock | Register block |
Type Definitions
| CS | Control and Status\n GENERAL CONSTRAINTS:\n Reference clock frequency min=5MHz, max=800MHz\n Feedback divider min=16, max=320\n VCO frequency min=400MHz, max=1600MHz |
| FBDIV_INT | Feedback divisor\n (note: this PLL does not support fractional division) |
| PRIM | Controls the PLL post dividers for the primary output\n (note: this PLL does not have a secondary output)\n the primary output is driven from VCO divided by postdiv1*postdiv2 |
| PWR | Controls the PLL power modes. |