[−][src]Crate rp2040
Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.17.0)
You can find an overview of the API here.
Modules
| adc | Control and data interface to SAR ADC |
| busctrl | Register block for busfabric control signals and performance counters |
| clocks | CLOCKS |
| dma | DMA with separate read and write masters |
| generic | Common register and bit access and modify traits |
| i2c0 | DW_apb_i2c address block |
| io_bank0 | IO_BANK0 |
| io_qspi | IO_QSPI |
| pads_bank0 | PADS_BANK0 |
| pads_qspi | PADS_QSPI |
| pio0 | Programmable IO block |
| pll_sys | PLL_SYS |
| ppb | PPB |
| psm | PSM |
| pwm | Simple PWM |
| resets | RESETS |
| rosc | ROSC |
| rtc | Register block to control RTC |
| sio | Single-cycle IO block\n Provides core-local and inter-core hardware for the two processors, with single-cycle access. |
| spi0 | SPI0 |
| syscfg | Register block for various chip control signals |
| sysinfo | SYSINFO |
| tbman | Testbench manager. Allows the programmer to know what platform their software is running on. |
| timer | Controls time and alarms\n time is a 64 bit value indicating the time in usec since power-on\n timeh is the top 32 bits of time & timel is the bottom 32 bits\n to change time write to timelw before timehw\n to read time read from timelr before timehr\n An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n When an alarm is pending, the corresponding alarm_running signal will be high\n An alarm can be cancelled before it has finished by clearing the alarm_enable\n When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n To clear the interrupt write a 1 to the corresponding alarm_irq |
| uart0 | UART0 |
| usbctrl_regs | USB FS/LS controller device registers |
| vreg_and_chip_reset | control and status for on-chip voltage regulator and chip level reset subsystem |
| watchdog | WATCHDOG |
| xip_ctrl | QSPI flash execute-in-place block |
| xip_ssi | DW_apb_ssi has the following features:\n * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n * APB3 and APB4 protocol support.\n * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n * Programmable Dual/Quad/Octal SPI support in Master Mode.\n * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n * Programmable features:\n - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n * Configured features:\n - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n - 1 slave select output.\n - Hardware slave-select – Dedicated hardware slave-select line.\n - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - Interrupt polarity – active high interrupt lines.\n - Serial clock polarity – low serial-clock polarity directly after reset.\n - Serial clock phase – capture on first edge of serial-clock directly after reset. |
| xosc | Controls the crystal oscillator |
Structs
| ADC | Control and data interface to SAR ADC |
| BUSCTRL | Register block for busfabric control signals and performance counters |
| CBP | Cache and branch predictor maintenance operations |
| CLOCKS | CLOCKS |
| CPUID | CPUID |
| CorePeripherals | Core peripherals |
| DCB | Debug Control Block |
| DMA | DMA with separate read and write masters |
| DWT | Data Watchpoint and Trace unit |
| FPB | Flash Patch and Breakpoint unit |
| I2C0 | DW_apb_i2c address block |
| I2C1 | DW_apb_i2c address block |
| IO_BANK0 | IO_BANK0 |
| IO_QSPI | IO_QSPI |
| ITM | Instrumentation Trace Macrocell |
| MPU | Memory Protection Unit |
| NVIC | Nested Vector Interrupt Controller |
| PADS_BANK0 | PADS_BANK0 |
| PADS_QSPI | PADS_QSPI |
| PIO0 | Programmable IO block |
| PIO1 | Programmable IO block |
| PLL_SYS | PLL_SYS |
| PLL_USB | PLL_USB |
| PPB | PPB |
| PSM | PSM |
| PWM | Simple PWM |
| Peripherals | All the peripherals |
| RESETS | RESETS |
| ROSC | ROSC |
| RTC | Register block to control RTC |
| SCB | System Control Block |
| SIO | Single-cycle IO block\n Provides core-local and inter-core hardware for the two processors, with single-cycle access. |
| SPI0 | SPI0 |
| SPI1 | SPI1 |
| SYSCFG | Register block for various chip control signals |
| SYSINFO | SYSINFO |
| SYST | SysTick: System Timer |
| TBMAN | Testbench manager. Allows the programmer to know what platform their software is running on. |
| TIMER | Controls time and alarms\n time is a 64 bit value indicating the time in usec since power-on\n timeh is the top 32 bits of time & timel is the bottom 32 bits\n to change time write to timelw before timehw\n to read time read from timelr before timehr\n An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n When an alarm is pending, the corresponding alarm_running signal will be high\n An alarm can be cancelled before it has finished by clearing the alarm_enable\n When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n To clear the interrupt write a 1 to the corresponding alarm_irq |
| TPIU | Trace Port Interface Unit |
| UART0 | UART0 |
| UART1 | UART1 |
| USBCTRL_REGS | USB FS/LS controller device registers |
| VREG_AND_CHIP_RESET | control and status for on-chip voltage regulator and chip level reset subsystem |
| WATCHDOG | WATCHDOG |
| XIP_CTRL | QSPI flash execute-in-place block |
| XIP_SSI | DW_apb_ssi has the following features:\n * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n * APB3 and APB4 protocol support.\n * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n * Programmable Dual/Quad/Octal SPI support in Master Mode.\n * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n * Programmable features:\n - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n * Configured features:\n - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n - 1 slave select output.\n - Hardware slave-select – Dedicated hardware slave-select line.\n - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - Interrupt polarity – active high interrupt lines.\n - Serial clock polarity – low serial-clock polarity directly after reset.\n - Serial clock phase – capture on first edge of serial-clock directly after reset. |
| XOSC | Controls the crystal oscillator |
Enums
| Interrupt | Enumeration of all the interrupts |
Constants
| NVIC_PRIO_BITS | Number available in the NVIC for configuring priority |