Type Alias rp2040_pac::pio0::INPUT_SYNC_BYPASS

pub type INPUT_SYNC_BYPASS = Reg<INPUT_SYNC_BYPASS_SPEC>;

INPUT_SYNC_BYPASS (rw) register accessor: There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all zeroes.

You can read this register and get input_sync_bypass::R. You can reset, write, write_with_zero this register using input_sync_bypass::W. You can also modify this register. See API.

For information about available fields see input_sync_bypass module

Aliased Type

struct INPUT_SYNC_BYPASS { /* private fields */ }