Module rp2040_pac::sio

Single-cycle IO block\n Provides core-local and inter-core hardware for the two processors, with single-cycle access.

Modules

cpuid	Processor core identifier\n Value is 0 when read from processor core 0, and 1 when read from processor core 1.
div_csr	Control and status register for divider.
div_quotient	Divider result quotient\n The result of DIVIDEND / DIVISOR (division). Contents undefined while CSR_READY is low.\n For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n This register can be written to directly, for context save/restore purposes. This halts any\n in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n REMAINDER, QUOTIENT if CSR_DIRTY is used.
div_remainder	Divider result remainder\n The result of DIVIDEND % DIVISOR (modulo). Contents undefined while CSR_READY is low.\n For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n This register can be written to directly, for context save/restore purposes. This halts any\n in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
div_sdividend	Divider signed dividend\n The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
div_sdivisor	Divider signed divisor\n The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
div_udividend	Divider unsigned dividend\n Write to the DIVIDEND operand of the divider, i.e. the p in p / q.\n Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n unsigned calculation, and the S alias starts a signed calculation.
div_udivisor	Divider unsigned divisor\n Write to the DIVISOR operand of the divider, i.e. the q in p / q.\n Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n unsigned calculation, and the S alias starts a signed calculation.
fifo_rd	Read access to this core’s RX FIFO
fifo_st	Status register for inter-core FIFOs (mailboxes).\n There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
fifo_wr	Write access to this core’s TX FIFO
gpio_hi_in	Input value for QSPI pins
gpio_hi_oe	QSPI output enable
gpio_hi_oe_clr	QSPI output enable clear
gpio_hi_oe_set	QSPI output enable set
gpio_hi_oe_xor	QSPI output enable XOR
gpio_hi_out	QSPI output value
gpio_hi_out_clr	QSPI output value clear
gpio_hi_out_set	QSPI output value set
gpio_hi_out_xor	QSPI output value XOR
gpio_in	Input value for GPIO pins
gpio_oe	GPIO output enable
gpio_oe_clr	GPIO output enable clear
gpio_oe_set	GPIO output enable set
gpio_oe_xor	GPIO output enable XOR
gpio_out	GPIO output value
gpio_out_clr	GPIO output value clear
gpio_out_set	GPIO output value set
gpio_out_xor	GPIO output value XOR
interp0_accum0	Read/write access to accumulator 0
interp0_accum0_add	Values written here are atomically added to ACCUM0\n Reading yields lane 0’s raw shift and mask value (BASE0 not added).
interp0_accum1	Read/write access to accumulator 1
interp0_accum1_add	Values written here are atomically added to ACCUM1\n Reading yields lane 1’s raw shift and mask value (BASE1 not added).
interp0_base0	Read/write access to BASE0 register.
interp0_base1	Read/write access to BASE1 register.
interp0_base2	Read/write access to BASE2 register.
interp0_base_1and0	On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
interp0_ctrl_lane0	Control register for lane 0
interp0_ctrl_lane1	Control register for lane 1
interp0_peek_full	Read FULL result, without altering any internal state (PEEK).
interp0_peek_lane0	Read LANE0 result, without altering any internal state (PEEK).
interp0_peek_lane1	Read LANE1 result, without altering any internal state (PEEK).
interp0_pop_full	Read FULL result, and simultaneously write lane results to both accumulators (POP).
interp0_pop_lane0	Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
interp0_pop_lane1	Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
interp1_accum0	Read/write access to accumulator 0
interp1_accum0_add	Values written here are atomically added to ACCUM0\n Reading yields lane 0’s raw shift and mask value (BASE0 not added).
interp1_accum1	Read/write access to accumulator 1
interp1_accum1_add	Values written here are atomically added to ACCUM1\n Reading yields lane 1’s raw shift and mask value (BASE1 not added).
interp1_base0	Read/write access to BASE0 register.
interp1_base1	Read/write access to BASE1 register.
interp1_base2	Read/write access to BASE2 register.
interp1_base_1and0	On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
interp1_ctrl_lane0	Control register for lane 0
interp1_ctrl_lane1	Control register for lane 1
interp1_peek_full	Read FULL result, without altering any internal state (PEEK).
interp1_peek_lane0	Read LANE0 result, without altering any internal state (PEEK).
interp1_peek_lane1	Read LANE1 result, without altering any internal state (PEEK).
interp1_pop_full	Read FULL result, and simultaneously write lane results to both accumulators (POP).
interp1_pop_lane0	Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
interp1_pop_lane1	Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
spinlock0	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock1	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock2	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock3	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock4	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock5	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock6	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock7	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock8	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock9	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock10	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock11	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock12	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock13	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock14	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock15	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock16	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock17	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock18	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock19	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock20	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock21	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock22	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock23	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock24	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock25	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock26	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock27	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock28	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock29	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock30	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock31	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
spinlock_st	Spinlock state\n A bitmap containing the state of all 32 spinlocks (1=locked).\n Mainly intended for debugging.

Structs

RegisterBlock

Register block

Type Definitions

CPUID	Processor core identifier\n Value is 0 when read from processor core 0, and 1 when read from processor core 1.
DIV_CSR	Control and status register for divider.
DIV_QUOTIENT	Divider result quotient\n The result of DIVIDEND / DIVISOR (division). Contents undefined while CSR_READY is low.\n For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n This register can be written to directly, for context save/restore purposes. This halts any\n in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n REMAINDER, QUOTIENT if CSR_DIRTY is used.
DIV_REMAINDER	Divider result remainder\n The result of DIVIDEND % DIVISOR (modulo). Contents undefined while CSR_READY is low.\n For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n This register can be written to directly, for context save/restore purposes. This halts any\n in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
DIV_SDIVIDEND	Divider signed dividend\n The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
DIV_SDIVISOR	Divider signed divisor\n The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
DIV_UDIVIDEND	Divider unsigned dividend\n Write to the DIVIDEND operand of the divider, i.e. the p in p / q.\n Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n unsigned calculation, and the S alias starts a signed calculation.
DIV_UDIVISOR	Divider unsigned divisor\n Write to the DIVISOR operand of the divider, i.e. the q in p / q.\n Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n unsigned calculation, and the S alias starts a signed calculation.
FIFO_RD	Read access to this core’s RX FIFO
FIFO_ST	Status register for inter-core FIFOs (mailboxes).\n There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
FIFO_WR	Write access to this core’s TX FIFO
GPIO_HI_IN	Input value for QSPI pins
GPIO_HI_OE	QSPI output enable
GPIO_HI_OE_CLR	QSPI output enable clear
GPIO_HI_OE_SET	QSPI output enable set
GPIO_HI_OE_XOR	QSPI output enable XOR
GPIO_HI_OUT	QSPI output value
GPIO_HI_OUT_CLR	QSPI output value clear
GPIO_HI_OUT_SET	QSPI output value set
GPIO_HI_OUT_XOR	QSPI output value XOR
GPIO_IN	Input value for GPIO pins
GPIO_OE	GPIO output enable
GPIO_OE_CLR	GPIO output enable clear
GPIO_OE_SET	GPIO output enable set
GPIO_OE_XOR	GPIO output enable XOR
GPIO_OUT	GPIO output value
GPIO_OUT_CLR	GPIO output value clear
GPIO_OUT_SET	GPIO output value set
GPIO_OUT_XOR	GPIO output value XOR
INTERP0_ACCUM0	Read/write access to accumulator 0
INTERP0_ACCUM0_ADD	Values written here are atomically added to ACCUM0\n Reading yields lane 0’s raw shift and mask value (BASE0 not added).
INTERP0_ACCUM1	Read/write access to accumulator 1
INTERP0_ACCUM1_ADD	Values written here are atomically added to ACCUM1\n Reading yields lane 1’s raw shift and mask value (BASE1 not added).
INTERP0_BASE0	Read/write access to BASE0 register.
INTERP0_BASE1	Read/write access to BASE1 register.
INTERP0_BASE2	Read/write access to BASE2 register.
INTERP0_BASE_1AND0	On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
INTERP0_CTRL_LANE0	Control register for lane 0
INTERP0_CTRL_LANE1	Control register for lane 1
INTERP0_PEEK_FULL	Read FULL result, without altering any internal state (PEEK).
INTERP0_PEEK_LANE0	Read LANE0 result, without altering any internal state (PEEK).
INTERP0_PEEK_LANE1	Read LANE1 result, without altering any internal state (PEEK).
INTERP0_POP_FULL	Read FULL result, and simultaneously write lane results to both accumulators (POP).
INTERP0_POP_LANE0	Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
INTERP0_POP_LANE1	Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
INTERP1_ACCUM0	Read/write access to accumulator 0
INTERP1_ACCUM0_ADD	Values written here are atomically added to ACCUM0\n Reading yields lane 0’s raw shift and mask value (BASE0 not added).
INTERP1_ACCUM1	Read/write access to accumulator 1
INTERP1_ACCUM1_ADD	Values written here are atomically added to ACCUM1\n Reading yields lane 1’s raw shift and mask value (BASE1 not added).
INTERP1_BASE0	Read/write access to BASE0 register.
INTERP1_BASE1	Read/write access to BASE1 register.
INTERP1_BASE2	Read/write access to BASE2 register.
INTERP1_BASE_1AND0	On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
INTERP1_CTRL_LANE0	Control register for lane 0
INTERP1_CTRL_LANE1	Control register for lane 1
INTERP1_PEEK_FULL	Read FULL result, without altering any internal state (PEEK).
INTERP1_PEEK_LANE0	Read LANE0 result, without altering any internal state (PEEK).
INTERP1_PEEK_LANE1	Read LANE1 result, without altering any internal state (PEEK).
INTERP1_POP_FULL	Read FULL result, and simultaneously write lane results to both accumulators (POP).
INTERP1_POP_LANE0	Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
INTERP1_POP_LANE1	Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
SPINLOCK0	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK1	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK2	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK3	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK4	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK5	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK6	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK7	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK8	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK9	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK10	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK11	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK12	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK13	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK14	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK15	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK16	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK17	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK18	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK19	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK20	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK21	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK22	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK23	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK24	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK25	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK26	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK27	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK28	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK29	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK30	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK31	Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number.
SPINLOCK_ST	Spinlock state\n A bitmap containing the state of all 32 spinlocks (1=locked).\n Mainly intended for debugging.