Module rp2040_pac::pio0

Programmable IO block

Modules

ctrl	PIO control register
dbg_cfginfo	The PIO hardware has some free parameters that may vary between chip products.\n These should be provided in the chip datasheet, but are also exposed here.
dbg_padoe	Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs.
dbg_padout	Read to sample the pad output values PIO is currently driving to the GPIOs.
fdebug	FIFO debug register
flevel	FIFO levels
fstat	FIFO status register
input_sync_bypass	There is a 2-flipflop synchronizer on each GPIO input, which protects\n PIO logic from metastabilities. This increases input delay, and for fast\n synchronous IO (e.g. SPI) these synchronizers may need to be bypassed.\n Each bit in this register corresponds to one GPIO.\n 0 -> input is synchronized (default)\n 1 -> synchronizer is bypassed\n If in doubt, leave this register as all zeroes.
instr_mem	Write-only access to instruction memory location 0
intr	Raw Interrupts
irq	Interrupt request register. Write 1 to clear
irq_force	Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.\n Note this is different to the INTF register: writing here affects PIO internal\n state. INTF just asserts the processor-facing IRQ signal for testing ISRs,\n and is not visible to the state machines.
rxf	Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO.
sm	Register block Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL
sm_irq	Register block Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS
txf	Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO.

Structs

RegisterBlock	Register block
SM	Register block
SM_IRQ	Register block

Type Definitions

CTRL	PIO control register
DBG_CFGINFO	The PIO hardware has some free parameters that may vary between chip products.\n These should be provided in the chip datasheet, but are also exposed here.
DBG_PADOE	Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs.
DBG_PADOUT	Read to sample the pad output values PIO is currently driving to the GPIOs.
FDEBUG	FIFO debug register
FLEVEL	FIFO levels
FSTAT	FIFO status register
INPUT_SYNC_BYPASS	There is a 2-flipflop synchronizer on each GPIO input, which protects\n PIO logic from metastabilities. This increases input delay, and for fast\n synchronous IO (e.g. SPI) these synchronizers may need to be bypassed.\n Each bit in this register corresponds to one GPIO.\n 0 -> input is synchronized (default)\n 1 -> synchronizer is bypassed\n If in doubt, leave this register as all zeroes.
INSTR_MEM	Write-only access to instruction memory location 0
INTR	Raw Interrupts
IRQ	Interrupt request register. Write 1 to clear
IRQ_FORCE	Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.\n Note this is different to the INTF register: writing here affects PIO internal\n state. INTF just asserts the processor-facing IRQ signal for testing ISRs,\n and is not visible to the state machines.
RXF	Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO.
TXF	Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO.