Module rp2040_hal::pll

Phase-Locked Loops (PLL)

Modules

common_configs

Common configs for the two PLLs. Both assume the XOSC is cadenced at 12MHz ! See Chapter 2, Section 18, §2

Structs

Disabled

PLL is disabled.

Locked

PLL is locked : it delivers a steady frequency.

LockedPLLToken

A token that’s given when the PLL is properly locked, so we can safely transition to the next state.

Locking

PLL is configured, started and locking into its designated frequency.

PLLConfig

Parameters for a PLL.

PhaseLockedLoop

A PLL.

Enums

Error

Error type for the PLL module. See Chapter 2, Section 18 §2 for details on constraints triggering these errors.

Traits

PhaseLockedLoopDevice

Trait to handle both underlying devices from the PAC (PLL_SYS & PLL_USB)

State

State of the PLL

Functions

setup_pll_blocking

Blocking helper method to setup the PLL without going through all the steps.