#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkAdcCtrl(pub u32);
impl ClkAdcCtrl {
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkAdcCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkAdcCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkAdcCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub const fn kill(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub fn set_kill(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub const fn enable(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub fn set_enable(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub const fn phase(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub fn set_phase(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub const fn nudge(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub fn set_nudge(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for ClkAdcCtrl {
#[inline(always)]
fn default() -> ClkAdcCtrl {
ClkAdcCtrl(0)
}
}
#[doc = "Clock divisor, can be changed on-the-fly"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkAdcDiv(pub u32);
impl ClkAdcDiv {
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub const fn int(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x03;
val as u8
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub fn set_int(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
}
}
impl Default for ClkAdcDiv {
#[inline(always)]
fn default() -> ClkAdcDiv {
ClkAdcDiv(0)
}
}
#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkGpoutCtrl(pub u32);
impl ClkGpoutCtrl {
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkGpoutCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x0f;
super::vals::ClkGpoutCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkGpoutCtrlAuxsrc) {
self.0 = (self.0 & !(0x0f << 5usize)) | (((val.to_bits() as u32) & 0x0f) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub const fn kill(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub fn set_kill(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub const fn enable(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub fn set_enable(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Enables duty cycle correction for odd divisors"]
#[inline(always)]
pub const fn dc50(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Enables duty cycle correction for odd divisors"]
#[inline(always)]
pub fn set_dc50(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub const fn phase(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub fn set_phase(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub const fn nudge(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub fn set_nudge(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for ClkGpoutCtrl {
#[inline(always)]
fn default() -> ClkGpoutCtrl {
ClkGpoutCtrl(0)
}
}
#[doc = "Clock divisor, can be changed on-the-fly"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkGpoutDiv(pub u32);
impl ClkGpoutDiv {
#[doc = "Fractional component of the divisor"]
#[inline(always)]
pub const fn frac(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "Fractional component of the divisor"]
#[inline(always)]
pub fn set_frac(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub const fn int(&self) -> u32 {
let val = (self.0 >> 8usize) & 0x00ff_ffff;
val as u32
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub fn set_int(&mut self, val: u32) {
self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize);
}
}
impl Default for ClkGpoutDiv {
#[inline(always)]
fn default() -> ClkGpoutDiv {
ClkGpoutDiv(0)
}
}
#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkPeriCtrl(pub u32);
impl ClkPeriCtrl {
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkPeriCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkPeriCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkPeriCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub const fn kill(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub fn set_kill(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub const fn enable(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub fn set_enable(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
}
impl Default for ClkPeriCtrl {
#[inline(always)]
fn default() -> ClkPeriCtrl {
ClkPeriCtrl(0)
}
}
#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkRefCtrl(pub u32);
impl ClkRefCtrl {
#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
#[inline(always)]
pub const fn src(&self) -> super::vals::ClkRefCtrlSrc {
let val = (self.0 >> 0usize) & 0x03;
super::vals::ClkRefCtrlSrc::from_bits(val as u8)
}
#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
#[inline(always)]
pub fn set_src(&mut self, val: super::vals::ClkRefCtrlSrc) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkRefCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x03;
super::vals::ClkRefCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkRefCtrlAuxsrc) {
self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize);
}
}
impl Default for ClkRefCtrl {
#[inline(always)]
fn default() -> ClkRefCtrl {
ClkRefCtrl(0)
}
}
#[doc = "Clock divisor, can be changed on-the-fly"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkRefDiv(pub u32);
impl ClkRefDiv {
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub const fn int(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x03;
val as u8
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub fn set_int(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
}
}
impl Default for ClkRefDiv {
#[inline(always)]
fn default() -> ClkRefDiv {
ClkRefDiv(0)
}
}
#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkRtcCtrl(pub u32);
impl ClkRtcCtrl {
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkRtcCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkRtcCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkRtcCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub const fn kill(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub fn set_kill(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub const fn enable(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub fn set_enable(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub const fn phase(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub fn set_phase(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub const fn nudge(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub fn set_nudge(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for ClkRtcCtrl {
#[inline(always)]
fn default() -> ClkRtcCtrl {
ClkRtcCtrl(0)
}
}
#[doc = "Clock divisor, can be changed on-the-fly"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkRtcDiv(pub u32);
impl ClkRtcDiv {
#[doc = "Fractional component of the divisor"]
#[inline(always)]
pub const fn frac(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "Fractional component of the divisor"]
#[inline(always)]
pub fn set_frac(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub const fn int(&self) -> u32 {
let val = (self.0 >> 8usize) & 0x00ff_ffff;
val as u32
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub fn set_int(&mut self, val: u32) {
self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize);
}
}
impl Default for ClkRtcDiv {
#[inline(always)]
fn default() -> ClkRtcDiv {
ClkRtcDiv(0)
}
}
#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkSysCtrl(pub u32);
impl ClkSysCtrl {
#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
#[inline(always)]
pub const fn src(&self) -> super::vals::ClkSysCtrlSrc {
let val = (self.0 >> 0usize) & 0x01;
super::vals::ClkSysCtrlSrc::from_bits(val as u8)
}
#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
#[inline(always)]
pub fn set_src(&mut self, val: super::vals::ClkSysCtrlSrc) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkSysCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkSysCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkSysCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
}
impl Default for ClkSysCtrl {
#[inline(always)]
fn default() -> ClkSysCtrl {
ClkSysCtrl(0)
}
}
#[doc = "Clock divisor, can be changed on-the-fly"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkSysDiv(pub u32);
impl ClkSysDiv {
#[doc = "Fractional component of the divisor"]
#[inline(always)]
pub const fn frac(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "Fractional component of the divisor"]
#[inline(always)]
pub fn set_frac(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub const fn int(&self) -> u32 {
let val = (self.0 >> 8usize) & 0x00ff_ffff;
val as u32
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub fn set_int(&mut self, val: u32) {
self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize);
}
}
impl Default for ClkSysDiv {
#[inline(always)]
fn default() -> ClkSysDiv {
ClkSysDiv(0)
}
}
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkSysResusCtrl(pub u32);
impl ClkSysResusCtrl {
#[doc = "This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
#[inline(always)]
pub const fn timeout(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
#[inline(always)]
pub fn set_timeout(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "Enable resus"]
#[inline(always)]
pub const fn enable(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Enable resus"]
#[inline(always)]
pub fn set_enable(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Force a resus, for test purposes only"]
#[inline(always)]
pub const fn frce(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Force a resus, for test purposes only"]
#[inline(always)]
pub fn set_frce(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "For clearing the resus after the fault that triggered it has been corrected"]
#[inline(always)]
pub const fn clear(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "For clearing the resus after the fault that triggered it has been corrected"]
#[inline(always)]
pub fn set_clear(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
}
impl Default for ClkSysResusCtrl {
#[inline(always)]
fn default() -> ClkSysResusCtrl {
ClkSysResusCtrl(0)
}
}
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkSysResusStatus(pub u32);
impl ClkSysResusStatus {
#[doc = "Clock has been resuscitated, correct the error then send ctrl_clear=1"]
#[inline(always)]
pub const fn resussed(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Clock has been resuscitated, correct the error then send ctrl_clear=1"]
#[inline(always)]
pub fn set_resussed(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for ClkSysResusStatus {
#[inline(always)]
fn default() -> ClkSysResusStatus {
ClkSysResusStatus(0)
}
}
#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkUsbCtrl(pub u32);
impl ClkUsbCtrl {
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkUsbCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkUsbCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkUsbCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub const fn kill(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
pub fn set_kill(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub const fn enable(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Starts and stops the clock generator cleanly"]
#[inline(always)]
pub fn set_enable(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub const fn phase(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
#[inline(always)]
pub fn set_phase(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub const fn nudge(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
#[inline(always)]
pub fn set_nudge(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for ClkUsbCtrl {
#[inline(always)]
fn default() -> ClkUsbCtrl {
ClkUsbCtrl(0)
}
}
#[doc = "Clock divisor, can be changed on-the-fly"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkUsbDiv(pub u32);
impl ClkUsbDiv {
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub const fn int(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x03;
val as u8
}
#[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
#[inline(always)]
pub fn set_int(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
}
}
impl Default for ClkUsbDiv {
#[inline(always)]
fn default() -> ClkUsbDiv {
ClkUsbDiv(0)
}
}
#[doc = "indicates the state of the clock enable"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Enabled0(pub u32);
impl Enabled0 {
#[inline(always)]
pub const fn clk_sys_clocks(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_clocks(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[inline(always)]
pub const fn clk_adc_adc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_adc_adc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[inline(always)]
pub const fn clk_sys_adc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_adc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[inline(always)]
pub const fn clk_sys_busctrl(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_busctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[inline(always)]
pub const fn clk_sys_busfabric(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_busfabric(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[inline(always)]
pub const fn clk_sys_dma(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_dma(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[inline(always)]
pub const fn clk_sys_i2c0(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_i2c0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[inline(always)]
pub const fn clk_sys_i2c1(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_i2c1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[inline(always)]
pub const fn clk_sys_io(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_io(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[inline(always)]
pub const fn clk_sys_jtag(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_jtag(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[inline(always)]
pub const fn clk_sys_vreg_and_chip_reset(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_vreg_and_chip_reset(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[inline(always)]
pub const fn clk_sys_pads(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pads(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[inline(always)]
pub const fn clk_sys_pio0(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pio0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[inline(always)]
pub const fn clk_sys_pio1(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pio1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[inline(always)]
pub const fn clk_sys_pll_sys(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pll_sys(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[inline(always)]
pub const fn clk_sys_pll_usb(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pll_usb(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[inline(always)]
pub const fn clk_sys_psm(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_psm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[inline(always)]
pub const fn clk_sys_pwm(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pwm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[inline(always)]
pub const fn clk_sys_resets(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_resets(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[inline(always)]
pub const fn clk_sys_rom(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rom(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[inline(always)]
pub const fn clk_sys_rosc(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rosc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[inline(always)]
pub const fn clk_rtc_rtc(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_rtc_rtc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[inline(always)]
pub const fn clk_sys_rtc(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rtc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[inline(always)]
pub const fn clk_sys_sio(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sio(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[inline(always)]
pub const fn clk_peri_spi0(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_spi0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[inline(always)]
pub const fn clk_sys_spi0(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_spi0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[inline(always)]
pub const fn clk_peri_spi1(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_spi1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[inline(always)]
pub const fn clk_sys_spi1(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_spi1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[inline(always)]
pub const fn clk_sys_sram0(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[inline(always)]
pub const fn clk_sys_sram1(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[inline(always)]
pub const fn clk_sys_sram2(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[inline(always)]
pub const fn clk_sys_sram3(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram3(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Enabled0 {
#[inline(always)]
fn default() -> Enabled0 {
Enabled0(0)
}
}
#[doc = "indicates the state of the clock enable"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Enabled1(pub u32);
impl Enabled1 {
#[inline(always)]
pub const fn clk_sys_sram4(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram4(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[inline(always)]
pub const fn clk_sys_sram5(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram5(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[inline(always)]
pub const fn clk_sys_syscfg(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_syscfg(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[inline(always)]
pub const fn clk_sys_sysinfo(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sysinfo(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[inline(always)]
pub const fn clk_sys_tbman(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_tbman(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[inline(always)]
pub const fn clk_sys_timer(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_timer(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[inline(always)]
pub const fn clk_peri_uart0(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_uart0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[inline(always)]
pub const fn clk_sys_uart0(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_uart0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[inline(always)]
pub const fn clk_peri_uart1(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_uart1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[inline(always)]
pub const fn clk_sys_uart1(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_uart1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[inline(always)]
pub const fn clk_sys_usbctrl(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_usbctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[inline(always)]
pub const fn clk_usb_usbctrl(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_usb_usbctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[inline(always)]
pub const fn clk_sys_watchdog(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_watchdog(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[inline(always)]
pub const fn clk_sys_xip(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_xip(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[inline(always)]
pub const fn clk_sys_xosc(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_xosc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for Enabled1 {
#[inline(always)]
fn default() -> Enabled1 {
Enabled1(0)
}
}
#[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0delay(pub u32);
impl Fc0delay {
#[inline(always)]
pub const fn fc0_delay(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x07;
val as u8
}
#[inline(always)]
pub fn set_fc0_delay(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
}
}
impl Default for Fc0delay {
#[inline(always)]
fn default() -> Fc0delay {
Fc0delay(0)
}
}
#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0interval(pub u32);
impl Fc0interval {
#[inline(always)]
pub const fn fc0_interval(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_fc0_interval(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
}
impl Default for Fc0interval {
#[inline(always)]
fn default() -> Fc0interval {
Fc0interval(0)
}
}
#[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0maxKhz(pub u32);
impl Fc0maxKhz {
#[inline(always)]
pub const fn fc0_max_khz(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x01ff_ffff;
val as u32
}
#[inline(always)]
pub fn set_fc0_max_khz(&mut self, val: u32) {
self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
}
}
impl Default for Fc0maxKhz {
#[inline(always)]
fn default() -> Fc0maxKhz {
Fc0maxKhz(0)
}
}
#[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0minKhz(pub u32);
impl Fc0minKhz {
#[inline(always)]
pub const fn fc0_min_khz(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x01ff_ffff;
val as u32
}
#[inline(always)]
pub fn set_fc0_min_khz(&mut self, val: u32) {
self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
}
}
impl Default for Fc0minKhz {
#[inline(always)]
fn default() -> Fc0minKhz {
Fc0minKhz(0)
}
}
#[doc = "Reference clock frequency in kHz"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0refKhz(pub u32);
impl Fc0refKhz {
#[inline(always)]
pub const fn fc0_ref_khz(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x000f_ffff;
val as u32
}
#[inline(always)]
pub fn set_fc0_ref_khz(&mut self, val: u32) {
self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
}
}
impl Default for Fc0refKhz {
#[inline(always)]
fn default() -> Fc0refKhz {
Fc0refKhz(0)
}
}
#[doc = "Result of frequency measurement, only valid when status_done=1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0result(pub u32);
impl Fc0result {
#[inline(always)]
pub const fn frac(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x1f;
val as u8
}
#[inline(always)]
pub fn set_frac(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
}
#[inline(always)]
pub const fn khz(&self) -> u32 {
let val = (self.0 >> 5usize) & 0x01ff_ffff;
val as u32
}
#[inline(always)]
pub fn set_khz(&mut self, val: u32) {
self.0 = (self.0 & !(0x01ff_ffff << 5usize)) | (((val as u32) & 0x01ff_ffff) << 5usize);
}
}
impl Default for Fc0result {
#[inline(always)]
fn default() -> Fc0result {
Fc0result(0)
}
}
#[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0src(pub u32);
impl Fc0src {
#[inline(always)]
pub const fn fc0_src(&self) -> super::vals::Fc0src {
let val = (self.0 >> 0usize) & 0xff;
super::vals::Fc0src::from_bits(val as u8)
}
#[inline(always)]
pub fn set_fc0_src(&mut self, val: super::vals::Fc0src) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize);
}
}
impl Default for Fc0src {
#[inline(always)]
fn default() -> Fc0src {
Fc0src(0)
}
}
#[doc = "Frequency counter status"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fc0status(pub u32);
impl Fc0status {
#[doc = "Test passed"]
#[inline(always)]
pub const fn pass(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Test passed"]
#[inline(always)]
pub fn set_pass(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Test complete"]
#[inline(always)]
pub const fn done(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Test complete"]
#[inline(always)]
pub fn set_done(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Test running"]
#[inline(always)]
pub const fn running(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Test running"]
#[inline(always)]
pub fn set_running(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Waiting for test clock to start"]
#[inline(always)]
pub const fn waiting(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Waiting for test clock to start"]
#[inline(always)]
pub fn set_waiting(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "Test failed"]
#[inline(always)]
pub const fn fail(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Test failed"]
#[inline(always)]
pub fn set_fail(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Test clock slower than expected, only valid when status_done=1"]
#[inline(always)]
pub const fn slow(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Test clock slower than expected, only valid when status_done=1"]
#[inline(always)]
pub fn set_slow(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Test clock faster than expected, only valid when status_done=1"]
#[inline(always)]
pub const fn fast(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Test clock faster than expected, only valid when status_done=1"]
#[inline(always)]
pub fn set_fast(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Test clock stopped during test"]
#[inline(always)]
pub const fn died(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Test clock stopped during test"]
#[inline(always)]
pub fn set_died(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
}
impl Default for Fc0status {
#[inline(always)]
fn default() -> Fc0status {
Fc0status(0)
}
}
#[doc = "Interrupt Force"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Int(pub u32);
impl Int {
#[inline(always)]
pub const fn clk_sys_resus(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_resus(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for Int {
#[inline(always)]
fn default() -> Int {
Int(0)
}
}
#[doc = "enable clock in sleep mode"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SleepEn0(pub u32);
impl SleepEn0 {
#[inline(always)]
pub const fn clk_sys_clocks(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_clocks(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[inline(always)]
pub const fn clk_adc_adc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_adc_adc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[inline(always)]
pub const fn clk_sys_adc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_adc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[inline(always)]
pub const fn clk_sys_busctrl(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_busctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[inline(always)]
pub const fn clk_sys_busfabric(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_busfabric(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[inline(always)]
pub const fn clk_sys_dma(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_dma(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[inline(always)]
pub const fn clk_sys_i2c0(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_i2c0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[inline(always)]
pub const fn clk_sys_i2c1(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_i2c1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[inline(always)]
pub const fn clk_sys_io(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_io(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[inline(always)]
pub const fn clk_sys_jtag(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_jtag(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[inline(always)]
pub const fn clk_sys_vreg_and_chip_reset(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_vreg_and_chip_reset(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[inline(always)]
pub const fn clk_sys_pads(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pads(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[inline(always)]
pub const fn clk_sys_pio0(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pio0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[inline(always)]
pub const fn clk_sys_pio1(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pio1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[inline(always)]
pub const fn clk_sys_pll_sys(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pll_sys(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[inline(always)]
pub const fn clk_sys_pll_usb(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pll_usb(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[inline(always)]
pub const fn clk_sys_psm(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_psm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[inline(always)]
pub const fn clk_sys_pwm(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pwm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[inline(always)]
pub const fn clk_sys_resets(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_resets(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[inline(always)]
pub const fn clk_sys_rom(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rom(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[inline(always)]
pub const fn clk_sys_rosc(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rosc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[inline(always)]
pub const fn clk_rtc_rtc(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_rtc_rtc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[inline(always)]
pub const fn clk_sys_rtc(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rtc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[inline(always)]
pub const fn clk_sys_sio(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sio(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[inline(always)]
pub const fn clk_peri_spi0(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_spi0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[inline(always)]
pub const fn clk_sys_spi0(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_spi0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[inline(always)]
pub const fn clk_peri_spi1(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_spi1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[inline(always)]
pub const fn clk_sys_spi1(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_spi1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[inline(always)]
pub const fn clk_sys_sram0(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[inline(always)]
pub const fn clk_sys_sram1(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[inline(always)]
pub const fn clk_sys_sram2(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[inline(always)]
pub const fn clk_sys_sram3(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram3(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for SleepEn0 {
#[inline(always)]
fn default() -> SleepEn0 {
SleepEn0(0)
}
}
#[doc = "enable clock in sleep mode"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SleepEn1(pub u32);
impl SleepEn1 {
#[inline(always)]
pub const fn clk_sys_sram4(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram4(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[inline(always)]
pub const fn clk_sys_sram5(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram5(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[inline(always)]
pub const fn clk_sys_syscfg(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_syscfg(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[inline(always)]
pub const fn clk_sys_sysinfo(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sysinfo(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[inline(always)]
pub const fn clk_sys_tbman(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_tbman(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[inline(always)]
pub const fn clk_sys_timer(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_timer(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[inline(always)]
pub const fn clk_peri_uart0(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_uart0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[inline(always)]
pub const fn clk_sys_uart0(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_uart0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[inline(always)]
pub const fn clk_peri_uart1(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_uart1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[inline(always)]
pub const fn clk_sys_uart1(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_uart1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[inline(always)]
pub const fn clk_sys_usbctrl(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_usbctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[inline(always)]
pub const fn clk_usb_usbctrl(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_usb_usbctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[inline(always)]
pub const fn clk_sys_watchdog(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_watchdog(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[inline(always)]
pub const fn clk_sys_xip(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_xip(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[inline(always)]
pub const fn clk_sys_xosc(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_xosc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for SleepEn1 {
#[inline(always)]
fn default() -> SleepEn1 {
SleepEn1(0)
}
}
#[doc = "enable clock in wake mode"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WakeEn0(pub u32);
impl WakeEn0 {
#[inline(always)]
pub const fn clk_sys_clocks(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_clocks(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[inline(always)]
pub const fn clk_adc_adc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_adc_adc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[inline(always)]
pub const fn clk_sys_adc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_adc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[inline(always)]
pub const fn clk_sys_busctrl(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_busctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[inline(always)]
pub const fn clk_sys_busfabric(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_busfabric(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[inline(always)]
pub const fn clk_sys_dma(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_dma(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[inline(always)]
pub const fn clk_sys_i2c0(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_i2c0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[inline(always)]
pub const fn clk_sys_i2c1(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_i2c1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[inline(always)]
pub const fn clk_sys_io(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_io(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[inline(always)]
pub const fn clk_sys_jtag(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_jtag(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[inline(always)]
pub const fn clk_sys_vreg_and_chip_reset(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_vreg_and_chip_reset(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[inline(always)]
pub const fn clk_sys_pads(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pads(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[inline(always)]
pub const fn clk_sys_pio0(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pio0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[inline(always)]
pub const fn clk_sys_pio1(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pio1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[inline(always)]
pub const fn clk_sys_pll_sys(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pll_sys(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[inline(always)]
pub const fn clk_sys_pll_usb(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pll_usb(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[inline(always)]
pub const fn clk_sys_psm(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_psm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[inline(always)]
pub const fn clk_sys_pwm(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_pwm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[inline(always)]
pub const fn clk_sys_resets(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_resets(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[inline(always)]
pub const fn clk_sys_rom(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rom(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[inline(always)]
pub const fn clk_sys_rosc(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rosc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[inline(always)]
pub const fn clk_rtc_rtc(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_rtc_rtc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[inline(always)]
pub const fn clk_sys_rtc(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_rtc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[inline(always)]
pub const fn clk_sys_sio(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sio(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[inline(always)]
pub const fn clk_peri_spi0(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_spi0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[inline(always)]
pub const fn clk_sys_spi0(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_spi0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[inline(always)]
pub const fn clk_peri_spi1(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_spi1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[inline(always)]
pub const fn clk_sys_spi1(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_spi1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[inline(always)]
pub const fn clk_sys_sram0(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[inline(always)]
pub const fn clk_sys_sram1(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[inline(always)]
pub const fn clk_sys_sram2(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[inline(always)]
pub const fn clk_sys_sram3(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram3(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for WakeEn0 {
#[inline(always)]
fn default() -> WakeEn0 {
WakeEn0(0)
}
}
#[doc = "enable clock in wake mode"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WakeEn1(pub u32);
impl WakeEn1 {
#[inline(always)]
pub const fn clk_sys_sram4(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram4(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[inline(always)]
pub const fn clk_sys_sram5(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sram5(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[inline(always)]
pub const fn clk_sys_syscfg(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_syscfg(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[inline(always)]
pub const fn clk_sys_sysinfo(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_sysinfo(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[inline(always)]
pub const fn clk_sys_tbman(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_tbman(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[inline(always)]
pub const fn clk_sys_timer(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_timer(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[inline(always)]
pub const fn clk_peri_uart0(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_uart0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[inline(always)]
pub const fn clk_sys_uart0(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_uart0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[inline(always)]
pub const fn clk_peri_uart1(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_peri_uart1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[inline(always)]
pub const fn clk_sys_uart1(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_uart1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[inline(always)]
pub const fn clk_sys_usbctrl(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_usbctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[inline(always)]
pub const fn clk_usb_usbctrl(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_usb_usbctrl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[inline(always)]
pub const fn clk_sys_watchdog(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_watchdog(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[inline(always)]
pub const fn clk_sys_xip(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_xip(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[inline(always)]
pub const fn clk_sys_xosc(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_clk_sys_xosc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for WakeEn1 {
#[inline(always)]
fn default() -> WakeEn1 {
WakeEn1(0)
}
}