Struct rk3399_rs::PcieClient
source · pub struct PcieClient { /* private fields */ }Expand description
PCIe Client
Implementations§
source§impl PcieClient
impl PcieClient
sourcepub const PTR: *const RegisterBlock = {0xfd000000 as *const pcie_client::RegisterBlock}
pub const PTR: *const RegisterBlock = {0xfd000000 as *const pcie_client::RegisterBlock}
Pointer to the register block
sourcepub const fn ptr() -> *const RegisterBlock
pub const fn ptr() -> *const RegisterBlock
Return the pointer to the register block
sourcepub unsafe fn steal() -> Self
pub unsafe fn steal() -> Self
Steal an instance of this peripheral
§Safety
Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.
Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.
Methods from Deref<Target = RegisterBlock>§
sourcepub fn pcie_client_basic_strap_conf(&self) -> &PcieClientBasicStrapConf
pub fn pcie_client_basic_strap_conf(&self) -> &PcieClientBasicStrapConf
0x00 - Basic strap configuration register
sourcepub fn pcie_client_power_ctrl(&self) -> &PcieClientPowerCtrl
pub fn pcie_client_power_ctrl(&self) -> &PcieClientPowerCtrl
0x04 - PCIe client power control configuration
sourcepub fn pcie_client_power_status(&self) -> &PcieClientPowerStatus
pub fn pcie_client_power_status(&self) -> &PcieClientPowerStatus
0x08 - PCIe power management status
sourcepub fn pcie_client_legacy_int_ctrl(&self) -> &PcieClientLegacyIntCtrl
pub fn pcie_client_legacy_int_ctrl(&self) -> &PcieClientLegacyIntCtrl
0x0c - Legacy interrupt control
sourcepub fn pcie_client_err_ctrl(&self) -> &PcieClientErrCtrl
pub fn pcie_client_err_ctrl(&self) -> &PcieClientErrCtrl
0x10 - Error control register
sourcepub fn pcie_client_err_cnt(&self) -> &PcieClientErrCnt
pub fn pcie_client_err_cnt(&self) -> &PcieClientErrCnt
0x14 - Error counter
sourcepub fn pcie_client_hot_reset_ctrl(&self) -> &PcieClientHotResetCtrl
pub fn pcie_client_hot_reset_ctrl(&self) -> &PcieClientHotResetCtrl
0x18 - Hot reset control
sourcepub fn pcie_client_side_band_ctrl(&self) -> &PcieClientSideBandCtrl
pub fn pcie_client_side_band_ctrl(&self) -> &PcieClientSideBandCtrl
0x1c - Side band control configuration
sourcepub fn pcie_client_side_band_status(&self) -> &PcieClientSideBandStatus
pub fn pcie_client_side_band_status(&self) -> &PcieClientSideBandStatus
0x20 - Side band status
sourcepub fn pcie_client_fc_level_rst_done(&self) -> &PcieClientFcLevelRstDone
pub fn pcie_client_fc_level_rst_done(&self) -> &PcieClientFcLevelRstDone
0x24 - Generate function level reset done pulse
sourcepub fn pcie_client_flr_status(&self) -> &PcieClientFlrStatus
pub fn pcie_client_flr_status(&self) -> &PcieClientFlrStatus
0x28 - Function level reset status
sourcepub fn pcie_client_vf_status(&self) -> &PcieClientVfStatus
pub fn pcie_client_vf_status(&self) -> &PcieClientVfStatus
0x2c - Virtual function status
sourcepub fn pcie_client_vf_pwr_status(&self) -> &PcieClientVfPwrStatus
pub fn pcie_client_vf_pwr_status(&self) -> &PcieClientVfPwrStatus
0x30 - Virtual function power status
sourcepub fn pcie_client_vf_tph_status(&self) -> &PcieClientVfTphStatus
pub fn pcie_client_vf_tph_status(&self) -> &PcieClientVfTphStatus
0x34 - Virtual function TPH status
sourcepub fn pcie_client_tph_status(&self) -> &PcieClientTphStatus
pub fn pcie_client_tph_status(&self) -> &PcieClientTphStatus
0x38 - Physical TPH status
sourcepub fn pcie_client_debug_out_0(&self) -> &PcieClientDebugOut0
pub fn pcie_client_debug_out_0(&self) -> &PcieClientDebugOut0
0x3c - Debug information 0
sourcepub fn pcie_client_debug_out_1(&self) -> &PcieClientDebugOut1
pub fn pcie_client_debug_out_1(&self) -> &PcieClientDebugOut1
0x40 - Debug information 1
sourcepub fn pcie_client_basic_status0(&self) -> &PcieClientBasicStatus0
pub fn pcie_client_basic_status0(&self) -> &PcieClientBasicStatus0
0x44 - Basic status 0
sourcepub fn pcie_client_basic_status1(&self) -> &PcieClientBasicStatus1
pub fn pcie_client_basic_status1(&self) -> &PcieClientBasicStatus1
0x48 - Basic status 1
sourcepub fn pcie_client_int_mask(&self) -> &PcieClientIntMask
pub fn pcie_client_int_mask(&self) -> &PcieClientIntMask
0x4c - Interrupt mask
sourcepub fn pcie_client_int_status(&self) -> &PcieClientIntStatus
pub fn pcie_client_int_status(&self) -> &PcieClientIntStatus
0x50 - Interrupt status
sourcepub fn pcie_client_msg_ctrl(&self) -> &PcieClientMsgCtrl
pub fn pcie_client_msg_ctrl(&self) -> &PcieClientMsgCtrl
0x54 - Message receive control register
sourcepub fn pcie_client_msg_status(&self) -> &PcieClientMsgStatus
pub fn pcie_client_msg_status(&self) -> &PcieClientMsgStatus
0x58 - Message control status
sourcepub fn pcie_client_msg_code0(&self) -> &PcieClientMsgCode0
pub fn pcie_client_msg_code0(&self) -> &PcieClientMsgCode0
0x5c - Message code 0
sourcepub fn pcie_client_msg_code1(&self) -> &PcieClientMsgCode1
pub fn pcie_client_msg_code1(&self) -> &PcieClientMsgCode1
0x60 - Message code 1
sourcepub fn pcie_client_msg_data_len(&self) -> &PcieClientMsgDataLen
pub fn pcie_client_msg_data_len(&self) -> &PcieClientMsgDataLen
0x64 - Message data length
sourcepub fn pcie_client_msg_fifo_rd_data(&self) -> &PcieClientMsgFifoRdData
pub fn pcie_client_msg_fifo_rd_data(&self) -> &PcieClientMsgFifoRdData
0x100 - Message fifo read data
sourcepub fn pcie_client_conf_nu0(&self) -> &PcieClientConfNu0
pub fn pcie_client_conf_nu0(&self) -> &PcieClientConfNu0
0x200 - Configuration no used
sourcepub fn pcie_client_conf_nu1(&self) -> &PcieClientConfNu1
pub fn pcie_client_conf_nu1(&self) -> &PcieClientConfNu1
0x204 - Configuration no used