Crate rk3399_rs

Peripheral access API for RK3399 microcontrollers (generated using svd2rust v0.32.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports

• pub use self::qos as qos_cci_m0;
• pub use self::errlog_slv as err_logger_slv0;
• pub use self::errlog_slv as err_logger_slv1;
• pub use self::errlog_msch as err_logger_msch0;
• pub use self::errlog_msch as err_logger_msch1;
• pub use self::msch as msch0;
• pub use self::msch as msch1;
• pub use self::probe as ic_probe_cci_msch0;
• pub use self::probe as ic_probe_gpu_msch0;
• pub use self::probe as ic_probe_perihp_msch0;
• pub use self::probe as ic_probe_perilp_msch0;
• pub use self::probe as ic_probe_video_msch0;
• pub use self::probe as ic_probe_vio0_msch0;
• pub use self::probe as ic_probe_vio1_msch0;
• pub use self::probe as ic_probe_cci_msch1;
• pub use self::probe as ic_probe_gpu_msch1;
• pub use self::probe as ic_probe_perihp_msch1;
• pub use self::probe as ic_probe_perilp_msch1;
• pub use self::probe as ic_probe_video_msch1;
• pub use self::probe as ic_probe_vio0_msch1;
• pub use self::probe as ic_probe_vio1_msch1;
• pub use self::ddr_pi as ddr_pi0;
• pub use self::ddr_pi as ddr_pi1;
• pub use self::mmu as mmu0_isp0;
• pub use self::mmu as mmu1_isp0;
• pub use self::mmu as mmu0_isp1;
• pub use self::mmu as mmu1_isp1;
• pub use self::mmu as mmu_vopb;
• pub use self::mmu as mmu_vopl;
• pub use self::mmu as mmu_iep;
• pub use self::mmu as mmu_hdcp;
• pub use self::timer as timer0;
• pub use self::timer as timer1;
• pub use self::timer as timer2;
• pub use self::timer as timer3;
• pub use self::timer as timer4;
• pub use self::timer as timer5;
• pub use self::timer as timer6;
• pub use self::timer as timer7;
• pub use self::timer as timer8;
• pub use self::timer as timer9;
• pub use self::timer as timer10;
• pub use self::timer as timer11;
• pub use self::timer as stimer0;
• pub use self::timer as stimer1;
• pub use self::timer as stimer2;
• pub use self::timer as stimer3;
• pub use self::timer as stimer4;
• pub use self::timer as stimer5;
• pub use self::timer as stimer6;
• pub use self::timer as stimer7;
• pub use self::timer as stimer8;
• pub use self::timer as stimer9;
• pub use self::timer as stimer10;
• pub use self::timer as stimer11;
• pub use self::dmac as dmac0;
• pub use self::dmac as dmac1;
• pub use self::mailbox as mailbox0;
• pub use self::mailbox as mailbox1;
• pub use self::efuse as efuse0;
• pub use self::efuse as efuse1;
• pub use self::wdt as wdt0;
• pub use self::wdt as wdt1;
• pub use self::wdt as wdt2;
• pub use self::usb3 as usb3_otg0;
• pub use self::usb3 as usb3_otg1;
• pub use self::uart as uart0;
• pub use self::uart as uart1;
• pub use self::uart as uart2;
• pub use self::uart as uart3;
• pub use self::uart as uart4;
• pub use self::gpio as gpio0;
• pub use self::gpio as gpio1;
• pub use self::gpio as gpio2;
• pub use self::gpio as gpio3;
• pub use self::gpio as gpio4;
• pub use self::rki2c as i2c0;
• pub use self::rki2c as i2c1;
• pub use self::rki2c as i2c2;
• pub use self::rki2c as i2c3;
• pub use self::rki2c as i2c4;
• pub use self::rki2c as i2c5;
• pub use self::rki2c as i2c6;
• pub use self::rki2c as i2c7;
• pub use self::rki2c as i2c8;
• pub use self::i2s as i2s0;
• pub use self::i2s as i2s1;
• pub use self::i2s as i2s2;
• pub use self::spi as spi0;
• pub use self::spi as spi1;
• pub use self::spi as spi2;
• pub use self::spi as spi3;
• pub use self::spi as spi4;
• pub use self::spi as spi5;
• pub use self::emmccore as emmc;

Modules

• cci500
  Cache Coherent Interconnect 500
• cru
  Clock and Reset Unit
• ddr_cic
  DDR Controller Interface Control
• ddr_ctl0
  DDR CTL 0
• ddr_ctl1
  DDR CTL 1
• ddr_mon
  DDR Monitor
• ddr_phy0
  DDR PHY 0
• ddr_phy1
  DDR PHY 1
• ddr_pi
  DDR_PI Registers
• dmac
  DMAC Registers
• dp
  DisplayPort
• efuse
  EFUSE Registers
• emmccore
  EMMCCORE Registers
• errlog_msch
  ERRLOG_MSCH Registers
• errlog_slv
  ERRLOG_SLV Registers
• generic
  Common register and bit access and modify traits
• gmac
  Gigabit Media Access Controller
• gpio
  GPIO Registers
• grf
  General Register File
• hdmi
  HDMI
• i2s
  I2S Registers
• mailbox
  MAILBOX Registers
• mmu
  MMU Registers
• msch
  MSCH Registers
• pcie_at_ep_ib
  EP Address Translation Register (Inbound)
• pcie_at_ob
  Address Translation Register (Outbound)
• pcie_at_rp_ib
  RP Address Translation Register (Inbound)
• pcie_client
  PCIe Client
• pcie_dma
  DMA Configuration Register
• pcie_lm
  Local Management Register
• pcie_pf
  Physical Function Configuration Register
• pcie_rc
  Root Port Configuration Register
• pcie_vf
  Virtual Function Configuration Register
• pmu
  Power Management Unit
• pmucru
  Power Management Unit Clock and Reset Unit
• pmugrf
  Power Management Unit General Register File
• probe
  PROBE Registers
• pwm
  Pulse Width Modulation
• qos
  QOS Registers
• qos_cci_m1
  QOS Registers for CCI_M1
• qos_crypto0
  QOS Registers for CRYPTO0
• qos_crypto1
  QOS Registers for CRYPTO1
• qos_dcf
  QOS Registers for DCF
• qos_dmac0
  QOS Registers for DMAC0
• qos_dmac1
  QOS Registers for DMAC1
• qos_emmc
  QOS Registers for EMMC
• qos_gic
  QOS Registers for GIC
• qos_gmac
  QOS Registers for GMAC
• qos_gpu
  QOS Registers for GPU
• qos_hdcp
  QOS Registers for HDCP
• qos_hsic
  QOS Registers for HSIC
• qos_iep
  QOS Registers for IEP
• qos_isp0_m0
  QOS Registers for ISP0_M0
• qos_isp0_m1
  QOS Registers for ISP0_M1
• qos_isp1_m0
  QOS Registers for ISP1_M0
• qos_isp1_m1
  QOS Registers for ISP1_M1
• qos_pcie
  QOS Registers for PCIE
• qos_peri_cm0
  QOS Registers for PERI_CM0
• qos_perihp_nsp
  QOS Registers for PERIHP_NSP
• qos_perilp_nsp
  QOS Registers for PERILP_NSP
• qos_perilpslv_nsp
  QOS Registers for PERILPSLV_NSP
• qos_pmu_cm0
  QOS Registers for PMU_CM0
• qos_rga_r
  QOS Registers for RGA_R
• qos_rga_w
  QOS Registers for RGA_W
• qos_sdio
  QOS Registers for SDIO
• qos_sdmmc
  QOS Registers for SDMMC
• qos_usb_host0
  QOS Registers for USB_HOST0
• qos_usb_host1
  QOS Registers for USB_HOST1
• qos_usb_otg0
  QOS Registers for USB_OTG0
• qos_usb_otg1
  QOS Registers for USB_OTG1
• qos_video_m0
  QOS Registers for VIDEO_M0
• qos_video_m1_r
  QOS Registers for VIDEO_M1_R
• qos_video_m1_w
  QOS Registers for VIDEO_M1_W
• qos_vop_big_r
  QOS Registers for VOP-BIG_R
• qos_vop_big_w
  QOS Registers for VOP-BIG_W
• qos_vop_little
  QOS Registers for VOP-LITTLE
• rki2c
  RKI2C Registers
• saradc
  Successive Approximation Register Analog-to-Digital Converter
• sdmmc
  Secure Digital MultiMedia Card
• spdif
  Sony/Philips Digital Interface
• spi
  SPI Registers
• timer
  TIMER Registers
• tsadc
  Temperature Sensor Analog-to-Digital Converter
• uart
  UART Registers
• usb3
  USB3 Registers
• wdt
  WDT Registers

Structs

• Cci500
  Cache Coherent Interconnect 500
• Cru
  Clock and Reset Unit
• DdrCic
  DDR Controller Interface Control
• DdrCtl0
  DDR CTL 0
• DdrCtl1
  DDR CTL 1
• DdrMon
  DDR Monitor
• DdrPhy0
  DDR PHY 0
• DdrPhy1
  DDR PHY 1
• DdrPi
  DDR_PI Registers
• DdrPi0
  DDR PHY Independent Register 0
• DdrPi1
  DDR PHY Independent Register 1
• Dmac
  DMAC Registers
• Dmac0
  DMA Controller 0
• Dmac1
  DMA Controller 1
• Dp
  DisplayPort
• Efuse
  EFUSE Registers
• Efuse0
  eFuse 0
• Efuse1
  eFuse 1
• Emmc
  eMMC Controller
• Emmccore
  EMMCCORE Registers
• ErrLoggerMsch0
  Error Logger covering paths from all masters to the memory schedule 0
• ErrLoggerMsch1
  Error Logger covering paths from all masters to the memory schedule 1
• ErrLoggerSlv0
  Error Logger covering paths from all masters except the PMU of the Cortex-M0 to all slaves outside the PMU power domain
• ErrLoggerSlv1
  Error Logger covering paths from the PMU of the Cortex-M0 to all slaves inside the PMU power domain
• ErrlogMsch
  ERRLOG_MSCH Registers
• ErrlogSlv
  ERRLOG_SLV Registers
• Gmac
  Gigabit Media Access Controller
• Gpio
  GPIO Registers
• Gpio0
  General Purpose Input/Output 0
• Gpio1
  General Purpose Input/Output 1
• Gpio2
  General Purpose Input/Output 2
• Gpio3
  General Purpose Input/Output 3
• Gpio4
  General Purpose Input/Output 4
• Grf
  General Register File
• Hdmi
  HDMI
• I2c0
  Rockchip Inter-Integrated Circuit 0
• I2c1
  Rockchip Inter-Integrated Circuit 1
• I2c2
  Rockchip Inter-Integrated Circuit 2
• I2c3
  Rockchip Inter-Integrated Circuit 3
• I2c4
  Rockchip Inter-Integrated Circuit 4
• I2c5
  Rockchip Inter-Integrated Circuit 5
• I2c6
  Rockchip Inter-Integrated Circuit 6
• I2c7
  Rockchip Inter-Integrated Circuit 7
• I2c8
  Rockchip Inter-Integrated Circuit 8
• I2s
  I2S Registers
• I2s0
  Inter-IC Sound 0
• I2s1
  Inter-IC Sound 1
• I2s2
  Inter-IC Sound 2
• IcProbeCciMsch0
  Probe covering paths from the CCI_M1 to the memory schedule 0
• IcProbeCciMsch1
  Probe covering paths from the CCI_M1 to the memory schedule 1
• IcProbeGpuMsch0
  Probe covering paths from the GPU to the memory schedule 0
• IcProbeGpuMsch1
  Probe covering paths from the GPU to the memory schedule 1
• IcProbePerihpMsch0
  Probe covering paths from the perihp master NIU to the memory schedule 0
• IcProbePerihpMsch1
  Probe covering paths from the perihp master NIU to the memory schedule 1
• IcProbePerilpMsch0
  Probe covering paths from the perilp master NIU, debug and CCI_M0 to the memory schedule 0
• IcProbePerilpMsch1
  Probe covering paths from the perilp master NIU, debug and CCI_M0 to the memory schedule 1
• IcProbeVideoMsch0
  Probe covering paths from video to the memory schedule 0
• IcProbeVideoMsch1
  Probe covering paths from video to the memory schedule 1
• IcProbeVio0Msch0
  Probe covering paths from the IEP, ISP0 and VOP-BIG to the memory schedule 0
• IcProbeVio0Msch1
  Probe covering paths from the IEP, ISP0 and VOP-BIG to the memory schedule 1
• IcProbeVio1Msch0
  Probe covering paths from the RGA, ISP1, VOP-LITTLE and HDCP to the memory schedule 0
• IcProbeVio1Msch1
  Probe covering paths from the RGA, ISP1, VOP-LITTLE and HDCP to the memory schedule 1
• Mailbox
  MAILBOX Registers
• Mailbox0
  Mailbox 0
• Mailbox1
  Mailbox 1
• Mmu
  MMU Registers
• Mmu0Isp0
  ISP0 MMU0
• Mmu0Isp1
  ISP1 MMU0
• Mmu1Isp0
  ISP0 MMU1
• Mmu1Isp1
  ISP1 MMU1
• MmuHdcp
  HDCP MMU
• MmuIep
  IEP MMU
• MmuVopb
  VOPB MMU
• MmuVopl
  VOPL MMU
• Msch
  MSCH Registers
• Msch0
  Memory Schedule 0
• Msch1
  Memory Schedule 1
• PcieAtEpIb
  EP Address Translation Register (Inbound)
• PcieAtOb
  Address Translation Register (Outbound)
• PcieAtRpIb
  RP Address Translation Register (Inbound)
• PcieClient
  PCIe Client
• PcieDma
  DMA Configuration Register
• PcieLm
  Local Management Register
• PciePf
  Physical Function Configuration Register
• PcieRc
  Root Port Configuration Register
• PcieVf
  Virtual Function Configuration Register
• Peripherals
  All the peripherals.
• Pmu
  Power Management Unit
• Pmucru
  Power Management Unit Clock and Reset Unit
• Pmugrf
  Power Management Unit General Register File
• Probe
  PROBE Registers
• Pwm
  Pulse Width Modulation
• Qos
  QOS Registers
• QosCciM0
  QOS Registers for CCI_M0
• QosCciM1
  QOS Registers for CCI_M1
• QosCrypto0
  QOS Registers for CRYPTO0
• QosCrypto1
  QOS Registers for CRYPTO1
• QosDcf
  QOS Registers for DCF
• QosDmac0
  QOS Registers for DMAC0
• QosDmac1
  QOS Registers for DMAC1
• QosEmmc
  QOS Registers for EMMC
• QosGic
  QOS Registers for GIC
• QosGmac
  QOS Registers for GMAC
• QosGpu
  QOS Registers for GPU
• QosHdcp
  QOS Registers for HDCP
• QosHsic
  QOS Registers for HSIC
• QosIep
  QOS Registers for IEP
• QosIsp0M0
  QOS Registers for ISP0_M0
• QosIsp0M1
  QOS Registers for ISP0_M1
• QosIsp1M0
  QOS Registers for ISP1_M0
• QosIsp1M1
  QOS Registers for ISP1_M1
• QosPcie
  QOS Registers for PCIE
• QosPeriCm0
  QOS Registers for PERI_CM0
• QosPerihpNsp
  QOS Registers for PERIHP_NSP
• QosPerilpNsp
  QOS Registers for PERILP_NSP
• QosPerilpslvNsp
  QOS Registers for PERILPSLV_NSP
• QosPmuCm0
  QOS Registers for PMU_CM0
• QosRgaR
  QOS Registers for RGA_R
• QosRgaW
  QOS Registers for RGA_W
• QosSdio
  QOS Registers for SDIO
• QosSdmmc
  QOS Registers for SDMMC
• QosUsbHost0
  QOS Registers for USB_HOST0
• QosUsbHost1
  QOS Registers for USB_HOST1
• QosUsbOtg0
  QOS Registers for USB_OTG0
• QosUsbOtg1
  QOS Registers for USB_OTG1
• QosVideoM0
  QOS Registers for VIDEO_M0
• QosVideoM1R
  QOS Registers for VIDEO_M1_R
• QosVideoM1W
  QOS Registers for VIDEO_M1_W
• QosVopBigR
  QOS Registers for VOP-BIG_R
• QosVopBigW
  QOS Registers for VOP-BIG_W
• QosVopLittle
  QOS Registers for VOP-LITTLE
• Rki2c
  RKI2C Registers
• Saradc
  Successive Approximation Register Analog-to-Digital Converter
• Sdmmc
  Secure Digital MultiMedia Card
• Spdif
  Sony/Philips Digital Interface
• Spi
  SPI Registers
• Spi0
  Serial Peripheral Interface 0
• Spi1
  Serial Peripheral Interface 1
• Spi2
  Serial Peripheral Interface 2
• Spi3
  Serial Peripheral Interface 3
• Spi4
  Serial Peripheral Interface 4
• Spi5
  Serial Peripheral Interface 5
• Stimer0
  Secure Timer 0
• Stimer1
  Secure Timer 1
• Stimer2
  Secure Timer 2
• Stimer3
  Secure Timer 3
• Stimer4
  Secure Timer 4
• Stimer5
  Secure Timer 5
• Stimer6
  Secure Timer 6
• Stimer7
  Secure Timer 7
• Stimer8
  Secure Timer 8
• Stimer9
  Secure Timer 9
• Stimer10
  Secure Timer 10
• Stimer11
  Secure Timer 11
• Timer
  TIMER Registers
• Timer0
  Timer 0
• Timer1
  Timer 1
• Timer2
  Timer 2
• Timer3
  Timer 3
• Timer4
  Timer 4
• Timer5
  Timer 5
• Timer6
  Timer 6
• Timer7
  Timer 7
• Timer8
  Timer 8
• Timer9
  Timer 9
• Timer10
  Timer 10
• Timer11
  Timer 11
• Tsadc
  Temperature Sensor Analog-to-Digital Converter
• Uart
  UART Registers
• Uart0
  Universal Asynchronous Receiver/Transmitter 0
• Uart1
  Universal Asynchronous Receiver/Transmitter 1
• Uart2
  Universal Asynchronous Receiver/Transmitter 2
• Uart3
  Universal Asynchronous Receiver/Transmitter 3
• Uart4
  Universal Asynchronous Receiver/Transmitter 4
• Usb3
  USB3 Registers
• Usb3Otg0
  USB 3.0/2.0 OTG Register 0
• Usb3Otg1
  USB 3.0/2.0 OTG Register 1
• Wdt
  WDT Registers
• Wdt0
  Watchdog Timer 0
• Wdt1
  Watchdog Timer 1
• Wdt2
  Watchdog Timer 2

Constants

• NVIC_PRIO_BITS
  Number available in the NVIC for configuring priority