Expand description
Peripheral access API for RK3399 microcontrollers (generated using svd2rust v0.32.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open
.
Re-exports§
pub use self::slv_err_logger0 as slv_err_logger1;
pub use self::msch_err_logger0 as msch_err_logger1;
pub use self::msch0 as msch1;
pub use self::cci_probe_msch0 as gpu_probe_msch0;
pub use self::cci_probe_msch0 as perihp_probe_msch0;
pub use self::cci_probe_msch0 as perilp_probe_msch0;
pub use self::cci_probe_msch0 as video_probe_msch0;
pub use self::cci_probe_msch0 as vio0_probe_msch0;
pub use self::cci_probe_msch0 as vio1_probe_msch0;
pub use self::cci_probe_msch0 as cci_probe_msch1;
pub use self::cci_probe_msch0 as gpu_probe_msch1;
pub use self::cci_probe_msch0 as perihp_probe_msch1;
pub use self::cci_probe_msch0 as perilp_probe_msch1;
pub use self::cci_probe_msch0 as video_probe_msch1;
pub use self::cci_probe_msch0 as vio0_probe_msch1;
pub use self::cci_probe_msch0 as vio1_probe_msch1;
pub use self::ddr_pi0 as ddr_pi1;
pub use self::isp0_mmu0 as isp0_mmu1;
pub use self::isp0_mmu0 as isp1_mmu0;
pub use self::isp0_mmu0 as isp1_mmu1;
pub use self::isp0_mmu0 as vopl_mmu;
pub use self::isp0_mmu0 as vopb_mmu;
pub use self::isp0_mmu0 as iep_mmu;
pub use self::isp0_mmu0 as hdcp_mmu;
pub use self::timer0 as timer1;
pub use self::timer0 as timer2;
pub use self::timer0 as timer3;
pub use self::timer0 as timer4;
pub use self::timer0 as timer5;
pub use self::timer0 as timer6;
pub use self::timer0 as timer7;
pub use self::timer0 as timer8;
pub use self::timer0 as timer9;
pub use self::timer0 as timer10;
pub use self::timer0 as timer11;
pub use self::timer0 as stimer0;
pub use self::timer0 as stimer1;
pub use self::timer0 as stimer2;
pub use self::timer0 as stimer3;
pub use self::timer0 as stimer4;
pub use self::timer0 as stimer5;
pub use self::timer0 as stimer6;
pub use self::timer0 as stimer7;
pub use self::timer0 as stimer8;
pub use self::timer0 as stimer9;
pub use self::timer0 as stimer10;
pub use self::timer0 as stimer11;
pub use self::dmac0 as dmac1;
pub use self::mailbox0 as mailbox1;
pub use self::efuse0 as efuse1;
pub use self::wdt0 as wdt1;
pub use self::wdt0 as wdt2;
pub use self::usb3_otg0 as usb3_otg1;
pub use self::uart0 as uart1;
pub use self::uart0 as uart2;
pub use self::uart0 as uart3;
pub use self::uart0 as uart4;
pub use self::gpio0 as gpio1;
pub use self::gpio0 as gpio2;
pub use self::gpio0 as gpio3;
pub use self::gpio0 as gpio4;
pub use self::i2c0 as i2c1;
pub use self::i2c0 as i2c2;
pub use self::i2c0 as i2c3;
pub use self::i2c0 as i2c4;
pub use self::i2c0 as i2c5;
pub use self::i2c0 as i2c6;
pub use self::i2c0 as i2c7;
pub use self::i2c0 as i2c8;
pub use self::i2s0 as i2s1;
pub use self::i2s0 as i2s2;
pub use self::spi0 as spi1;
pub use self::spi0 as spi2;
pub use self::spi0 as spi3;
pub use self::spi0 as spi4;
pub use self::spi0 as spi5;
Modules§
- Cache Coherent Interconnect 500
- cci_m1 to memory schedule 0
- Clock and Reset Unit
- Controller Interface Control
- DDR Monitor
- DDR PHY Independent Register 0
- DDR CTL 0
- DDR CTL 1
- DDR PHY 0
- DDR PHY 1
- DMA Controller 0
- DisplayPort
- eFuse 0
- eMMC Controller
- Common register and bit access and modify traits
- Gigabit Media Access Controller
- General Purpose Input/Output 0
- General Register File
- HDMI
- Rockchip Inter-Integrated Circuit 0
- Inter-IC Sound 0
- ISP0 MMU0
- Mailbox 0
- Memory Schedule 0
- All masters access memory schedule0
- EP Address Translation Register (Inbound)
- Address Translation Register (Outbound)
- RP Address Translation Register (Inbound)
- PCIe Client
- DMA Configuration Register
- Local Management Register
- Physical Function Configuration Register
- Root Port Configuration Register
- Virtual Function Configuration Register
- Power Management Unit
- Power Management Unit Clock and Reset Unit
- Power Management Unit General Register File
- Pulse Width Modulation
- QOS Registers for CCI_M0
- QOS Registers for CCI_M1
- QOS Registers for CRYPTO0
- QOS Registers for CRYPTO1
- QOS Registers for DCF
- QOS Registers for DMAC0
- QOS Registers for DMAC1
- QOS Registers for EMMC
- QOS Registers for GIC
- QOS Registers for GMAC
- QOS Registers for GPU
- QOS Registers for HDCP
- QOS Registers for HSIC
- QOS Registers for IEP
- QOS Registers for ISP0_M0
- QOS Registers for ISP0_M1
- QOS Registers for ISP1_M0
- QOS Registers for ISP1_M1
- QOS Registers for PCIE
- QOS Registers for PERI_CM0
- QOS Registers for PERIHP_NSP
- QOS Registers for PERILP_NSP
- QOS Registers for PERILPSLV_NSP
- QOS Registers for PMU_CM0
- QOS Registers for RGA_R
- QOS Registers for RGA_W
- QOS Registers for SDIO
- QOS Registers for SDMMC
- QOS Registers for USB_HOST0
- QOS Registers for USB_HOST1
- QOS Registers for USB_OTG0
- QOS Registers for USB_OTG1
- QOS Registers for VIDEO_M0
- QOS Registers for VIDEO_M1_R
- QOS Registers for VIDEO_M1_W
- QOS Registers for VOP-BIG_R
- QOS Registers for VOP-BIG_W
- QOS Registers for VOP-LITTLE
- Successive Approximation Register Analog-to-Digital Converter
- Secure Digital MultiMedia Card
- All masters except pmu CM0 access all slaves pmu CM0 access all slaves outside pmu power domain
- Sony/Philips Digital Interface
- Serial Peripheral Interface 0
- Timer 0
- Temperature Sensor Analog-to-Digital Converter
- Universal Asynchronous Receiver/Transmitter 0
- USB 3.0/2.0 OTG Register 0
- Watchdog Timer 0
Structs§
- Cache Coherent Interconnect 500
- cci_m1 to memory schedule 0
- cci_m1 to memory schedule 1
- Clock and Reset Unit
- Controller Interface Control
- DDR Monitor
- DDR PHY Independent Register 0
- DDR PHY Independent Register 1
- DDR CTL 0
- DDR CTL 1
- DDR PHY 0
- DDR PHY 1
- DMA Controller 0
- DMA Controller 1
- DisplayPort
- eFuse 0
- eFuse 1
- eMMC Controller
- Gigabit Media Access Controller
- General Purpose Input/Output 0
- General Purpose Input/Output 1
- General Purpose Input/Output 2
- General Purpose Input/Output 3
- General Purpose Input/Output 4
- gpu to memory schedule 0
- gpu to memory schedule 1
- General Register File
- HDCP MMU
- HDMI
- Rockchip Inter-Integrated Circuit 0
- Rockchip Inter-Integrated Circuit 1
- Rockchip Inter-Integrated Circuit 2
- Rockchip Inter-Integrated Circuit 3
- Rockchip Inter-Integrated Circuit 4
- Rockchip Inter-Integrated Circuit 5
- Rockchip Inter-Integrated Circuit 6
- Rockchip Inter-Integrated Circuit 7
- Rockchip Inter-Integrated Circuit 8
- Inter-IC Sound 0
- Inter-IC Sound 1
- Inter-IC Sound 2
- IEP MMU
- ISP0 MMU0
- ISP0 MMU1
- ISP1 MMU0
- ISP1 MMU1
- Mailbox 0
- Mailbox 1
- Memory Schedule 0
- Memory Schedule 1
- All masters access memory schedule0
- All masters access memory schedule1
- EP Address Translation Register (Inbound)
- Address Translation Register (Outbound)
- RP Address Translation Register (Inbound)
- PCIe Client
- DMA Configuration Register
- Local Management Register
- Physical Function Configuration Register
- Root Port Configuration Register
- Virtual Function Configuration Register
- perihp master NIU to memory schedule 0
- perihp master NIU to memory schedule 1
- perilp master NIU,debug and cci_m0 to memory schedule 0
- perilp master NIU,debug and cci_m0 to memory schedule 1
- All the peripherals.
- Power Management Unit
- Power Management Unit Clock and Reset Unit
- Power Management Unit General Register File
- Pulse Width Modulation
- QOS Registers for CCI_M0
- QOS Registers for CCI_M1
- QOS Registers for CRYPTO0
- QOS Registers for CRYPTO1
- QOS Registers for DCF
- QOS Registers for DMAC0
- QOS Registers for DMAC1
- QOS Registers for EMMC
- QOS Registers for GIC
- QOS Registers for GMAC
- QOS Registers for GPU
- QOS Registers for HDCP
- QOS Registers for HSIC
- QOS Registers for IEP
- QOS Registers for ISP0_M0
- QOS Registers for ISP0_M1
- QOS Registers for ISP1_M0
- QOS Registers for ISP1_M1
- QOS Registers for PCIE
- QOS Registers for PERI_CM0
- QOS Registers for PERIHP_NSP
- QOS Registers for PERILP_NSP
- QOS Registers for PERILPSLV_NSP
- QOS Registers for PMU_CM0
- QOS Registers for RGA_R
- QOS Registers for RGA_W
- QOS Registers for SDIO
- QOS Registers for SDMMC
- QOS Registers for USB_HOST0
- QOS Registers for USB_HOST1
- QOS Registers for USB_OTG0
- QOS Registers for USB_OTG1
- QOS Registers for VIDEO_M0
- QOS Registers for VIDEO_M1_R
- QOS Registers for VIDEO_M1_W
- QOS Registers for VOP-BIG_R
- QOS Registers for VOP-BIG_W
- QOS Registers for VOP-LITTLE
- Successive Approximation Register Analog-to-Digital Converter
- Secure Digital MultiMedia Card
- All masters except pmu CM0 access all slaves pmu CM0 access all slaves outside pmu power domain
- pmu CM0 access all slaves inside pmu power domain
- Sony/Philips Digital Interface
- Serial Peripheral Interface 0
- Serial Peripheral Interface 1
- Serial Peripheral Interface 2
- Serial Peripheral Interface 3
- Serial Peripheral Interface 4
- Serial Peripheral Interface 5
- Secure Timer 0
- Secure Timer 1
- Secure Timer 2
- Secure Timer 3
- Secure Timer 4
- Secure Timer 5
- Secure Timer 6
- Secure Timer 7
- Secure Timer 8
- Secure Timer 9
- Secure Timer 10
- Secure Timer 11
- Timer 0
- Timer 1
- Timer 2
- Timer 3
- Timer 4
- Timer 5
- Timer 6
- Timer 7
- Timer 8
- Timer 9
- Timer 10
- Timer 11
- Temperature Sensor Analog-to-Digital Converter
- Universal Asynchronous Receiver/Transmitter 0
- Universal Asynchronous Receiver/Transmitter 1
- Universal Asynchronous Receiver/Transmitter 2
- Universal Asynchronous Receiver/Transmitter 3
- Universal Asynchronous Receiver/Transmitter 4
- USB 3.0/2.0 OTG Register 0
- USB 3.0/2.0 OTG Register 1
- video to memory schedule 0
- video to memory schedule 1
- iep,isp0 and vop-big to memory schedule 0
- iep,isp0 and vop-big to memory schedule 1
- rga,isp1,vop-little and hdcp to memory schedule 0
- rga,isp1,vop-little and hdcp to memory schedule 1
- VOPB MMU
- VOPL MMU
- Watchdog Timer 0
- Watchdog Timer 1
- Watchdog Timer 2
Constants§
- Number available in the NVIC for configuring priority