Module riscv::register::vexriscv

VexRiscv CSRs

VexRiscv is a RISC-V softcore written in Scala. It is highly configurable, and can be built with features such as a dcache and an external interrupt controller.

These features use vendor-specific CSRs, which are available using this module.

Modules

dci	vexriscv dci register -- dcache info
mim	vexriscv mim register -- machine irq mask
mip	vexriscv mip register -- machine irq pending
sim	vexriscv sim register -- supervisor irq mask
sip	vexriscv sip register -- supervisor irq pending