1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
//! Low level access to RISCV processors
//!
//! This crate provides:
//!
//! - Access to core registers like mstatus or mcause.
//! - Interrupt manipulation mechanisms.
//! - Safe wrappers around assembly instructions like `mret`.

#![no_std]
#![deny(warnings)]
#![feature(asm)]
#![feature(const_fn)]

extern crate bare_metal;

pub mod asm;
pub mod interrupt;
pub mod register;