Module riscv::csr [] [src]

Functions for accessing Control and Status Registers

Modules

cycle
cycleh
dcsr
dpc
dscratch
fcsr
fflags
frm
instret
instreth
marchid
mcause
mcounteren
mcycle
mcycleh
medeleg
mepc
mhartid
mideleg
mie
mimpid
minstret
minstreth
mip
misa
mscratch
mstatus
mtval
mtvec
mvendorid
pmpcfg0
pmpcfg1
pmpcfg2
pmpcfg3
satp
scause
scounteren
sedeleg
sepc
sideleg
sie
sip
sscratch
sstatus
stval
stvec
tdata1
tdata2
tdata3
time
timeh
tselect
ucause
uepc
uie
uip
uscratch
ustatus
utval
utvec

Structs

CYCLE
CYCLEH
DCSR
DPC
DSCRATCH
FCSR
FFLAGS
FRM
INSTRET
INSTRETH
MARCHID
MCAUSE
MCOUNTEREN
MCYCLE
MCYCLEH
MEDELEG
MEPC
MHARTID
MIDELEG
MIE
MIMPID
MINSTRET
MINSTRETH
MIP
MISA
MSCRATCH
MSTATUS
MTVAL
MTVEC
MVENDORID
PMPCFG0
PMPCFG1
PMPCFG2
PMPCFG3
SATP
SCAUSE
SCOUNTEREN
SEDELEG
SEPC
SIDELEG
SIE
SIP
SSCRATCH
SSTATUS
STVAL
STVEC
TDATA1
TDATA2
TDATA3
TIME
TIMEH
TSELECT
UCAUSE
UEPC
UIE
UIP
USCRATCH
USTATUS
UTVAL
UTVEC

Enums

Exception

Exception

Interrupt

Interrupt

MPP

Machine Status CSR is ReadWrite Machine Previous Privilege Mode

SPP

Supervisor Previous Privilege Mode

Trap

Machine Cause CSR (mcause) is ReadOnly. Trap Cause

Constants

cycle
cycleh
dcsr
dpc
dscratch
fcsr
fflags
frm
instret
instreth
marchid
mcause
mcounteren
mcycle
mcycleh
medeleg
mepc
mhartid
mideleg
mie
mimpid
minstret
minstreth
mip
misa
mscratch
mstatus
mtval
mtvec
mvendorid
pmpcfg0
pmpcfg1
pmpcfg2
pmpcfg3
satp
scause
scounteren
sedeleg
sepc
sideleg
sie
sip
sscratch
sstatus
stval
stvec
tdata1
tdata2
tdata3
time
timeh
tselect
ucause
uepc
uie
uip
uscratch
ustatus
utval
utvec