[][src]Struct riscv_sandbox::isa::Instruction

pub struct Instruction(pub u32);

Base structure of an instruction in the RV32I format (just an unsigned 32bits int)

For more information, see the RISC-V reference in the repository

Methods

impl Instruction[src]

pub fn create_r(
    opcode: OpCode,
    rd: u8,
    rs1: u8,
    rs2: u8,
    funct: u16
) -> Instruction
[src]

Creates a R type RV32I instruction. These are used for operations with only register operands (e.g. add r1 r1 r2).

Arguments

  • opcode - The opcode
  • rd - The destination register
  • rs1 - The first operand register
  • rs2 - The second operand register
  • funct - A 10bits number extending the opcode

pub fn create_i(
    opcode: OpCode,
    rd: u8,
    rs1: u8,
    imm: i32,
    funct: u8
) -> Instruction
[src]

Creates a I type RV32I instruction. These are used for operations with a register and an immediate (e.g. addi r1 r1 128).

Arguments

  • opcode - The opcode
  • rd - The destination register
  • rs1 - The register operand
  • imm - The immediate operand on 12bits
  • funct - The function to perform (extension of the opcode, on 3bits)

pub fn create_s(
    opcode: OpCode,
    rs1: u8,
    rs2: u8,
    imm: i32,
    funct: u8
) -> Instruction
[src]

Creates a S type RV32I instruction. These are used for operations with 2 register operands and an immediate, but no destination register (e.g. stw r1 r2 10).

Arguments

  • opcode - The opcode
  • rs1 - First register operand
  • rs2 - Second register operand
  • imm - Immediate operand on 12bits representing bits [11:0]
  • funct - A 3bits extension of the opcode

pub fn create_b(
    opcode: OpCode,
    rs1: u8,
    rs2: u8,
    imm: i32,
    funct: u8
) -> Instruction
[src]

Creates a B type RV32I instruction. These are S type instructions with a different immediate layout (the immediate on B represent bits [12:1])

pub fn create_u(opcode: OpCode, rd: u8, imm: i32) -> Instruction[src]

Creates a U type RV32I instruction. These are used for operations with only an immediate operand. As it carries fewer information than other instructions, U type instructions have more space for their immediate.

Arguments

  • opcode - The opcode
  • rd - The destination register of the operation
  • imm - bits [31:12] of the 32bits immediate value

pub fn create_j(opcode: OpCode, rd: u8, imm: i32) -> Instruction[src]

Creates a J type RV32I instruction. These are U type instructions with a different immediate layout (the immdiate on J represent bits [19:0])

pub fn lui(rd: u8, imm: i32) -> Instruction[src]

pub fn auipc(rd: u8, imm: i32) -> Instruction[src]

pub fn jal(rd: u8, imm: i32) -> Instruction[src]

pub fn jalr(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn beq(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn bne(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn blt(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn bge(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn bltu(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn bgeu(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn lb(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn lh(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn lw(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn lbu(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn lhu(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn sb(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn sh(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn sw(rs1: u8, rs2: u8, imm: i32) -> Instruction[src]

pub fn addi(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn slti(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn sltiu(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn xori(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn ori(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn andi(rd: u8, rs1: u8, imm: i32) -> Instruction[src]

pub fn slli(rd: u8, rs1: u8, shamt: i32) -> Instruction[src]

pub fn srli(rd: u8, rs1: u8, shamt: i32) -> Instruction[src]

pub fn srai(rd: u8, rs1: u8, shamt: i32) -> Instruction[src]

pub fn add(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn sub(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn sll(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn slt(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn sltu(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn xor(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn srl(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn sra(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn or(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn and(rd: u8, rs1: u8, rs2: u8) -> Instruction[src]

pub fn fence(pred: u8, succ: u8) -> Instruction[src]

pub fn fence1() -> Instruction[src]

pub fn nop() -> Instruction[src]

pub fn get_opcode(&self) -> u8[src]

pub fn set_opcode(&mut self, opcode: u8)[src]

pub fn get_rd(&self) -> u8[src]

pub fn set_rd(&mut self, rd: u8)[src]

pub fn get_rs1(&self) -> u8[src]

pub fn set_rs1(&mut self, rs1: u8)[src]

pub fn get_rs2(&self) -> u8[src]

pub fn set_rs2(&mut self, rs2: u8)[src]

pub fn get_funct3(&self) -> u8[src]

pub fn set_funct3(&mut self, funct3: u8)[src]

pub fn get_funct7(&self) -> u8[src]

pub fn set_funct7(&mut self, funct7: u8)[src]

pub fn get_funct10(&self) -> u16[src]

pub fn set_funct10(&mut self, funct10: u16)[src]

pub fn get_imm_i(&self) -> i32[src]

pub fn set_imm_i(&mut self, imm: i32)[src]

pub fn get_imm_s(&self) -> i32[src]

pub fn set_imm_s(&mut self, imm: i32)[src]

pub fn get_imm_u(&self) -> i32[src]

pub fn set_imm_u(&mut self, imm: i32)[src]

pub fn get_imm_b(&self) -> i32[src]

pub fn set_imm_b(&mut self, imm: i32)[src]

pub fn get_imm_j(&self) -> i32[src]

pub fn set_imm_j(&mut self, imm: i32)[src]

pub fn get_c_func3(&self) -> u8[src]

pub fn get_cmem_rs1(&self) -> u8[src]

pub fn get_cl_rd(&self) -> u8[src]

pub fn get_cmem_imm(&self) -> i32[src]

pub fn get_cs_rs2(&self) -> u8[src]

pub fn get_c_nzr(&self) -> u8[src]

pub fn get_c_nzimm(&self) -> i32[src]

pub fn get_cj_imm(&self) -> i32[src]

pub fn get_cb_imm(&self) -> i32[src]

pub fn get_clwsp_imm(&self) -> i32[src]

pub fn get_cswsp_imm(&self) -> i32[src]

pub fn get_type(&self) -> Type[src]

pub fn get_opcode_enum(&self) -> OpCode[src]

pub fn be(&self) -> u32[src]

pub fn le(&self) -> u32[src]

pub fn get_mnemonic(&self) -> &str[src]

This function is mainly used as a helper for the fmt::Display trait in order to pretty-print an instruction with println!()

pub fn is_compressed(&self) -> bool[src]

Tells if an instruction is a C instruction (compressed instruction from the C extension of RISC-V). A compressed instruction is 16bits wide.

pub fn uncompressed(&self) -> Instruction[src]

Translates a C instruction into a RV32 one, useful for machines that want to implement C extension by only implementing the RV32 base

pub fn display_values(&self, rs: &[i32]) -> String[src]

Display the values of registers instead of their name. It is useful for debugging, to know if a register has a bad value.

Trait Implementations

impl Clone for Instruction[src]

impl Copy for Instruction[src]

impl Display for Instruction[src]

impl Debug for Instruction[src]

Auto Trait Implementations

Blanket Implementations

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> From<T> for T[src]

impl<T> ToOwned for T where
    T: Clone
[src]

type Owned = T

The resulting type after obtaining ownership.

impl<T> ToString for T where
    T: Display + ?Sized
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> Any for T where
    T: 'static + ?Sized
[src]