[−][src]Enum riscv_asm::Instr

pub enum Instr {
    Illegal,
    Lb {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Lh {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Lw {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Ld {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Lbu {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Lhu {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Lwu {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Fence {
        rd: Reg,
        rs1: Reg,
        successor: u8,
        predecessor: u8,
        fm: u8,
    },
    FenceI {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Addi {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Slli {
        rd: Reg,
        rs1: Reg,
        imm5: u8,
    },
    Slti {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Sltiu {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Xori {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Srli {
        rd: Reg,
        rs1: Reg,
        imm5: u8,
    },
    Srai {
        rd: Reg,
        rs1: Reg,
        imm5: u8,
    },
    Ori {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Andi {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Auipc {
        rd: Reg,
        imm20: i32,
    },
    Sb {
        rs1: Reg,
        rs2: Reg,
        imm12: i32,
    },
    Sh {
        rs1: Reg,
        rs2: Reg,
        imm12: i32,
    },
    Sw {
        rs1: Reg,
        rs2: Reg,
        imm12: i32,
    },
    Sd {
        rs1: Reg,
        rs2: Reg,
        imm12: i32,
    },
    Add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sub {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sll {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slt {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sltu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srl {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sra {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Or {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    And {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Lui {
        rd: Reg,
        imm20: i32,
    },
    Beq {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bne {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Blt {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bge {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bltu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Bgeu {
        rs1: Reg,
        rs2: Reg,
        imm: i32,
    },
    Jalr {
        rd: Reg,
        rs1: Reg,
        imm12: i32,
    },
    Jal {
        rd: Reg,
        imm20: i32,
    },
    Ecall {
        rd: Reg,
        rs1: Reg,
    },
    Ebreak {
        rd: Reg,
        rs1: Reg,
    },
    Wfi {},
    Mret {},
    Csrrw {
        rs1: Reg,
        imm12: u32,
    },
    Csrrs {
        rd: Reg,
        rs1: Reg,
        imm12: u32,
    },
    Csrrc {
        rs1: Reg,
    },
    Csrrwi {
        rd: Reg,
    },
    Csrrsi {
        imm5: u8,
        imm12: u32,
    },
    Csrrci {
        imm5: u8,
        imm12: u32,
    },
    Hint {
        hint: (),
    },
}

Variants

Illegal

Lb

Fields of Lb

rd: Regrs1: Regimm12: i32

Lh

Fields of Lh

rd: Regrs1: Regimm12: i32

Lw

Fields of Lw

rd: Regrs1: Regimm12: i32

Ld

Fields of Ld

rd: Regrs1: Regimm12: i32

Lbu

Fields of Lbu

rd: Regrs1: Regimm12: i32

Lhu

Fields of Lhu

rd: Regrs1: Regimm12: i32

Lwu

Fields of Lwu

rd: Regrs1: Regimm12: i32

Fence

Fields of Fence

rd: Regrs1: Regsuccessor: u8

Successor Write/Read/Device Output/DeviceInput

4-bit value

predecessor: u8

Predecessor Write/Read/Device Output/DeviceInput

4-bit value

fm: u8

Fence Mode

4-bit value

FenceI

Fields of FenceI

rd: Regrs1: Regimm12: i32

Addi

Fields of Addi

rd: Regrs1: Regimm12: i32

Slli

Fields of Slli

rd: Regrs1: Regimm5: u8

Slti

Fields of Slti

rd: Regrs1: Regimm12: i32

Sltiu

Fields of Sltiu

rd: Regrs1: Regimm12: i32

Xori

Fields of Xori

rd: Regrs1: Regimm12: i32

Srli

Fields of Srli

rd: Regrs1: Regimm5: u8

Srai

Fields of Srai

rd: Regrs1: Regimm5: u8

Ori

Fields of Ori

rd: Regrs1: Regimm12: i32

Andi

Fields of Andi

rd: Regrs1: Regimm12: i32

Auipc

Fields of Auipc

rd: Regimm20: i32

Sb

Fields of Sb

rs1: Reg

Base address

rs2: Reg

Source register

imm12: i32

Offset

Sh

Fields of Sh

rs1: Reg

Base address

rs2: Reg

Source register

imm12: i32

Offset

Sw

Fields of Sw

rs1: Reg

Base address

rs2: Reg

Source register

imm12: i32

Offset

Sd

Fields of Sd

rs1: Reg

Base address

rs2: Reg

Source register

imm12: i32

Offset

Add

Fields of Add

rd: Regrs1: Regrs2: Reg

Sub

Fields of Sub

rd: Regrs1: Regrs2: Reg

Sll

Fields of Sll

rd: Regrs1: Regrs2: Reg

Slt

Fields of Slt

rd: Regrs1: Regrs2: Reg

Sltu

Fields of Sltu

rd: Regrs1: Regrs2: Reg

Xor

Fields of Xor

rd: Regrs1: Regrs2: Reg

Srl

Fields of Srl

rd: Regrs1: Regrs2: Reg

Sra

Fields of Sra

rd: Regrs1: Regrs2: Reg

Or

Fields of Or

rd: Regrs1: Regrs2: Reg

And

Fields of And

rd: Regrs1: Regrs2: Reg

Lui

Fields of Lui

rd: Regimm20: i32

Beq

Fields of Beq

rs1: Regrs2: Regimm: i32

Bne

Fields of Bne

rs1: Regrs2: Regimm: i32

Blt

Fields of Blt

rs1: Regrs2: Regimm: i32

Bge

Fields of Bge

rs1: Regrs2: Regimm: i32

Bltu

Fields of Bltu

rs1: Regrs2: Regimm: i32

Bgeu

Fields of Bgeu

rs1: Regrs2: Regimm: i32

Jalr

Jumps to a target address and saves the return address

The target address is obtained by adding the sign-extended imm12 to the register rs1 then setting the LSB to 0. The instruction following the jump (pc + 4) is written to register rd The standard software calling convention uses x1 as the return address register and x5 as an alternative link register.

Fields of Jalr

rd: Regrs1: Regimm12: i32

Encoded as a multiple of 2-bytes

Jal

Jumps to a relative address

imm20 is sign-extended and added to the address of the jump instruction to form the jump target address. The standard software calling convention uses x1 as the return address register and x5 as an alternative link register.

Fields of Jal

rd: Regimm20: i32

Encoded as a multiple of 2-bytes

Ecall

Make a service request to the execution environment

The EEI will define how parameters for the service request are passed, but usually these will be in define locations in the integer register file.

Fields of Ecall

rd: Regrs1: Reg

Ebreak

Return control to a debugging environment

Fields of Ebreak

rd: Regrs1: Reg

Wfi

Fields of Wfi

Mret

Fields of Mret

Csrrw

Fields of Csrrw

rs1: Regimm12: u32

Csrrs

Fields of Csrrs

rd: Regrs1: Regimm12: u32

Csrrc

Fields of Csrrc

rs1: Reg

Csrrwi

Fields of Csrrwi

rd: Reg

Csrrsi

Fields of Csrrsi

imm5: u8imm12: u32

Csrrci

Fields of Csrrci

imm5: u8imm12: u32

Hint

Fields of Hint

hint: ()

TODO: Encode hint instructions Most of them use rd == x0 as a reserved space

Trait Implementations

`impl Clone for Instr`[src]

`fn clone(&self) -> Instr`[src]

`fn clone_from(&mut self, source: &Self)`1.0.0[src]

`impl Copy for Instr`[src]

`impl Debug for Instr`[src]

`fn fmt(&self, f: &mut Formatter) -> Result`[src]

`impl Eq for Instr`[src]

`impl PartialEq<Instr> for Instr`[src]

`fn eq(&self, other: &Instr) -> bool`[src]

`fn ne(&self, other: &Instr) -> bool`[src]

`impl StructuralEq for Instr`[src]

`impl StructuralPartialEq for Instr`[src]

Auto Trait Implementations

`impl RefUnwindSafe for Instr`

`impl Send for Instr`

`impl Sync for Instr`

`impl Unpin for Instr`

`impl UnwindSafe for Instr`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> ToOwned for T where T: Clone,` [src]

`type Owned = T`

The resulting type after obtaining ownership.

`fn to_owned(&self) -> T`[src]

`fn clone_into(&self, target: &mut T)`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Enum riscv_asm::Instr

Variants

Fields of Lb

Fields of Lh

Fields of Lw

Fields of Ld

Fields of Lbu

Fields of Lhu

Fields of Lwu

Fields of Fence

Fields of FenceI

Fields of Addi

Fields of Slli

Fields of Slti

Fields of Sltiu

Fields of Xori

Fields of Srli

Fields of Srai

Fields of Ori

Fields of Andi

Fields of Auipc

Fields of Sb

Fields of Sh

Fields of Sw

Fields of Sd

Fields of Add

Fields of Sub

Fields of Sll

Fields of Slt

Fields of Sltu

Fields of Xor

Fields of Srl

Fields of Sra

Fields of Or

Fields of And

Fields of Lui

Fields of Beq

Fields of Bne

Fields of Blt

Fields of Bge

Fields of Bltu

Fields of Bgeu

Fields of Jalr

Fields of Jal

Fields of Ecall

Fields of Ebreak

Fields of Wfi

Fields of Mret

Fields of Csrrw

Fields of Csrrs

Fields of Csrrc

Fields of Csrrwi

Fields of Csrrsi

Fields of Csrrci

Fields of Hint

Trait Implementations

impl Clone for Instr[src]

fn clone(&self) -> Instr[src]

fn clone_from(&mut self, source: &Self)1.0.0[src]

impl Copy for Instr[src]

impl Debug for Instr[src]

fn fmt(&self, f: &mut Formatter) -> Result[src]

impl Eq for Instr[src]

impl PartialEq<Instr> for Instr[src]

fn eq(&self, other: &Instr) -> bool[src]

fn ne(&self, other: &Instr) -> bool[src]

impl StructuralEq for Instr[src]

impl StructuralPartialEq for Instr[src]

Auto Trait Implementations

impl RefUnwindSafe for Instr

impl Send for Instr

impl Sync for Instr

impl Unpin for Instr

impl UnwindSafe for Instr

Blanket Implementations

impl<T> Any for T where T: 'static + ?Sized, [src]

fn type_id(&self) -> TypeId[src]

impl<T> Borrow<T> for T where T: ?Sized, [src]

fn borrow(&self) -> &T[src]

impl<T> BorrowMut<T> for T where T: ?Sized, [src]

`impl Clone for Instr`[src]

`fn clone(&self) -> Instr`[src]

`fn clone_from(&mut self, source: &Self)`1.0.0[src]

`impl Copy for Instr`[src]

`impl Debug for Instr`[src]

`fn fmt(&self, f: &mut Formatter) -> Result`[src]

`impl Eq for Instr`[src]

`impl PartialEq<Instr> for Instr`[src]

`fn eq(&self, other: &Instr) -> bool`[src]

`fn ne(&self, other: &Instr) -> bool`[src]

`impl StructuralEq for Instr`[src]

`impl StructuralPartialEq for Instr`[src]

`impl RefUnwindSafe for Instr`

`impl Send for Instr`

`impl Sync for Instr`

`impl Unpin for Instr`

`impl UnwindSafe for Instr`

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into<U> for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> ToOwned for T where T: Clone,` [src]

`type Owned = T`

`fn to_owned(&self) -> T`[src]

`fn clone_into(&self, target: &mut T)`[src]

`impl<T, U> TryFrom<U> for T where U: Into<T>,` [src]

`type Error = Infallible`

`fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>`[src]

`impl<T, U> TryInto<U> for T where U: TryFrom<T>,` [src]

`type Error = <U as TryFrom<T>>::Error`

`fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>`[src]