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fsitok
iron-shapes-0.0.7
Basic data types and routines for computational geometry focused on VLSI chip design.
0
libreda-splay-0.1.0
Splay map and splay set data structures.
0
iron-shapes-booleanop-0.0.2
Boolean operations on polygons for iron-shapes.
0
libreda-oasis-0.0.3
OASIS input/output for libreda-db.
0
libreda-structural-verilog-0.0.3
Parser for structural verilog as it is created by Yosys.
0
liberty-io-0.0.2
Parser and writer for the Liberty format.
0
libreda-db-0.0.9
Layout and netlist datastructures for chip design.
0
libreda-lefdef-0.0.2
LEF/DEF input/output for libreda-db.
0
libreda-pnr-0.0.0
Algorithm interface definitions of the LibrEDA place-and-route framework.
0
steiner-tree-0.0.1
Fast construction of rectilinear steiner minimal trees (RSMT) in two dimensions.
0