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#![no_std]
extern crate embedded_hal as hal;
extern crate radio;
use radio::Registers;
use hal::blocking::{spi, delay};
use hal::digital::{OutputPin};
use hal::spi::{Mode, Phase, Polarity};
pub mod device;
pub use device::{TrxCmd, TrxStatus, CCAMode, defaults};
pub mod regs;
pub use regs::{Register};
#[derive(Copy, Clone, Debug)]
pub enum At86rf212Error<SPIError> {
SPI(SPIError),
InvalidPart(u8),
InvalidLength(usize),
MaxRetries,
PLLLock,
DigitalVoltage,
AnalogueVoltage,
}
impl <SPIError>From<SPIError> for At86rf212Error<SPIError> {
fn from(e: SPIError) -> At86rf212Error<SPIError> {
At86rf212Error::SPI(e)
}
}
pub const MODE: Mode = Mode {
polarity: Polarity::IdleLow,
phase: Phase::CaptureOnFirstTransition,
};
pub struct At86Rf212<SPI, OUTPUT, DELAY> {
spi: SPI,
reset: OUTPUT,
cs: OUTPUT,
sleep: OUTPUT,
delay: DELAY,
auto_crc: bool,
}
impl<E, SPI, OUTPUT, DELAY> At86Rf212<SPI, OUTPUT, DELAY>
where
SPI: spi::Transfer<u8, Error = E> + spi::Write<u8, Error = E>,
OUTPUT: OutputPin,
DELAY: delay::DelayMs<u32>,
{
pub fn new(spi: SPI, reset: OUTPUT, cs: OUTPUT, sleep: OUTPUT, delay: DELAY) -> Result<Self, At86rf212Error<E>> {
let mut at86rf212 = At86Rf212 { spi, reset, cs, sleep, delay, auto_crc: true };
at86rf212.sleep.set_low();
at86rf212.reset.set_low();
at86rf212.delay.delay_ms(10);
at86rf212.reset.set_high();
at86rf212.delay.delay_ms(20);
let who = at86rf212.reg_read(Register::PART_NUM)?;
if who != 0x07 {
return Err(At86rf212Error::InvalidPart(who));
}
at86rf212.set_state(TrxCmd::TRX_OFF)?;
let v = at86rf212.reg_read(Register::VREG_CTRL)?;
if v & regs::VREG_CTRL_DVDD_OK_MASK == 0 {
return Err(At86rf212Error::DigitalVoltage);
}
at86rf212.set_channel(defaults::CHANNEL)?;
at86rf212.set_cca_mode(defaults::CCA_MODE)?;
at86rf212.reg_write(Register::CSMA_BE, (defaults::MINBE << regs::CSMA_BE_MIN_SHIFT) | ((defaults::MAXBE as u8) << regs::CSMA_BE_MAX_SHIFT))?;
at86rf212.reg_update(Register::XAH_CTRL_0, regs::XAH_CTRL_MAX_CSMA_RETRIES_MASK, defaults::MAX_CSMA_BACKOFFS << regs::XAH_CTRL_MAX_CSMA_RETRIES_SHIFT)?;
at86rf212.reg_update(Register::XAH_CTRL_1, regs::XAH_CTRL_1_AACK_PROM_MODE_MASK, 1 << regs::XAH_CTRL_1_AACK_PROM_MODE_SHIFT)?;
at86rf212.reg_update(Register::TRX_CTRL_1, regs::TRX_CTRL1_TX_AUTO_CRC_ON_MASK, 1 << regs::TRX_CTRL1_TX_AUTO_CRC_ON_SHIFT)?;
at86rf212.reg_update(Register::TRX_CTRL_1, regs::TRX_CTRL1_IRQ_MASK_MODE_MASK, 1 << regs::TRX_CTRL1_IRQ_MASK_MODE_SHIFT)?;
at86rf212.reg_update(Register::TRX_CTRL_2, regs::TRX_CTRL2_RX_SAFE_MODE_MASK, 1 << regs::TRX_CTRL2_RX_SAFE_MODE_SHIFT)?;
Ok(at86rf212)
}
pub fn read_frame<'a>(&mut self, data: &'a mut [u8]) -> Result<&'a [u8], At86rf212Error<E>> {
let cmd: [u8; 1] = [device::FRAME_READ_FLAG as u8];
self.cs.set_low();
match self.spi.write(&cmd) {
Ok(_r) => (),
Err(e) => {
self.cs.set_high();
return Err(At86rf212Error::SPI(e));
}
};
let res = match self.spi.transfer(data) {
Ok(r) => r,
Err(e) => {
self.cs.set_high();
return Err(At86rf212Error::SPI(e));
}
};
self.cs.set_high();
Ok(res)
}
pub fn write_frame(&mut self, data: &[u8]) -> Result<(), At86rf212Error<E>> {
let mut cmd: [u8; 2] = [device::FRAME_WRITE_FLAG as u8, 0];
if self.auto_crc {
cmd[1] = (data.len() + device::LEN_FIELD_LEN + device::CRC_LEN) as u8;
} else {
cmd[1] = (data.len() + device::LEN_FIELD_LEN) as u8;
}
self.cs.set_low();
match self.spi.write(&cmd) {
Ok(_r) => (),
Err(e) => {
self.cs.set_high();
return Err(At86rf212Error::SPI(e));
}
};
match self.spi.write(&data) {
Ok(_r) => (),
Err(e) => {
self.cs.set_high();
return Err(At86rf212Error::SPI(e));
}
};
if self.auto_crc {
let crc = [0u8; device::CRC_LEN];
match self.spi.write(&crc) {
Ok(_r) => (),
Err(e) => {
self.cs.set_high();
return Err(At86rf212Error::SPI(e));
}
};
}
self.cs.set_high();
Ok(())
}
pub fn set_state(&mut self, state: device::TrxCmd) -> Result<(), At86rf212Error<E>> {
self.reg_update(Register::TRX_STATE, regs::TRX_STATE_TRX_CMD_MASK, state as u8)
}
pub fn set_state_blocking(&mut self, state: device::TrxCmd) -> Result<(), At86rf212Error<E>> {
self.reg_update(Register::TRX_STATE, regs::TRX_STATE_TRX_CMD_MASK, state as u8)?;
for _i in 0..defaults::MAX_SPI_RETRIES {
let v = self.reg_read(Register::TRX_STATE)?;
if (v & regs::TRX_STATUS_TRX_STATUS_MASK) != (TrxStatus::STATE_TRANSITION_IN_PROGRESS as u8) {
return Ok(());
}
self.delay.delay_ms(1);
}
Err(At86rf212Error::MaxRetries)
}
pub fn get_state(&mut self) -> Result<u8, At86rf212Error<E>> {
self.reg_read(Register::TRX_STATE).map(|v| v & regs::TRX_STATUS_TRX_STATUS_MASK)
}
pub fn set_channel(&mut self, channel: u8) -> Result<(), At86rf212Error<E>> {
self.reg_update(Register::PHY_CC_CCA, regs::PHY_CC_CCA_CHANNEL_MASK, channel << regs::PHY_CC_CCA_CHANNEL_SHIFT)
}
pub fn get_channel(&mut self) -> Result<u8, At86rf212Error<E>> {
self.reg_read(Register::PHY_CC_CCA).map(|v| (v & regs::PHY_CC_CCA_CHANNEL_MASK) >> regs::PHY_CC_CCA_CHANNEL_SHIFT)
}
pub fn set_irq_mask(&mut self, mask: u8) -> Result<(), At86rf212Error<E>> {
self.reg_write(Register::IRQ_MASK, mask)
}
pub fn get_irq_status(&mut self) -> Result<u8, At86rf212Error<E>> {
self.reg_read(Register::IRQ_STATUS)
}
pub fn set_cca_mode(&mut self, mode: CCAMode) -> Result<(), At86rf212Error<E>> {
self.reg_update(Register::PHY_CC_CCA, regs::PHY_CC_CCA_CCA_MODE_MASK, (mode as u8) << regs::PHY_CC_CCA_CCA_MODE_SHIFT)
}
pub fn get_cca_mode(&mut self) -> Result<u8, At86rf212Error<E>> {
self.reg_read(Register::PHY_CC_CCA).map(|v| (v & regs::PHY_CC_CCA_CCA_MODE_MASK) >> regs::PHY_CC_CCA_CCA_MODE_SHIFT)
}
pub fn set_short_address(&mut self, address: u16) -> Result<(), At86rf212Error<E>> {
self.reg_write(Register::SHORT_ADDR_0, (address & 0xFF) as u8)?;
self.reg_write(Register::SHORT_ADDR_1, (address >> 8) as u8)?;
Ok(())
}
pub fn set_pan_id(&mut self, pan_id: u16) -> Result<(), At86rf212Error<E>> {
self.reg_write(Register::PAN_ID_0, (pan_id & 0xFF) as u8)?;
self.reg_write(Register::PAN_ID_1, (pan_id >> 8) as u8)?;
Ok(())
}
pub fn set_power_raw(&mut self, power: u8) -> Result<(), At86rf212Error<E>> {
self.reg_update(Register::PHY_TX_PWR, regs::PHY_TX_PWR_TX_PWR_MASK, power << regs::PHY_TX_PWR_TX_PWR_SHIFT)?;
Ok(())
}
fn enable_pll(&mut self) -> Result<(), At86rf212Error<E>> {
self.set_state_blocking(TrxCmd::PLL_ON)?;
for _i in 0 .. defaults::MAX_SPI_RETRIES {
let v = self.get_irq_status()?;
if (v & regs::IRQ_STATUS_IRQ_0_PLL_LOCK_MASK) != 0 {
return Ok(())
}
}
Err(At86rf212Error::PLLLock)
}
fn check_tx_rx(&mut self) -> Result<bool, At86rf212Error<E>> {
let v = self.get_irq_status()?;
if (v & regs::IRQ_STATUS_IRQ_3_TRX_END_MASK) != 0 {
Ok(true)
} else {
Ok(false)
}
}
fn get_rx<'a>(&mut self, data: &'a mut [u8]) -> Result<&'a [u8], At86rf212Error<E>>{
let mut buf = [0u8; 1];
let len = self.read_frame(&mut buf)?[0] as usize;
if len > device::MAX_LENGTH {
return Err(At86rf212Error::InvalidLength(len));
}
if (len + device::LEN_FIELD_LEN + device::FRAME_RX_OVERHEAD) > data.len() {
return Err(At86rf212Error::InvalidLength(len));
}
self.read_frame(data)
}
}
impl<E, SPI, OUTPUT, DELAY> radio::Registers for At86Rf212<SPI, OUTPUT, DELAY>
where
SPI: spi::Transfer<u8, Error = E> + spi::Write<u8, Error = E>,
OUTPUT: OutputPin,
DELAY: delay::DelayMs<u32>,
{
type Error = At86rf212Error<E>;
type Register = Register;
fn reg_read<'a>(&mut self, reg: Self::Register) -> Result<u8, Self::Error>{
let mut buf: [u8; 2] = [device::REG_READ_FLAG as u8 | reg as u8, 0];
self.cs.set_low();
let res = self.spi.transfer(&mut buf);
self.cs.set_high();
match res {
Ok(v) => Ok(v[1]),
Err(e) => Err(At86rf212Error::SPI(e)),
}
}
fn reg_write(&mut self, reg: Self::Register, value: u8) -> Result<(), Self::Error>{
let buf: [u8; 2] = [device::REG_WRITE_FLAG as u8 | reg as u8, value];
self.cs.set_low();
let res = self.spi.write(&buf);
self.cs.set_high();
match res {
Ok(_) => Ok(()),
Err(e) => Err(At86rf212Error::SPI(e)),
}
}
fn reg_update(&mut self, reg: Self::Register, mask: u8, value: u8) -> Result<(), Self::Error>{
let mut data = self.reg_read(reg.clone())?;
data &= !mask;
data |= mask & value;
self.reg_write(reg, data)?;
Ok(())
}
}
impl<E, SPI, OUTPUT, DELAY> radio::Transmit for At86Rf212<SPI, OUTPUT, DELAY>
where
SPI: spi::Transfer<u8, Error = E> + spi::Write<u8, Error = E>,
OUTPUT: OutputPin,
DELAY: delay::DelayMs<u32>,
{
type Error = At86rf212Error<E>;
fn start_transmit(&mut self, channel: u16, data: &[u8]) -> Result<(), Self::Error>{
self.set_state_blocking(TrxCmd::TRX_OFF)?;
self.get_irq_status()?;
self.set_channel(channel as u8)?;
self.enable_pll()?;
self.write_frame(data)?;
self.set_state_blocking(TrxCmd::TX_START)?;
Ok(())
}
fn check_transmit(&mut self) -> Result<bool, Self::Error>{
self.check_tx_rx()
}
}
impl<E, SPI, OUTPUT, DELAY> radio::Receive for At86Rf212<SPI, OUTPUT, DELAY>
where
SPI: spi::Transfer<u8, Error = E> + spi::Write<u8, Error = E>,
OUTPUT: OutputPin,
DELAY: delay::DelayMs<u32>,
{
type Error = At86rf212Error<E>;
type Info = ();
fn start_receive(&mut self, channel: u16) -> Result<(), Self::Error> {
self.set_state_blocking(TrxCmd::TRX_OFF)?;
self.set_channel(channel as u8)?;
self.get_irq_status()?;
self.enable_pll()?;
self.set_state_blocking(TrxCmd::RX_ON)?;
Ok(())
}
fn get_received<'a>(&mut self, buff: &'a mut [u8]) -> Result<Option<(&'a[u8], Self::Info)>, Self::Error> {
if !self.check_tx_rx()? {
return Ok(None);
}
let data = self.get_rx(buff)?;
Ok(Some((data, ())))
}
}