Expand description
ARM 32-bit Olympus Microcontroller based device, CPU clock up to 480MHz, etc.
Re-exports§
Modules§
- acmphs0
- adc120
- adc121
- agt0
- bus
- cac
- canfd0
- ceu
- common
- cpscu
- cpu_dbg
- cpu_ocd
- crc
- dac12
- dma
- dmac0
- doc
- dphycnt
- drw
- dsilink
- dtc
- eccmb0
- edmac0
- elc
- etherc0
- faci
- fcache
- flad
- glcdc
- gpt320
- gpt_ops
- i3c
- icu
- icu_
common - iic0
- iic0wu
- iic1
- interrupt_
handlers - iwdt
- mstp
- pfs
- poeg
- port0
- port1
- pscu
- rmpu
- rtc
- sci0
- sdhi0
- spi0
- sram
- ssie0
- sysc
- tsd
- tsn
- tzf
- ulpt0
- usbfs
- usbhs
- wdt
- xspi
Structs§
- Acmphs0
- Adc120
- Adc121
- Agt0
- Bus
- CBP
- Cache and branch predictor maintenance operations
- CPUID
- CPUID
- Cac
- Canfd0
- Ceu
- Core
Peripherals - Core peripherals
- Cpscu
- CpuDbg
- CpuOcd
- Crc
- DCB
- Debug Control Block
- DWT
- Data Watchpoint and Trace unit
- Dac12
- Dma
- Dmac0
- Doc
- Dphycnt
- Drw
- Dsilink
- Dtc
- Eccmb0
- Edmac0
- Elc
- Etherc0
- FPB
- Flash Patch and Breakpoint unit
- FPU
- Floating Point Unit
- Faci
- Fcache
- Flad
- Glcdc
- Gpt320
- GptOps
- I3C
- ITM
- Instrumentation Trace Macrocell
- Icu
- IcuCommon
- Iic0
- Iic0Wu
- Iic1
- Iwdt
- MPU
- Memory Protection Unit
- Mstp
- NVIC
- Nested Vector Interrupt Controller
- Peripherals
- Required for compatibility with RTIC and other frameworks
- Pfs
- Poeg
- Port0
- Port1
- Pscu
- Rmpu
- Rtc
- SCB
- System Control Block
- SYST
- SysTick: System Timer
- Sci0
- Sdhi0
- Spi0
- Sram
- Ssie0
- Sysc
- TPIU
- Trace Port Interface Unit
- Tsd
- Tsn
- Tzf
- Ulpt0
- Usbfs
- Usbhs
- Wdt
- XSpi
Enums§
- Interrupt
- Enumeration of all the interrupts.
Constants§
- ACMPHS0
- ACMPH
S0_ NS - ACMPHS1
- ACMPH
S1_ NS - ADC120
- ADC121
- ADC120_
NS - ADC121_
NS - AGT0
- AGT0_NS
- AGT1
- AGT1_NS
- BUS
- BUS_NS
- CAC
- CAC_NS
- CANFD0
- CANF
D0_ NS - CANFD1
- CANF
D1_ NS - CEU
- CEU_NS
- CPSCU
- CPSCU_
NS - CPU_DBG
- CPU_
DBG_ NS - CPU_OCD
- CPU_
OCD_ NS - CRC
- CRC_NS
- DAC12
- DAC12_
NS - DMA
- DMAC0
- DMAC0_
NS - DMAC1
- DMAC2
- DMAC3
- DMAC4
- DMAC5
- DMAC6
- DMAC7
- DMAC1_
NS - DMAC2_
NS - DMAC3_
NS - DMAC4_
NS - DMAC5_
NS - DMAC6_
NS - DMAC7_
NS - DMA_NS
- DOC
- DOC_NS
- DPHYCNT
- DPHYCNT_
NS - DRW
- DRW_NS
- DSILINK
- DSILINK_
NS - DTC
- DTC_NS
- ECCMB0
- ECCM
B0_ NS - ECCMB1
- ECCM
B1_ NS - EDMAC0
- EDMA
C0_ NS - ELC
- ELC_NS
- ETHERC0
- ETHER
C0_ NS - FACI
- FACI_NS
- FCACHE
- FCACHE_
NS - FLAD
- FLAD_NS
- GLCDC
- GLCDC_
NS - GPT168
- GPT169
- GPT320
- GPT321
- GPT322
- GPT323
- GPT324
- GPT325
- GPT326
- GPT327
- GPT168_
NS - GPT169_
NS - GPT320_
NS - GPT321_
NS - GPT322_
NS - GPT323_
NS - GPT324_
NS - GPT325_
NS - GPT326_
NS - GPT327_
NS - GPT1610
- GPT1611
- GPT1612
- GPT1613
- GPT1610_
NS - GPT1611_
NS - GPT1612_
NS - GPT1613_
NS - GPT_OPS
- GPT_
OPS_ NS - I3C
- I3C_NS
- ICU
- ICU_
COMMON - ICU_
COMMON_ NS - ICU_NS
- IIC0
- IIC0WU
- IIC0WU_
NS - IIC0_NS
- IIC1
- IIC1_NS
- IWDT
- IWDT_NS
- MSTP
- MSTP_NS
- NVIC_
PRIO_ BITS - Number available in the NVIC for configuring priority
- PFS
- PFS_NS
- POEG
- POEG_NS
- PORT0
- PORT0_
NS - PORT1
- PORT2
- PORT3
- PORT4
- PORT5
- PORT6
- PORT7
- PORT8
- PORT9
- PORT1_
NS - PORT2_
NS - PORT3_
NS - PORT4_
NS - PORT5_
NS - PORT6_
NS - PORT7_
NS - PORT8_
NS - PORT9_
NS - PORTA
- PORTA_
NS - PORTB
- PORTB_
NS - PORTC
- PORTC_
NS - PORTD
- PORTD_
NS - PORTE
- PORTE_
NS - PORTF
- PORTF_
NS - PORTG
- PORTG_
NS - PSCU
- PSCU_NS
- RMPU
- RMPU_NS
- RTC
- RTC_NS
- SCI0
- SCI0_NS
- SCI1
- SCI2
- SCI3
- SCI4
- SCI9
- SCI1_NS
- SCI2_NS
- SCI3_NS
- SCI4_NS
- SCI9_NS
- SDHI0
- SDHI0_
NS - SDHI1
- SDHI1_
NS - SPI0
- SPI0_NS
- SPI1
- SPI1_NS
- SRAM
- SRAM_NS
- SSIE0
- SSIE0_
NS - SSIE1
- SSIE1_
NS - SYSC
- SYSC_NS
- TSD
- TSD_NS
- TSN
- TSN_NS
- TZF
- TZF_NS
- ULPT0
- ULPT0_
NS - ULPT1
- ULPT1_
NS - USBFS
- USBFS_
NS - USBHS
- USBHS_
NS - WDT
- WDT_NS
- XSPI
- XSPI_NS