Expand description
Peripheral access API for R7FA6T2BD microcontrollers (generated using svd2rust v0.28.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports
pub use self::dmac0 as dmac1;pub use self::dmac0 as dmac2;pub use self::dmac0 as dmac3;pub use self::dmac0 as dmac4;pub use self::dmac0 as dmac5;pub use self::dmac0 as dmac6;pub use self::dmac0 as dmac7;pub use self::agtw_b0 as agtw_b1;pub use self::acmphs0 as acmphs1;pub use self::acmphs0 as acmphs2;pub use self::acmphs0 as acmphs3;pub use self::sci_b0 as sci_b1;pub use self::sci_b0 as sci_b2;pub use self::sci_b0 as sci_b3;pub use self::sci_b0 as sci_b4;pub use self::sci_b0 as sci_b9;pub use self::spi_b0 as spi_b1;pub use self::iic_b0 as iic_b1;pub use self::gpt320 as gpt321;pub use self::gpt320 as gpt322;pub use self::gpt320 as gpt323;pub use self::gpt324 as gpt325;pub use self::gpt324 as gpt326;pub use self::gpt324 as gpt327;pub use self::gpt324 as gpt328;pub use self::gpt324 as gpt329;pub use self::dac120 as dac121;Modules
High-Speed Analog Comparator 0
12-bit A/D Converter
Low Power Asynchronous General Purpose Timer 0
BUS Control
Clock Frequency Accuracy Measurement Circuit
CACHE
CANFD Module Control
CPU System Security Control Unit
Cyclic Redundancy Check
12-bit D/A converter 0
Debug Function
DMAC Module Activation
Direct memory access controller 0
Data Operation Circuit
Data Transfer Controller
CANFD ECC Module
Event Link Controller
Flash Application Command Interface
Flash Cache
Data Flash
Common register and bit access and modify traits
General PWM 32-bit Timer 0
General PWM 32-bit Timer 4
GTCLK
Output Phase Switching Controller
Interrupt Controller
Inter-Integrated Circuit 0 Wake-up Unit
Inter-Integrated Circuit 0
IIR filter accelerator
Independent Watchdog Timer
Key Interrupt Function
Module Stop Control
PWM Delay Generation Circuit
Pmn Pin Function Control Register
Port Output Enable for GPT
Port 0 Control Registers
Port 2 Control Registers
Port A Control Registers
Port B Control Registers
Port C Control Registers
Port D Control Registers
Port E Control Registers
Peripheral Security Control Unit
Renesas Memory Protection Unit
Serial Communication Interface 0
Serial Peripheral Interface 0
SRAM Control
System Control
Trigonometric Function Unit
Temperature Sensor Calibration Data
Temperature Sensor
TrustZone Filter
Watchdog Timer
Structs
High-Speed Analog Comparator 0
High-Speed Analog Comparator 1
High-Speed Analog Comparator 2
High-Speed Analog Comparator 3
12-bit A/D Converter
Low Power Asynchronous General Purpose Timer 0
Low Power Asynchronous General Purpose Timer 1
BUS Control
Clock Frequency Accuracy Measurement Circuit
CACHE
CANFD Module Control
Cache and branch predictor maintenance operations
CPU System Security Control Unit
CPUID
Cyclic Redundancy Check
Core peripherals
12-bit D/A converter 0
12-bit D/A converter 1
Debug Function
Debug Control Block
DMAC Module Activation
Direct memory access controller 0
Direct memory access controller 1
Direct memory access controller 2
Direct memory access controller 3
Direct memory access controller 4
Direct memory access controller 5
Direct memory access controller 6
Direct memory access controller 7
Data Operation Circuit
Data Transfer Controller
Data Watchpoint and Trace unit
CANFD ECC Module
Event Link Controller
Flash Application Command Interface
Flash Cache
Data Flash
Flash Patch and Breakpoint unit
Floating Point Unit
General PWM 32-bit Timer 0
General PWM 32-bit Timer 1
General PWM 32-bit Timer 2
General PWM 32-bit Timer 3
General PWM 32-bit Timer 4
General PWM 32-bit Timer 5
General PWM 32-bit Timer 6
General PWM 32-bit Timer 7
General PWM 32-bit Timer 8
General PWM 32-bit Timer 9
GTCLK
Output Phase Switching Controller
Interrupt Controller
Inter-Integrated Circuit 0 Wake-up Unit
Inter-Integrated Circuit 0
Inter-Integrated Circuit 1
IIR filter accelerator
Instrumentation Trace Macrocell
Independent Watchdog Timer
Key Interrupt Function
Memory Protection Unit
Module Stop Control
Nested Vector Interrupt Controller
PWM Delay Generation Circuit
Pmn Pin Function Control Register
Port Output Enable for GPT
Port 0 Control Registers
Port 2 Control Registers
Port A Control Registers
Port B Control Registers
Port C Control Registers
Port D Control Registers
Port E Control Registers
Peripheral Security Control Unit
All the peripherals.
Renesas Memory Protection Unit
System Control Block
Serial Communication Interface 0
Serial Communication Interface 1
Serial Communication Interface 2
Serial Communication Interface 3
Serial Communication Interface 4
Serial Communication Interface 9
Serial Peripheral Interface 0
Serial Peripheral Interface 1
SRAM Control
System Control
SysTick: System Timer
Trigonometric Function Unit
Trace Port Interface Unit
Temperature Sensor Calibration Data
Temperature Sensor
TrustZone Filter
Watchdog Timer
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority