Crate ra4m1_pac

Crate ra4m1_pac 

Source
Expand description

ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 48MHz, etc.

Re-exports§

pub use self::Interrupt as interrupt;
pub use common::*;

Modules§

acmplp
adc140
agt0
bus
cac
can0
common
crc
ctsu
dac8
dac12
dbg
dma
dmac0
doc
dtc
elc
fcache
gpt162
gpt320
gpt_ops
icu
iic0
iic1
interrupt_handlers
iwdt
kint
mmpu
mstp
opamp
pfs
pmisc
poeg
port0
port1
rtc
sci0
sci2
slcdc
smpu
spi0
spi1
spmon
sram
ssie0
system
tsn
usbfs
wdt

Structs§

Acmplp
Adc140
Agt0
Bus
CBP
Cache and branch predictor maintenance operations
CPUID
CPUID
Cac
Can0
CorePeripherals
Core peripherals
Crc
Ctsu
DCB
Debug Control Block
DWT
Data Watchpoint and Trace unit
Dac8
Dac12
Dbg
Dma
Dmac0
Doc
Dtc
Elc
FPB
Flash Patch and Breakpoint unit
FPU
Floating Point Unit
Fcache
Gpt162
Gpt320
GptOps
ITM
Instrumentation Trace Macrocell
Icu
Iic0
Iic1
Iwdt
Kint
MPU
Memory Protection Unit
Mmpu
Mstp
NVIC
Nested Vector Interrupt Controller
Opamp
Peripherals
Required for compatibility with RTIC and other frameworks
Pfs
Pmisc
Poeg
Port0
Port1
Rtc
SCB
System Control Block
SYST
SysTick: System Timer
Sci0
Sci2
Slcdc
Smpu
Spi0
Spi1
Spmon
Sram
Ssie0
System
TPIU
Trace Port Interface Unit
Tsn
Usbfs
Wdt

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

ACMPLP
ADC140
AGT0
AGT1
BUS
CAC
CAN0
CRC
CTSU
DAC8
DAC12
DBG
DMA
DMAC0
DMAC1
DMAC2
DMAC3
DOC
DTC
ELC
FCACHE
GPT162
GPT163
GPT164
GPT165
GPT166
GPT167
GPT320
GPT321
GPT_OPS
ICU
IIC0
IIC1
IWDT
KINT
MMPU
MSTP
NVIC_PRIO_BITS
Number available in the NVIC for configuring priority
OPAMP
PFS
PMISC
POEG
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
RTC
SCI0
SCI1
SCI2
SCI9
SLCDC
SMPU
SPI0
SPI1
SPMON
SRAM
SSIE0
SYSTEM
TSN
USBFS
WDT

Attribute Macros§

interrupt