Crate ra0e1_pac

Crate ra0e1_pac 

Source
Expand description

Arm Cortex-M23 based Microcontroller RA0E1 device

Re-exports§

pub use self::Interrupt as interrupt;
pub use common::*;

Modules§

adc_d
bus
common
crc
dbg
dtc
elc
flcn
icu
iica
interrupt_handlers
iwdt
mstp
pclbuz
pfs_a
porga
port0
port1
port2
port3
port4
port9
rtc_c
sau0
sau1
sram
sysc
tau
tml32
trng
uarta

Structs§

AdcD
Bus
CBP
Cache and branch predictor maintenance operations
CPUID
CPUID
CorePeripherals
Core peripherals
Crc
DCB
Debug Control Block
DWT
Data Watchpoint and Trace unit
Dbg
Dtc
Elc
FPB
Flash Patch and Breakpoint unit
Flcn
ITM
Instrumentation Trace Macrocell
Icu
Iica
Iwdt
Mstp
NVIC
Nested Vector Interrupt Controller
Pclbuz
Peripherals
Required for compatibility with RTIC and other frameworks
PfsA
Porga
Port0
Port1
Port2
Port3
Port4
Port9
RtcC
SCB
System Control Block
SYST
SysTick: System Timer
Sau0
Sau1
Sram
Sysc
TPIU
Trace Port Interface Unit
Tau
Tml32
Trng
Uarta

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

ADC_D
BUS
CRC
DBG
DTC
ELC
FLCN
ICU
IICA
IWDT
MSTP
NVIC_PRIO_BITS
Number available in the NVIC for configuring priority
PCLBUZ
PFS_A
PORGA
PORT0
PORT1
PORT2
PORT3
PORT4
PORT9
RTC_C
SAU0
SAU1
SRAM
SYSC
TAU
TML32
TRNG
UARTA

Attribute Macros§

interrupt