List of all items

Structs

• AUDIOCODEC
• CCU
• CE_NS
• CIR_RX
• CIR_TX
• CSIC
• DMAC
• DMIC
• DSP_MSGBOX
• EMAC
• GPADC
• GPIO
• HSTIMER
• I2S_PCM0
• I2S_PCM1
• I2S_PCM2
• IOMMU
• LEDC
• LRADC
• OWA
• PLIC
• PWM
• Peripherals
• RTC
• RV_MSGBOX
• SMHC0
• SMHC1
• SMHC2
• SPI0
• SPINLOCK
• SPI_DBI
• SYS_CFG
• TCON_LCD0
• TCON_TV0
• THS
• TIMER
• TPADC
• TVD0
• TVD_TOP
• TVE
• TVE_TOP
• TWI0
• TWI1
• TWI2
• TWI3
• UART0
• UART1
• UART2
• UART3
• UART4
• UART5
• USB1
• audio_codec::RegisterBlock
• audio_codec::ac_adc_cnt::AC_ADC_CNT_SPEC
• audio_codec::ac_adc_cnt::R
• audio_codec::ac_adc_cnt::W
• audio_codec::ac_adc_dap_ctr::AC_ADC_DAP_CTR_SPEC
• audio_codec::ac_adc_dap_ctr::R
• audio_codec::ac_adc_dap_ctr::W
• audio_codec::ac_adc_dg::AC_ADC_DG_SPEC
• audio_codec::ac_adc_dg::R
• audio_codec::ac_adc_dg::W
• audio_codec::ac_adc_drc_ctrl::AC_ADC_DRC_CTRL_SPEC
• audio_codec::ac_adc_drc_ctrl::R
• audio_codec::ac_adc_drc_ctrl::W
• audio_codec::ac_adc_drc_epshc::AC_ADC_DRC_EPSHC_SPEC
• audio_codec::ac_adc_drc_epshc::R
• audio_codec::ac_adc_drc_epshc::W
• audio_codec::ac_adc_drc_epslc::AC_ADC_DRC_EPSLC_SPEC
• audio_codec::ac_adc_drc_epslc::R
• audio_codec::ac_adc_drc_epslc::W
• audio_codec::ac_adc_drc_hct::AC_ADC_DRC_HCT_SPEC
• audio_codec::ac_adc_drc_hct::R
• audio_codec::ac_adc_drc_hct::W
• audio_codec::ac_adc_drc_het::AC_ADC_DRC_HET_SPEC
• audio_codec::ac_adc_drc_het::R
• audio_codec::ac_adc_drc_het::W
• audio_codec::ac_adc_drc_hhpfc::AC_ADC_DRC_HHPFC_SPEC
• audio_codec::ac_adc_drc_hhpfc::R
• audio_codec::ac_adc_drc_hhpfc::W
• audio_codec::ac_adc_drc_hkc::AC_ADC_DRC_HKC_SPEC
• audio_codec::ac_adc_drc_hkc::R
• audio_codec::ac_adc_drc_hkc::W
• audio_codec::ac_adc_drc_hke::AC_ADC_DRC_HKE_SPEC
• audio_codec::ac_adc_drc_hke::R
• audio_codec::ac_adc_drc_hke::W
• audio_codec::ac_adc_drc_hkl::AC_ADC_DRC_HKL_SPEC
• audio_codec::ac_adc_drc_hkl::R
• audio_codec::ac_adc_drc_hkl::W
• audio_codec::ac_adc_drc_hkn::AC_ADC_DRC_HKN_SPEC
• audio_codec::ac_adc_drc_hkn::R
• audio_codec::ac_adc_drc_hkn::W
• audio_codec::ac_adc_drc_hlt::AC_ADC_DRC_HLT_SPEC
• audio_codec::ac_adc_drc_hlt::R
• audio_codec::ac_adc_drc_hlt::W
• audio_codec::ac_adc_drc_hopc::AC_ADC_DRC_HOPC_SPEC
• audio_codec::ac_adc_drc_hopc::R
• audio_codec::ac_adc_drc_hopc::W
• audio_codec::ac_adc_drc_hope::AC_ADC_DRC_HOPE_SPEC
• audio_codec::ac_adc_drc_hope::R
• audio_codec::ac_adc_drc_hope::W
• audio_codec::ac_adc_drc_hopl::AC_ADC_DRC_HOPL_SPEC
• audio_codec::ac_adc_drc_hopl::R
• audio_codec::ac_adc_drc_hopl::W
• audio_codec::ac_adc_drc_hpfhgain::AC_ADC_DRC_HPFHGAIN_SPEC
• audio_codec::ac_adc_drc_hpfhgain::R
• audio_codec::ac_adc_drc_hpfhgain::W
• audio_codec::ac_adc_drc_hpflgain::AC_ADC_DRC_HPFLGAIN_SPEC
• audio_codec::ac_adc_drc_hpflgain::R
• audio_codec::ac_adc_drc_hpflgain::W
• audio_codec::ac_adc_drc_lct::AC_ADC_DRC_LCT_SPEC
• audio_codec::ac_adc_drc_lct::R
• audio_codec::ac_adc_drc_lct::W
• audio_codec::ac_adc_drc_let::AC_ADC_DRC_LET_SPEC
• audio_codec::ac_adc_drc_let::R
• audio_codec::ac_adc_drc_let::W
• audio_codec::ac_adc_drc_lhpfc::AC_ADC_DRC_LHPFC_SPEC
• audio_codec::ac_adc_drc_lhpfc::R
• audio_codec::ac_adc_drc_lhpfc::W
• audio_codec::ac_adc_drc_lkc::AC_ADC_DRC_LKC_SPEC
• audio_codec::ac_adc_drc_lkc::R
• audio_codec::ac_adc_drc_lkc::W
• audio_codec::ac_adc_drc_lke::AC_ADC_DRC_LKE_SPEC
• audio_codec::ac_adc_drc_lke::R
• audio_codec::ac_adc_drc_lke::W
• audio_codec::ac_adc_drc_lkl::AC_ADC_DRC_LKL_SPEC
• audio_codec::ac_adc_drc_lkl::R
• audio_codec::ac_adc_drc_lkl::W
• audio_codec::ac_adc_drc_lkn::AC_ADC_DRC_LKN_SPEC
• audio_codec::ac_adc_drc_lkn::R
• audio_codec::ac_adc_drc_lkn::W
• audio_codec::ac_adc_drc_llt::AC_ADC_DRC_LLT_SPEC
• audio_codec::ac_adc_drc_llt::R
• audio_codec::ac_adc_drc_llt::W
• audio_codec::ac_adc_drc_lopc::AC_ADC_DRC_LOPC_SPEC
• audio_codec::ac_adc_drc_lopc::R
• audio_codec::ac_adc_drc_lopc::W
• audio_codec::ac_adc_drc_lope::AC_ADC_DRC_LOPE_SPEC
• audio_codec::ac_adc_drc_lope::R
• audio_codec::ac_adc_drc_lope::W
• audio_codec::ac_adc_drc_lopl::AC_ADC_DRC_LOPL_SPEC
• audio_codec::ac_adc_drc_lopl::R
• audio_codec::ac_adc_drc_lopl::W
• audio_codec::ac_adc_drc_lpfhat::AC_ADC_DRC_LPFHAT_SPEC
• audio_codec::ac_adc_drc_lpfhat::R
• audio_codec::ac_adc_drc_lpfhat::W
• audio_codec::ac_adc_drc_lpfhrt::AC_ADC_DRC_LPFHRT_SPEC
• audio_codec::ac_adc_drc_lpfhrt::R
• audio_codec::ac_adc_drc_lpfhrt::W
• audio_codec::ac_adc_drc_lpflat::AC_ADC_DRC_LPFLAT_SPEC
• audio_codec::ac_adc_drc_lpflat::R
• audio_codec::ac_adc_drc_lpflat::W
• audio_codec::ac_adc_drc_lpflrt::AC_ADC_DRC_LPFLRT_SPEC
• audio_codec::ac_adc_drc_lpflrt::R
• audio_codec::ac_adc_drc_lpflrt::W
• audio_codec::ac_adc_drc_lrmshat::AC_ADC_DRC_LRMSHAT_SPEC
• audio_codec::ac_adc_drc_lrmshat::R
• audio_codec::ac_adc_drc_lrmshat::W
• audio_codec::ac_adc_drc_lrmslat::AC_ADC_DRC_LRMSLAT_SPEC
• audio_codec::ac_adc_drc_lrmslat::R
• audio_codec::ac_adc_drc_lrmslat::W
• audio_codec::ac_adc_drc_mnghs::AC_ADC_DRC_MNGHS_SPEC
• audio_codec::ac_adc_drc_mnghs::R
• audio_codec::ac_adc_drc_mnghs::W
• audio_codec::ac_adc_drc_mngls::AC_ADC_DRC_MNGLS_SPEC
• audio_codec::ac_adc_drc_mngls::R
• audio_codec::ac_adc_drc_mngls::W
• audio_codec::ac_adc_drc_mxghs::AC_ADC_DRC_MXGHS_SPEC
• audio_codec::ac_adc_drc_mxghs::R
• audio_codec::ac_adc_drc_mxghs::W
• audio_codec::ac_adc_drc_mxgls::AC_ADC_DRC_MXGLS_SPEC
• audio_codec::ac_adc_drc_mxgls::R
• audio_codec::ac_adc_drc_mxgls::W
• audio_codec::ac_adc_drc_rpfhat::AC_ADC_DRC_RPFHAT_SPEC
• audio_codec::ac_adc_drc_rpfhat::R
• audio_codec::ac_adc_drc_rpfhat::W
• audio_codec::ac_adc_drc_rpfhrt::AC_ADC_DRC_RPFHRT_SPEC
• audio_codec::ac_adc_drc_rpfhrt::R
• audio_codec::ac_adc_drc_rpfhrt::W
• audio_codec::ac_adc_drc_rpflat::AC_ADC_DRC_RPFLAT_SPEC
• audio_codec::ac_adc_drc_rpflat::R
• audio_codec::ac_adc_drc_rpflat::W
• audio_codec::ac_adc_drc_rpflrt::AC_ADC_DRC_RPFLRT_SPEC
• audio_codec::ac_adc_drc_rpflrt::R
• audio_codec::ac_adc_drc_rpflrt::W
• audio_codec::ac_adc_drc_rrmshat::AC_ADC_DRC_RRMSHAT_SPEC
• audio_codec::ac_adc_drc_rrmshat::R
• audio_codec::ac_adc_drc_rrmshat::W
• audio_codec::ac_adc_drc_rrmslat::AC_ADC_DRC_RRMSLAT_SPEC
• audio_codec::ac_adc_drc_rrmslat::R
• audio_codec::ac_adc_drc_rrmslat::W
• audio_codec::ac_adc_drc_sfhat::AC_ADC_DRC_SFHAT_SPEC
• audio_codec::ac_adc_drc_sfhat::R
• audio_codec::ac_adc_drc_sfhat::W
• audio_codec::ac_adc_drc_sfhrt::AC_ADC_DRC_SFHRT_SPEC
• audio_codec::ac_adc_drc_sfhrt::R
• audio_codec::ac_adc_drc_sfhrt::W
• audio_codec::ac_adc_drc_sflat::AC_ADC_DRC_SFLAT_SPEC
• audio_codec::ac_adc_drc_sflat::R
• audio_codec::ac_adc_drc_sflat::W
• audio_codec::ac_adc_drc_sflrt::AC_ADC_DRC_SFLRT_SPEC
• audio_codec::ac_adc_drc_sflrt::R
• audio_codec::ac_adc_drc_sflrt::W
• audio_codec::ac_adc_fifoc::AC_ADC_FIFOC_SPEC
• audio_codec::ac_adc_fifoc::R
• audio_codec::ac_adc_fifoc::W
• audio_codec::ac_adc_fifos::AC_ADC_FIFOS_SPEC
• audio_codec::ac_adc_fifos::R
• audio_codec::ac_adc_fifos::W
• audio_codec::ac_adc_rxdata::AC_ADC_RXDATA_SPEC
• audio_codec::ac_adc_rxdata::R
• audio_codec::ac_adc_rxdata::W
• audio_codec::ac_dac_cnt::AC_DAC_CNT_SPEC
• audio_codec::ac_dac_cnt::R
• audio_codec::ac_dac_cnt::W
• audio_codec::ac_dac_dap_ctrl::AC_DAC_DAP_CTRL_SPEC
• audio_codec::ac_dac_dap_ctrl::R
• audio_codec::ac_dac_dap_ctrl::W
• audio_codec::ac_dac_dg::AC_DAC_DG_SPEC
• audio_codec::ac_dac_dg::R
• audio_codec::ac_dac_dg::W
• audio_codec::ac_dac_dpc::AC_DAC_DPC_SPEC
• audio_codec::ac_dac_dpc::R
• audio_codec::ac_dac_dpc::W
• audio_codec::ac_dac_drc_ctrl::AC_DAC_DRC_CTRL_SPEC
• audio_codec::ac_dac_drc_ctrl::R
• audio_codec::ac_dac_drc_ctrl::W
• audio_codec::ac_dac_drc_epshc::AC_DAC_DRC_EPSHC_SPEC
• audio_codec::ac_dac_drc_epshc::R
• audio_codec::ac_dac_drc_epshc::W
• audio_codec::ac_dac_drc_epslc::AC_DAC_DRC_EPSLC_SPEC
• audio_codec::ac_dac_drc_epslc::R
• audio_codec::ac_dac_drc_epslc::W
• audio_codec::ac_dac_drc_hct::AC_DAC_DRC_HCT_SPEC
• audio_codec::ac_dac_drc_hct::R
• audio_codec::ac_dac_drc_hct::W
• audio_codec::ac_dac_drc_het::AC_DAC_DRC_HET_SPEC
• audio_codec::ac_dac_drc_het::R
• audio_codec::ac_dac_drc_het::W
• audio_codec::ac_dac_drc_hhpfc::AC_DAC_DRC_HHPFC_SPEC
• audio_codec::ac_dac_drc_hhpfc::R
• audio_codec::ac_dac_drc_hhpfc::W
• audio_codec::ac_dac_drc_hkc::AC_DAC_DRC_HKC_SPEC
• audio_codec::ac_dac_drc_hkc::R
• audio_codec::ac_dac_drc_hkc::W
• audio_codec::ac_dac_drc_hke::AC_DAC_DRC_HKE_SPEC
• audio_codec::ac_dac_drc_hke::R
• audio_codec::ac_dac_drc_hke::W
• audio_codec::ac_dac_drc_hkl::AC_DAC_DRC_HKL_SPEC
• audio_codec::ac_dac_drc_hkl::R
• audio_codec::ac_dac_drc_hkl::W
• audio_codec::ac_dac_drc_hkn::AC_DAC_DRC_HKN_SPEC
• audio_codec::ac_dac_drc_hkn::R
• audio_codec::ac_dac_drc_hkn::W
• audio_codec::ac_dac_drc_hlt::AC_DAC_DRC_HLT_SPEC
• audio_codec::ac_dac_drc_hlt::R
• audio_codec::ac_dac_drc_hlt::W
• audio_codec::ac_dac_drc_hopc::AC_DAC_DRC_HOPC_SPEC
• audio_codec::ac_dac_drc_hopc::R
• audio_codec::ac_dac_drc_hopc::W
• audio_codec::ac_dac_drc_hope::AC_DAC_DRC_HOPE_SPEC
• audio_codec::ac_dac_drc_hope::R
• audio_codec::ac_dac_drc_hope::W
• audio_codec::ac_dac_drc_hopl::AC_DAC_DRC_HOPL_SPEC
• audio_codec::ac_dac_drc_hopl::R
• audio_codec::ac_dac_drc_hopl::W
• audio_codec::ac_dac_drc_hpfhgain::AC_DAC_DRC_HPFHGAIN_SPEC
• audio_codec::ac_dac_drc_hpfhgain::R
• audio_codec::ac_dac_drc_hpfhgain::W
• audio_codec::ac_dac_drc_hpflgain::AC_DAC_DRC_HPFLGAIN_SPEC
• audio_codec::ac_dac_drc_hpflgain::R
• audio_codec::ac_dac_drc_hpflgain::W
• audio_codec::ac_dac_drc_lct::AC_DAC_DRC_LCT_SPEC
• audio_codec::ac_dac_drc_lct::R
• audio_codec::ac_dac_drc_lct::W
• audio_codec::ac_dac_drc_let::AC_DAC_DRC_LET_SPEC
• audio_codec::ac_dac_drc_let::R
• audio_codec::ac_dac_drc_let::W
• audio_codec::ac_dac_drc_lhpfc::AC_DAC_DRC_LHPFC_SPEC
• audio_codec::ac_dac_drc_lhpfc::R
• audio_codec::ac_dac_drc_lhpfc::W
• audio_codec::ac_dac_drc_lkc::AC_DAC_DRC_LKC_SPEC
• audio_codec::ac_dac_drc_lkc::R
• audio_codec::ac_dac_drc_lkc::W
• audio_codec::ac_dac_drc_lke::AC_DAC_DRC_LKE_SPEC
• audio_codec::ac_dac_drc_lke::R
• audio_codec::ac_dac_drc_lke::W
• audio_codec::ac_dac_drc_lkl::AC_DAC_DRC_LKL_SPEC
• audio_codec::ac_dac_drc_lkl::R
• audio_codec::ac_dac_drc_lkl::W
• audio_codec::ac_dac_drc_lkn::AC_DAC_DRC_LKN_SPEC
• audio_codec::ac_dac_drc_lkn::R
• audio_codec::ac_dac_drc_lkn::W
• audio_codec::ac_dac_drc_llt::AC_DAC_DRC_LLT_SPEC
• audio_codec::ac_dac_drc_llt::R
• audio_codec::ac_dac_drc_llt::W
• audio_codec::ac_dac_drc_lopc::AC_DAC_DRC_LOPC_SPEC
• audio_codec::ac_dac_drc_lopc::R
• audio_codec::ac_dac_drc_lopc::W
• audio_codec::ac_dac_drc_lope::AC_DAC_DRC_LOPE_SPEC
• audio_codec::ac_dac_drc_lope::R
• audio_codec::ac_dac_drc_lope::W
• audio_codec::ac_dac_drc_lopl::AC_DAC_DRC_LOPL_SPEC
• audio_codec::ac_dac_drc_lopl::R
• audio_codec::ac_dac_drc_lopl::W
• audio_codec::ac_dac_drc_lpfhat::AC_DAC_DRC_LPFHAT_SPEC
• audio_codec::ac_dac_drc_lpfhat::R
• audio_codec::ac_dac_drc_lpfhat::W
• audio_codec::ac_dac_drc_lpfhrt::AC_DAC_DRC_LPFHRT_SPEC
• audio_codec::ac_dac_drc_lpfhrt::R
• audio_codec::ac_dac_drc_lpfhrt::W
• audio_codec::ac_dac_drc_lpflat::AC_DAC_DRC_LPFLAT_SPEC
• audio_codec::ac_dac_drc_lpflat::R
• audio_codec::ac_dac_drc_lpflat::W
• audio_codec::ac_dac_drc_lpflrt::AC_DAC_DRC_LPFLRT_SPEC
• audio_codec::ac_dac_drc_lpflrt::R
• audio_codec::ac_dac_drc_lpflrt::W
• audio_codec::ac_dac_drc_lrmshat::AC_DAC_DRC_LRMSHAT_SPEC
• audio_codec::ac_dac_drc_lrmshat::R
• audio_codec::ac_dac_drc_lrmshat::W
• audio_codec::ac_dac_drc_lrmslat::AC_DAC_DRC_LRMSLAT_SPEC
• audio_codec::ac_dac_drc_lrmslat::R
• audio_codec::ac_dac_drc_lrmslat::W
• audio_codec::ac_dac_drc_mnghs::AC_DAC_DRC_MNGHS_SPEC
• audio_codec::ac_dac_drc_mnghs::R
• audio_codec::ac_dac_drc_mnghs::W
• audio_codec::ac_dac_drc_mngls::AC_DAC_DRC_MNGLS_SPEC
• audio_codec::ac_dac_drc_mngls::R
• audio_codec::ac_dac_drc_mngls::W
• audio_codec::ac_dac_drc_mxghs::AC_DAC_DRC_MXGHS_SPEC
• audio_codec::ac_dac_drc_mxghs::R
• audio_codec::ac_dac_drc_mxghs::W
• audio_codec::ac_dac_drc_mxgls::AC_DAC_DRC_MXGLS_SPEC
• audio_codec::ac_dac_drc_mxgls::R
• audio_codec::ac_dac_drc_mxgls::W
• audio_codec::ac_dac_drc_rpfhat::AC_DAC_DRC_RPFHAT_SPEC
• audio_codec::ac_dac_drc_rpfhat::R
• audio_codec::ac_dac_drc_rpfhat::W
• audio_codec::ac_dac_drc_rpfhrt::AC_DAC_DRC_RPFHRT_SPEC
• audio_codec::ac_dac_drc_rpfhrt::R
• audio_codec::ac_dac_drc_rpfhrt::W
• audio_codec::ac_dac_drc_rpflat::AC_DAC_DRC_RPFLAT_SPEC
• audio_codec::ac_dac_drc_rpflat::R
• audio_codec::ac_dac_drc_rpflat::W
• audio_codec::ac_dac_drc_rpflrt::AC_DAC_DRC_RPFLRT_SPEC
• audio_codec::ac_dac_drc_rpflrt::R
• audio_codec::ac_dac_drc_rpflrt::W
• audio_codec::ac_dac_drc_rrmshat::AC_DAC_DRC_RRMSHAT_SPEC
• audio_codec::ac_dac_drc_rrmshat::R
• audio_codec::ac_dac_drc_rrmshat::W
• audio_codec::ac_dac_drc_rrmslat::AC_DAC_DRC_RRMSLAT_SPEC
• audio_codec::ac_dac_drc_rrmslat::R
• audio_codec::ac_dac_drc_rrmslat::W
• audio_codec::ac_dac_drc_sfhat::AC_DAC_DRC_SFHAT_SPEC
• audio_codec::ac_dac_drc_sfhat::R
• audio_codec::ac_dac_drc_sfhat::W
• audio_codec::ac_dac_drc_sfhrt::AC_DAC_DRC_SFHRT_SPEC
• audio_codec::ac_dac_drc_sfhrt::R
• audio_codec::ac_dac_drc_sfhrt::W
• audio_codec::ac_dac_drc_sflat::AC_DAC_DRC_SFLAT_SPEC
• audio_codec::ac_dac_drc_sflat::R
• audio_codec::ac_dac_drc_sflat::W
• audio_codec::ac_dac_drc_sflrt::AC_DAC_DRC_SFLRT_SPEC
• audio_codec::ac_dac_drc_sflrt::R
• audio_codec::ac_dac_drc_sflrt::W
• audio_codec::ac_dac_fifoc::AC_DAC_FIFOC_SPEC
• audio_codec::ac_dac_fifoc::R
• audio_codec::ac_dac_fifoc::W
• audio_codec::ac_dac_fifos::AC_DAC_FIFOS_SPEC
• audio_codec::ac_dac_fifos::R
• audio_codec::ac_dac_fifos::W
• audio_codec::ac_dac_txdata::AC_DAC_TXDATA_SPEC
• audio_codec::ac_dac_txdata::R
• audio_codec::ac_dac_txdata::W
• audio_codec::adc1_reg::ADC1_REG_SPEC
• audio_codec::adc1_reg::R
• audio_codec::adc1_reg::W
• audio_codec::adc2_reg::ADC2_REG_SPEC
• audio_codec::adc2_reg::R
• audio_codec::adc2_reg::W
• audio_codec::adc3_reg::ADC3_REG_SPEC
• audio_codec::adc3_reg::R
• audio_codec::adc3_reg::W
• audio_codec::adc5_reg::ADC5_REG_SPEC
• audio_codec::adc5_reg::R
• audio_codec::adc5_reg::W
• audio_codec::adc_dig_ctrl::ADC_DIG_CTRL_SPEC
• audio_codec::adc_dig_ctrl::R
• audio_codec::adc_dig_ctrl::W
• audio_codec::adc_vol_ctrl1::ADC_VOL_CTRL1_SPEC
• audio_codec::adc_vol_ctrl1::R
• audio_codec::adc_vol_ctrl1::W
• audio_codec::bias_reg::BIAS_REG_SPEC
• audio_codec::bias_reg::R
• audio_codec::bias_reg::W
• audio_codec::dac_reg::DAC_REG_SPEC
• audio_codec::dac_reg::R
• audio_codec::dac_reg::W
• audio_codec::dac_vol_ctrl::DAC_VOL_CTRL_SPEC
• audio_codec::dac_vol_ctrl::R
• audio_codec::dac_vol_ctrl::W
• audio_codec::micbias_reg::MICBIAS_REG_SPEC
• audio_codec::micbias_reg::R
• audio_codec::micbias_reg::W
• audio_codec::ramp_reg::R
• audio_codec::ramp_reg::RAMP_REG_SPEC
• audio_codec::ramp_reg::W
• audio_codec::vra1speedup_down_ctrl::R
• audio_codec::vra1speedup_down_ctrl::VRA1SPEEDUP_DOWN_CTRL_SPEC
• audio_codec::vra1speedup_down_ctrl::W
• ccu::RegisterBlock
• ccu::apb_clk::APB_CLK_SPEC
• ccu::apb_clk::R
• ccu::apb_clk::W
• ccu::audio_codec_adc_clk::AUDIO_CODEC_ADC_CLK_SPEC
• ccu::audio_codec_adc_clk::R
• ccu::audio_codec_adc_clk::W
• ccu::audio_codec_bgr::AUDIO_CODEC_BGR_SPEC
• ccu::audio_codec_bgr::R
• ccu::audio_codec_bgr::W
• ccu::audio_codec_dac_clk::AUDIO_CODEC_DAC_CLK_SPEC
• ccu::audio_codec_dac_clk::R
• ccu::audio_codec_dac_clk::W
• ccu::avs_clk::AVS_CLK_SPEC
• ccu::avs_clk::R
• ccu::avs_clk::W
• ccu::ccu_fan::CCU_FAN_SPEC
• ccu::ccu_fan::R
• ccu::ccu_fan::W
• ccu::ccu_fan_gate::CCU_FAN_GATE_SPEC
• ccu::ccu_fan_gate::R
• ccu::ccu_fan_gate::W
• ccu::ce_bgr::CE_BGR_SPEC
• ccu::ce_bgr::R
• ccu::ce_bgr::W
• ccu::ce_clk::CE_CLK_SPEC
• ccu::ce_clk::R
• ccu::ce_clk::W
• ccu::clk27m_fan::CLK27M_FAN_SPEC
• ccu::clk27m_fan::R
• ccu::clk27m_fan::W
• ccu::cpu_axi_cfg::CPU_AXI_CFG_SPEC
• ccu::cpu_axi_cfg::R
• ccu::cpu_axi_cfg::W
• ccu::cpu_gating::CPU_GATING_SPEC
• ccu::cpu_gating::R
• ccu::cpu_gating::W
• ccu::csi_bgr::CSI_BGR_SPEC
• ccu::csi_bgr::R
• ccu::csi_bgr::W
• ccu::csi_clk::CSI_CLK_SPEC
• ccu::csi_clk::R
• ccu::csi_clk::W
• ccu::csi_master_clk::CSI_MASTER_CLK_SPEC
• ccu::csi_master_clk::R
• ccu::csi_master_clk::W
• ccu::dbgsys_bgr::DBGSYS_BGR_SPEC
• ccu::dbgsys_bgr::R
• ccu::dbgsys_bgr::W
• ccu::de_bgr::DE_BGR_SPEC
• ccu::de_bgr::R
• ccu::de_bgr::W
• ccu::de_clk::DE_CLK_SPEC
• ccu::de_clk::R
• ccu::de_clk::W
• ccu::di_bgr::DI_BGR_SPEC
• ccu::di_bgr::R
• ccu::di_bgr::W
• ccu::di_clk::DI_CLK_SPEC
• ccu::di_clk::R
• ccu::di_clk::W
• ccu::dma_bgr::DMA_BGR_SPEC
• ccu::dma_bgr::R
• ccu::dma_bgr::W
• ccu::dmic_bgr::DMIC_BGR_SPEC
• ccu::dmic_bgr::R
• ccu::dmic_bgr::W
• ccu::dmic_clk::DMIC_CLK_SPEC
• ccu::dmic_clk::R
• ccu::dmic_clk::W
• ccu::dpss_top_bgr::DPSS_TOP_BGR_SPEC
• ccu::dpss_top_bgr::R
• ccu::dpss_top_bgr::W
• ccu::dram_bgr::DRAM_BGR_SPEC
• ccu::dram_bgr::R
• ccu::dram_bgr::W
• ccu::dram_clk::DRAM_CLK_SPEC
• ccu::dram_clk::R
• ccu::dram_clk::W
• ccu::dsi_bgr::DSI_BGR_SPEC
• ccu::dsi_bgr::R
• ccu::dsi_bgr::W
• ccu::dsi_clk::DSI_CLK_SPEC
• ccu::dsi_clk::R
• ccu::dsi_clk::W
• ccu::dsp_bgr::DSP_BGR_SPEC
• ccu::dsp_bgr::R
• ccu::dsp_bgr::W
• ccu::dsp_clk::DSP_CLK_SPEC
• ccu::dsp_clk::R
• ccu::dsp_clk::W
• ccu::emac_25m_clk::EMAC_25M_CLK_SPEC
• ccu::emac_25m_clk::R
• ccu::emac_25m_clk::W
• ccu::emac_bgr::EMAC_BGR_SPEC
• ccu::emac_bgr::R
• ccu::emac_bgr::W
• ccu::fre_det_ctrl::FRE_DET_CTRL_SPEC
• ccu::fre_det_ctrl::R
• ccu::fre_det_ctrl::W
• ccu::fre_down_lim::FRE_DOWN_LIM_SPEC
• ccu::fre_down_lim::R
• ccu::fre_down_lim::W
• ccu::fre_up_lim::FRE_UP_LIM_SPEC
• ccu::fre_up_lim::R
• ccu::fre_up_lim::W
• ccu::g2d_bgr::G2D_BGR_SPEC
• ccu::g2d_bgr::R
• ccu::g2d_bgr::W
• ccu::g2d_clk::G2D_CLK_SPEC
• ccu::g2d_clk::R
• ccu::g2d_clk::W
• ccu::gpadc_bgr::GPADC_BGR_SPEC
• ccu::gpadc_bgr::R
• ccu::gpadc_bgr::W
• ccu::hstimer_bgr::HSTIMER_BGR_SPEC
• ccu::hstimer_bgr::R
• ccu::hstimer_bgr::W
• ccu::i2s2_asrc_clk::I2S2_ASRC_CLK_SPEC
• ccu::i2s2_asrc_clk::R
• ccu::i2s2_asrc_clk::W
• ccu::i2s_bgr::I2S_BGR_SPEC
• ccu::i2s_bgr::R
• ccu::i2s_bgr::W
• ccu::i2s_clk::I2S_CLK_SPEC
• ccu::i2s_clk::R
• ccu::i2s_clk::W
• ccu::iommu_bgr::IOMMU_BGR_SPEC
• ccu::iommu_bgr::R
• ccu::iommu_bgr::W
• ccu::irtx_bgr::IRTX_BGR_SPEC
• ccu::irtx_bgr::R
• ccu::irtx_bgr::W
• ccu::irtx_clk::IRTX_CLK_SPEC
• ccu::irtx_clk::R
• ccu::irtx_clk::W
• ccu::ledc_bgr::LEDC_BGR_SPEC
• ccu::ledc_bgr::R
• ccu::ledc_bgr::W
• ccu::ledc_clk::LEDC_CLK_SPEC
• ccu::ledc_clk::R
• ccu::ledc_clk::W
• ccu::lradc_bgr::LRADC_BGR_SPEC
• ccu::lradc_bgr::R
• ccu::lradc_bgr::W
• ccu::lvds_bgr::LVDS_BGR_SPEC
• ccu::lvds_bgr::R
• ccu::lvds_bgr::W
• ccu::mbus_clk::MBUS_CLK_SPEC
• ccu::mbus_clk::R
• ccu::mbus_clk::W
• ccu::mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC
• ccu::mbus_mat_clk_gating::R
• ccu::mbus_mat_clk_gating::W
• ccu::msgbox_bgr::MSGBOX_BGR_SPEC
• ccu::msgbox_bgr::R
• ccu::msgbox_bgr::W
• ccu::owa_bgr::OWA_BGR_SPEC
• ccu::owa_bgr::R
• ccu::owa_bgr::W
• ccu::owa_rx_clk::OWA_RX_CLK_SPEC
• ccu::owa_rx_clk::R
• ccu::owa_rx_clk::W
• ccu::owa_tx_clk::OWA_TX_CLK_SPEC
• ccu::owa_tx_clk::R
• ccu::owa_tx_clk::W
• ccu::pclk_fan::PCLK_FAN_SPEC
• ccu::pclk_fan::R
• ccu::pclk_fan::W
• ccu::pll_audio0_bias::PLL_AUDIO0_BIAS_SPEC
• ccu::pll_audio0_bias::R
• ccu::pll_audio0_bias::W
• ccu::pll_audio0_ctrl::PLL_AUDIO0_CTRL_SPEC
• ccu::pll_audio0_ctrl::R
• ccu::pll_audio0_ctrl::W
• ccu::pll_audio0_pat0_ctrl::PLL_AUDIO0_PAT0_CTRL_SPEC
• ccu::pll_audio0_pat0_ctrl::R
• ccu::pll_audio0_pat0_ctrl::W
• ccu::pll_audio0_pat1_ctrl::PLL_AUDIO0_PAT1_CTRL_SPEC
• ccu::pll_audio0_pat1_ctrl::R
• ccu::pll_audio0_pat1_ctrl::W
• ccu::pll_audio1_bias::PLL_AUDIO1_BIAS_SPEC
• ccu::pll_audio1_bias::R
• ccu::pll_audio1_bias::W
• ccu::pll_audio1_ctrl::PLL_AUDIO1_CTRL_SPEC
• ccu::pll_audio1_ctrl::R
• ccu::pll_audio1_ctrl::W
• ccu::pll_audio1_pat0_ctrl::PLL_AUDIO1_PAT0_CTRL_SPEC
• ccu::pll_audio1_pat0_ctrl::R
• ccu::pll_audio1_pat0_ctrl::W
• ccu::pll_audio1_pat1_ctrl::PLL_AUDIO1_PAT1_CTRL_SPEC
• ccu::pll_audio1_pat1_ctrl::R
• ccu::pll_audio1_pat1_ctrl::W
• ccu::pll_cpu_bias::PLL_CPU_BIAS_SPEC
• ccu::pll_cpu_bias::R
• ccu::pll_cpu_bias::W
• ccu::pll_cpu_ctrl::PLL_CPU_CTRL_SPEC
• ccu::pll_cpu_ctrl::R
• ccu::pll_cpu_ctrl::W
• ccu::pll_cpu_tun::PLL_CPU_TUN_SPEC
• ccu::pll_cpu_tun::R
• ccu::pll_cpu_tun::W
• ccu::pll_ddr_bias::PLL_DDR_BIAS_SPEC
• ccu::pll_ddr_bias::R
• ccu::pll_ddr_bias::W
• ccu::pll_ddr_ctrl::PLL_DDR_CTRL_SPEC
• ccu::pll_ddr_ctrl::R
• ccu::pll_ddr_ctrl::W
• ccu::pll_ddr_pat0_ctrl::PLL_DDR_PAT0_CTRL_SPEC
• ccu::pll_ddr_pat0_ctrl::R
• ccu::pll_ddr_pat0_ctrl::W
• ccu::pll_ddr_pat1_ctrl::PLL_DDR_PAT1_CTRL_SPEC
• ccu::pll_ddr_pat1_ctrl::R
• ccu::pll_ddr_pat1_ctrl::W
• ccu::pll_lock_dbg_ctrl::PLL_LOCK_DBG_CTRL_SPEC
• ccu::pll_lock_dbg_ctrl::R
• ccu::pll_lock_dbg_ctrl::W
• ccu::pll_peri_bias::PLL_PERI_BIAS_SPEC
• ccu::pll_peri_bias::R
• ccu::pll_peri_bias::W
• ccu::pll_peri_ctrl::PLL_PERI_CTRL_SPEC
• ccu::pll_peri_ctrl::R
• ccu::pll_peri_ctrl::W
• ccu::pll_peri_pat0_ctrl::PLL_PERI_PAT0_CTRL_SPEC
• ccu::pll_peri_pat0_ctrl::R
• ccu::pll_peri_pat0_ctrl::W
• ccu::pll_peri_pat1_ctrl::PLL_PERI_PAT1_CTRL_SPEC
• ccu::pll_peri_pat1_ctrl::R
• ccu::pll_peri_pat1_ctrl::W
• ccu::pll_ve_bias::PLL_VE_BIAS_SPEC
• ccu::pll_ve_bias::R
• ccu::pll_ve_bias::W
• ccu::pll_ve_ctrl::PLL_VE_CTRL_SPEC
• ccu::pll_ve_ctrl::R
• ccu::pll_ve_ctrl::W
• ccu::pll_ve_pat0_ctrl::PLL_VE_PAT0_CTRL_SPEC
• ccu::pll_ve_pat0_ctrl::R
• ccu::pll_ve_pat0_ctrl::W
• ccu::pll_ve_pat1_ctrl::PLL_VE_PAT1_CTRL_SPEC
• ccu::pll_ve_pat1_ctrl::R
• ccu::pll_ve_pat1_ctrl::W
• ccu::pll_video0_bias::PLL_VIDEO0_BIAS_SPEC
• ccu::pll_video0_bias::R
• ccu::pll_video0_bias::W
• ccu::pll_video0_ctrl::PLL_VIDEO0_CTRL_SPEC
• ccu::pll_video0_ctrl::R
• ccu::pll_video0_ctrl::W
• ccu::pll_video0_pat0_ctrl::PLL_VIDEO0_PAT0_CTRL_SPEC
• ccu::pll_video0_pat0_ctrl::R
• ccu::pll_video0_pat0_ctrl::W
• ccu::pll_video0_pat1_ctrl::PLL_VIDEO0_PAT1_CTRL_SPEC
• ccu::pll_video0_pat1_ctrl::R
• ccu::pll_video0_pat1_ctrl::W
• ccu::pll_video1_bias::PLL_VIDEO1_BIAS_SPEC
• ccu::pll_video1_bias::R
• ccu::pll_video1_bias::W
• ccu::pll_video1_ctrl::PLL_VIDEO1_CTRL_SPEC
• ccu::pll_video1_ctrl::R
• ccu::pll_video1_ctrl::W
• ccu::pll_video1_pat0_ctrl::PLL_VIDEO1_PAT0_CTRL_SPEC
• ccu::pll_video1_pat0_ctrl::R
• ccu::pll_video1_pat0_ctrl::W
• ccu::pll_video1_pat1_ctrl::PLL_VIDEO1_PAT1_CTRL_SPEC
• ccu::pll_video1_pat1_ctrl::R
• ccu::pll_video1_pat1_ctrl::W
• ccu::psi_clk::PSI_CLK_SPEC
• ccu::psi_clk::R
• ccu::psi_clk::W
• ccu::pwm_bgr::PWM_BGR_SPEC
• ccu::pwm_bgr::R
• ccu::pwm_bgr::W
• ccu::riscv_cfg_bgr::R
• ccu::riscv_cfg_bgr::RISCV_CFG_BGR_SPEC
• ccu::riscv_cfg_bgr::W
• ccu::riscv_clk::R
• ccu::riscv_clk::RISCV_CLK_SPEC
• ccu::riscv_clk::W
• ccu::riscv_gating::R
• ccu::riscv_gating::RISCV_GATING_SPEC
• ccu::riscv_gating::W
• ccu::smhc0_clk::R
• ccu::smhc0_clk::SMHC0_CLK_SPEC
• ccu::smhc0_clk::W
• ccu::smhc1_clk::R
• ccu::smhc1_clk::SMHC1_CLK_SPEC
• ccu::smhc1_clk::W
• ccu::smhc2_clk::R
• ccu::smhc2_clk::SMHC2_CLK_SPEC
• ccu::smhc2_clk::W
• ccu::smhc_bgr::R
• ccu::smhc_bgr::SMHC_BGR_SPEC
• ccu::smhc_bgr::W
• ccu::spi0_clk::R
• ccu::spi0_clk::SPI0_CLK_SPEC
• ccu::spi0_clk::W
• ccu::spi1_clk::R
• ccu::spi1_clk::SPI1_CLK_SPEC
• ccu::spi1_clk::W
• ccu::spi_bgr::R
• ccu::spi_bgr::SPI_BGR_SPEC
• ccu::spi_bgr::W
• ccu::spinlock_bgr::R
• ccu::spinlock_bgr::SPINLOCK_BGR_SPEC
• ccu::spinlock_bgr::W
• ccu::tconlcd_bgr::R
• ccu::tconlcd_bgr::TCONLCD_BGR_SPEC
• ccu::tconlcd_bgr::W
• ccu::tconlcd_clk::R
• ccu::tconlcd_clk::TCONLCD_CLK_SPEC
• ccu::tconlcd_clk::W
• ccu::tcontv_bgr::R
• ccu::tcontv_bgr::TCONTV_BGR_SPEC
• ccu::tcontv_bgr::W
• ccu::tcontv_clk::R
• ccu::tcontv_clk::TCONTV_CLK_SPEC
• ccu::tcontv_clk::W
• ccu::ths_bgr::R
• ccu::ths_bgr::THS_BGR_SPEC
• ccu::ths_bgr::W
• ccu::tpadc_bgr::R
• ccu::tpadc_bgr::TPADC_BGR_SPEC
• ccu::tpadc_bgr::W
• ccu::tpadc_clk::R
• ccu::tpadc_clk::TPADC_CLK_SPEC
• ccu::tpadc_clk::W
• ccu::tvd_bgr::R
• ccu::tvd_bgr::TVD_BGR_SPEC
• ccu::tvd_bgr::W
• ccu::tvd_clk::R
• ccu::tvd_clk::TVD_CLK_SPEC
• ccu::tvd_clk::W
• ccu::tve_bgr::R
• ccu::tve_bgr::TVE_BGR_SPEC
• ccu::tve_bgr::W
• ccu::tve_clk::R
• ccu::tve_clk::TVE_CLK_SPEC
• ccu::tve_clk::W
• ccu::twi_bgr::R
• ccu::twi_bgr::TWI_BGR_SPEC
• ccu::twi_bgr::W
• ccu::uart_bgr::R
• ccu::uart_bgr::UART_BGR_SPEC
• ccu::uart_bgr::W
• ccu::usb0_clk::R
• ccu::usb0_clk::USB0_CLK_SPEC
• ccu::usb0_clk::W
• ccu::usb1_clk::R
• ccu::usb1_clk::USB1_CLK_SPEC
• ccu::usb1_clk::W
• ccu::usb_bgr::R
• ccu::usb_bgr::USB_BGR_SPEC
• ccu::usb_bgr::W
• ccu::ve_bgr::R
• ccu::ve_bgr::VE_BGR_SPEC
• ccu::ve_bgr::W
• ccu::ve_clk::R
• ccu::ve_clk::VE_CLK_SPEC
• ccu::ve_clk::W
• ce_ns::RegisterBlock
• ce_ns::ce_cda::CE_CDA_SPEC
• ce_ns::ce_cda::R
• ce_ns::ce_cda::W
• ce_ns::ce_csa::CE_CSA_SPEC
• ce_ns::ce_csa::R
• ce_ns::ce_csa::W
• ce_ns::ce_esr::CE_ESR_SPEC
• ce_ns::ce_esr::R
• ce_ns::ce_esr::W
• ce_ns::ce_icr::CE_ICR_SPEC
• ce_ns::ce_icr::R
• ce_ns::ce_icr::W
• ce_ns::ce_isr::CE_ISR_SPEC
• ce_ns::ce_isr::R
• ce_ns::ce_isr::W
• ce_ns::ce_tda::CE_TDA_SPEC
• ce_ns::ce_tda::R
• ce_ns::ce_tda::W
• ce_ns::ce_tlr::CE_TLR_SPEC
• ce_ns::ce_tlr::R
• ce_ns::ce_tlr::W
• ce_ns::ce_tpr::CE_TPR_SPEC
• ce_ns::ce_tpr::R
• ce_ns::ce_tpr::W
• ce_ns::ce_tsr::CE_TSR_SPEC
• ce_ns::ce_tsr::R
• ce_ns::ce_tsr::W
• cir_rx::RegisterBlock
• cir_rx::cir_ctl::CIR_CTL_SPEC
• cir_rx::cir_ctl::R
• cir_rx::cir_ctl::W
• cir_rx::cir_rxcfg::CIR_RXCFG_SPEC
• cir_rx::cir_rxcfg::R
• cir_rx::cir_rxcfg::W
• cir_rx::cir_rxfifo::CIR_RXFIFO_SPEC
• cir_rx::cir_rxfifo::R
• cir_rx::cir_rxfifo::W
• cir_rx::cir_rxint::CIR_RXINT_SPEC
• cir_rx::cir_rxint::R
• cir_rx::cir_rxint::W
• cir_rx::cir_rxpcfg::CIR_RXPCFG_SPEC
• cir_rx::cir_rxpcfg::R
• cir_rx::cir_rxpcfg::W
• cir_rx::cir_rxsta::CIR_RXSTA_SPEC
• cir_rx::cir_rxsta::R
• cir_rx::cir_rxsta::W
• cir_tx::RegisterBlock
• cir_tx::cir_dma_ctl::CIR_DMA_CTL_SPEC
• cir_tx::cir_dma_ctl::R
• cir_tx::cir_dma_ctl::W
• cir_tx::cir_idc_h::CIR_IDC_H_SPEC
• cir_tx::cir_idc_h::R
• cir_tx::cir_idc_h::W
• cir_tx::cir_idc_l::CIR_IDC_L_SPEC
• cir_tx::cir_idc_l::R
• cir_tx::cir_idc_l::W
• cir_tx::cir_tac::CIR_TAC_SPEC
• cir_tx::cir_tac::R
• cir_tx::cir_tac::W
• cir_tx::cir_tcr::CIR_TCR_SPEC
• cir_tx::cir_tcr::R
• cir_tx::cir_tcr::W
• cir_tx::cir_tel::CIR_TEL_SPEC
• cir_tx::cir_tel::R
• cir_tx::cir_tel::W
• cir_tx::cir_tglr::CIR_TGLR_SPEC
• cir_tx::cir_tglr::R
• cir_tx::cir_tglr::W
• cir_tx::cir_ticr_h::CIR_TICR_H_SPEC
• cir_tx::cir_ticr_h::R
• cir_tx::cir_ticr_h::W
• cir_tx::cir_ticr_l::CIR_TICR_L_SPEC
• cir_tx::cir_ticr_l::R
• cir_tx::cir_ticr_l::W
• cir_tx::cir_tmcr::CIR_TMCR_SPEC
• cir_tx::cir_tmcr::R
• cir_tx::cir_tmcr::W
• cir_tx::cir_txfifo::CIR_TXFIFO_SPEC
• cir_tx::cir_txfifo::R
• cir_tx::cir_txfifo::W
• cir_tx::cir_txint::CIR_TXINT_SPEC
• cir_tx::cir_txint::R
• cir_tx::cir_txint::W
• cir_tx::cir_txsta::CIR_TXSTA_SPEC
• cir_tx::cir_txsta::R
• cir_tx::cir_txsta::W
• cir_tx::cir_txt::CIR_TXT_SPEC
• cir_tx::cir_txt::R
• cir_tx::cir_txt::W
• csic::CSIC_CCU
• csic::CSIC_DMA
• csic::CSIC_PARSER0
• csic::CSIC_TOP
• csic::RegisterBlock
• csic::csic_ccu::ccu_clk_mode_reg::CCU_CLK_MODE_REG_SPEC
• csic::csic_ccu::ccu_clk_mode_reg::R
• csic::csic_ccu::ccu_clk_mode_reg::W
• csic::csic_ccu::ccu_parser_clk_en_reg::CCU_PARSER_CLK_EN_REG_SPEC
• csic::csic_ccu::ccu_parser_clk_en_reg::R
• csic::csic_ccu::ccu_parser_clk_en_reg::W
• csic::csic_ccu::ccu_post0_clk_en_reg::CCU_POST0_CLK_EN_REG_SPEC
• csic::csic_ccu::ccu_post0_clk_en_reg::R
• csic::csic_ccu::ccu_post0_clk_en_reg::W
• csic::csic_dma::csic_dma_acc_itnl_clk_cnt_reg::CSIC_DMA_ACC_ITNL_CLK_CNT_REG_SPEC
• csic::csic_dma::csic_dma_acc_itnl_clk_cnt_reg::R
• csic::csic_dma::csic_dma_acc_itnl_clk_cnt_reg::W
• csic::csic_dma::csic_dma_buf_addr_fifo0_entry_reg::CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG_SPEC
• csic::csic_dma::csic_dma_buf_addr_fifo0_entry_reg::R
• csic::csic_dma::csic_dma_buf_addr_fifo0_entry_reg::W
• csic::csic_dma::csic_dma_buf_addr_fifo1_entry_reg::CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG_SPEC
• csic::csic_dma::csic_dma_buf_addr_fifo1_entry_reg::R
• csic::csic_dma::csic_dma_buf_addr_fifo1_entry_reg::W
• csic::csic_dma::csic_dma_buf_addr_fifo2_entry_reg::CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG_SPEC
• csic::csic_dma::csic_dma_buf_addr_fifo2_entry_reg::R
• csic::csic_dma::csic_dma_buf_addr_fifo2_entry_reg::W
• csic::csic_dma::csic_dma_buf_addr_fifo_con_reg::CSIC_DMA_BUF_ADDR_FIFO_CON_REG_SPEC
• csic::csic_dma::csic_dma_buf_addr_fifo_con_reg::R
• csic::csic_dma::csic_dma_buf_addr_fifo_con_reg::W
• csic::csic_dma::csic_dma_buf_len_reg::CSIC_DMA_BUF_LEN_REG_SPEC
• csic::csic_dma::csic_dma_buf_len_reg::R
• csic::csic_dma::csic_dma_buf_len_reg::W
• csic::csic_dma::csic_dma_buf_th_reg::CSIC_DMA_BUF_TH_REG_SPEC
• csic::csic_dma::csic_dma_buf_th_reg::R
• csic::csic_dma::csic_dma_buf_th_reg::W
• csic::csic_dma::csic_dma_cap_sta_reg::CSIC_DMA_CAP_STA_REG_SPEC
• csic::csic_dma::csic_dma_cap_sta_reg::R
• csic::csic_dma::csic_dma_cap_sta_reg::W
• csic::csic_dma::csic_dma_cfg_reg::CSIC_DMA_CFG_REG_SPEC
• csic::csic_dma::csic_dma_cfg_reg::R
• csic::csic_dma::csic_dma_cfg_reg::W
• csic::csic_dma::csic_dma_en_reg::CSIC_DMA_EN_REG_SPEC
• csic::csic_dma::csic_dma_en_reg::R
• csic::csic_dma::csic_dma_en_reg::W
• csic::csic_dma::csic_dma_f0_bufa_reg::CSIC_DMA_F0_BUFA_REG_SPEC
• csic::csic_dma::csic_dma_f0_bufa_reg::R
• csic::csic_dma::csic_dma_f0_bufa_reg::W
• csic::csic_dma::csic_dma_f0_bufa_result_reg::CSIC_DMA_F0_BUFA_RESULT_REG_SPEC
• csic::csic_dma::csic_dma_f0_bufa_result_reg::R
• csic::csic_dma::csic_dma_f0_bufa_result_reg::W
• csic::csic_dma::csic_dma_f1_bufa_reg::CSIC_DMA_F1_BUFA_REG_SPEC
• csic::csic_dma::csic_dma_f1_bufa_reg::R
• csic::csic_dma::csic_dma_f1_bufa_reg::W
• csic::csic_dma::csic_dma_f1_bufa_result_reg::CSIC_DMA_F1_BUFA_RESULT_REG_SPEC
• csic::csic_dma::csic_dma_f1_bufa_result_reg::R
• csic::csic_dma::csic_dma_f1_bufa_result_reg::W
• csic::csic_dma::csic_dma_f2_bufa_reg::CSIC_DMA_F2_BUFA_REG_SPEC
• csic::csic_dma::csic_dma_f2_bufa_reg::R
• csic::csic_dma::csic_dma_f2_bufa_reg::W
• csic::csic_dma::csic_dma_f2_bufa_result_reg::CSIC_DMA_F2_BUFA_RESULT_REG_SPEC
• csic::csic_dma::csic_dma_f2_bufa_result_reg::R
• csic::csic_dma::csic_dma_f2_bufa_result_reg::W
• csic::csic_dma::csic_dma_fifo_stat_reg::CSIC_DMA_FIFO_STAT_REG_SPEC
• csic::csic_dma::csic_dma_fifo_stat_reg::R
• csic::csic_dma::csic_dma_fifo_stat_reg::W
• csic::csic_dma::csic_dma_fifo_thrs_reg::CSIC_DMA_FIFO_THRS_REG_SPEC
• csic::csic_dma::csic_dma_fifo_thrs_reg::R
• csic::csic_dma::csic_dma_fifo_thrs_reg::W
• csic::csic_dma::csic_dma_flip_size_reg::CSIC_DMA_FLIP_SIZE_REG_SPEC
• csic::csic_dma::csic_dma_flip_size_reg::R
• csic::csic_dma::csic_dma_flip_size_reg::W
• csic::csic_dma::csic_dma_frm_clk_cnt_reg::CSIC_DMA_FRM_CLK_CNT_REG_SPEC
• csic::csic_dma::csic_dma_frm_clk_cnt_reg::R
• csic::csic_dma::csic_dma_frm_clk_cnt_reg::W
• csic::csic_dma::csic_dma_frm_cnt_reg::CSIC_DMA_FRM_CNT_REG_SPEC
• csic::csic_dma::csic_dma_frm_cnt_reg::R
• csic::csic_dma::csic_dma_frm_cnt_reg::W
• csic::csic_dma::csic_dma_hsize_reg::CSIC_DMA_HSIZE_REG_SPEC
• csic::csic_dma::csic_dma_hsize_reg::R
• csic::csic_dma::csic_dma_hsize_reg::W
• csic::csic_dma::csic_dma_int_en_reg::CSIC_DMA_INT_EN_REG_SPEC
• csic::csic_dma::csic_dma_int_en_reg::R
• csic::csic_dma::csic_dma_int_en_reg::W
• csic::csic_dma::csic_dma_int_sta_reg::CSIC_DMA_INT_STA_REG_SPEC
• csic::csic_dma::csic_dma_int_sta_reg::R
• csic::csic_dma::csic_dma_int_sta_reg::W
• csic::csic_dma::csic_dma_line_cnt_reg::CSIC_DMA_LINE_CNT_REG_SPEC
• csic::csic_dma::csic_dma_line_cnt_reg::R
• csic::csic_dma::csic_dma_line_cnt_reg::W
• csic::csic_dma::csic_dma_pclk_stat_reg::CSIC_DMA_PCLK_STAT_REG_SPEC
• csic::csic_dma::csic_dma_pclk_stat_reg::R
• csic::csic_dma::csic_dma_pclk_stat_reg::W
• csic::csic_dma::csic_dma_stored_frm_cnt_reg::CSIC_DMA_STORED_FRM_CNT_REG_SPEC
• csic::csic_dma::csic_dma_stored_frm_cnt_reg::R
• csic::csic_dma::csic_dma_stored_frm_cnt_reg::W
• csic::csic_dma::csic_dma_vi_to_cnt_val_reg::CSIC_DMA_VI_TO_CNT_VAL_REG_SPEC
• csic::csic_dma::csic_dma_vi_to_cnt_val_reg::R
• csic::csic_dma::csic_dma_vi_to_cnt_val_reg::W
• csic::csic_dma::csic_dma_vi_to_th0_reg::CSIC_DMA_VI_TO_TH0_REG_SPEC
• csic::csic_dma::csic_dma_vi_to_th0_reg::R
• csic::csic_dma::csic_dma_vi_to_th0_reg::W
• csic::csic_dma::csic_dma_vi_to_th1_reg::CSIC_DMA_VI_TO_TH1_REG_SPEC
• csic::csic_dma::csic_dma_vi_to_th1_reg::R
• csic::csic_dma::csic_dma_vi_to_th1_reg::W
• csic::csic_dma::csic_dma_vsize_reg::CSIC_DMA_VSIZE_REG_SPEC
• csic::csic_dma::csic_dma_vsize_reg::R
• csic::csic_dma::csic_dma_vsize_reg::W
• csic::csic_dma::csic_feature_reg::CSIC_FEATURE_REG_SPEC
• csic::csic_dma::csic_feature_reg::R
• csic::csic_dma::csic_feature_reg::W
• csic::csic_parser0::csic_prs_ncsic_bt656_head_cfg_reg::CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG_SPEC
• csic::csic_parser0::csic_prs_ncsic_bt656_head_cfg_reg::R
• csic::csic_parser0::csic_prs_ncsic_bt656_head_cfg_reg::W
• csic::csic_parser0::csic_prs_ncsic_rx_signal0_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG_SPEC
• csic::csic_parser0::csic_prs_ncsic_rx_signal0_dly_adj_reg::R
• csic::csic_parser0::csic_prs_ncsic_rx_signal0_dly_adj_reg::W
• csic::csic_parser0::csic_prs_ncsic_rx_signal5_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG_SPEC
• csic::csic_parser0::csic_prs_ncsic_rx_signal5_dly_adj_reg::R
• csic::csic_parser0::csic_prs_ncsic_rx_signal5_dly_adj_reg::W
• csic::csic_parser0::csic_prs_ncsic_rx_signal6_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG_SPEC
• csic::csic_parser0::csic_prs_ncsic_rx_signal6_dly_adj_reg::R
• csic::csic_parser0::csic_prs_ncsic_rx_signal6_dly_adj_reg::W
• csic::csic_parser0::csic_prs_signal_sta_reg::CSIC_PRS_SIGNAL_STA_REG_SPEC
• csic::csic_parser0::csic_prs_signal_sta_reg::R
• csic::csic_parser0::csic_prs_signal_sta_reg::W
• csic::csic_parser0::prs_c0_infmt_reg::PRS_C0_INFMT_REG_SPEC
• csic::csic_parser0::prs_c0_infmt_reg::R
• csic::csic_parser0::prs_c0_infmt_reg::W
• csic::csic_parser0::prs_c0_input_para0_reg::PRS_C0_INPUT_PARA0_REG_SPEC
• csic::csic_parser0::prs_c0_input_para0_reg::R
• csic::csic_parser0::prs_c0_input_para0_reg::W
• csic::csic_parser0::prs_c0_input_para1_reg::PRS_C0_INPUT_PARA1_REG_SPEC
• csic::csic_parser0::prs_c0_input_para1_reg::R
• csic::csic_parser0::prs_c0_input_para1_reg::W
• csic::csic_parser0::prs_c0_input_para2_reg::PRS_C0_INPUT_PARA2_REG_SPEC
• csic::csic_parser0::prs_c0_input_para2_reg::R
• csic::csic_parser0::prs_c0_input_para2_reg::W
• csic::csic_parser0::prs_c0_input_para3_reg::PRS_C0_INPUT_PARA3_REG_SPEC
• csic::csic_parser0::prs_c0_input_para3_reg::R
• csic::csic_parser0::prs_c0_input_para3_reg::W
• csic::csic_parser0::prs_c0_int_en_reg::PRS_C0_INT_EN_REG_SPEC
• csic::csic_parser0::prs_c0_int_en_reg::R
• csic::csic_parser0::prs_c0_int_en_reg::W
• csic::csic_parser0::prs_c0_int_sta_reg::PRS_C0_INT_STA_REG_SPEC
• csic::csic_parser0::prs_c0_int_sta_reg::R
• csic::csic_parser0::prs_c0_int_sta_reg::W
• csic::csic_parser0::prs_c0_output_hsize_reg::PRS_C0_OUTPUT_HSIZE_REG_SPEC
• csic::csic_parser0::prs_c0_output_hsize_reg::R
• csic::csic_parser0::prs_c0_output_hsize_reg::W
• csic::csic_parser0::prs_c0_output_vsize_reg::PRS_C0_OUTPUT_VSIZE_REG_SPEC
• csic::csic_parser0::prs_c0_output_vsize_reg::R
• csic::csic_parser0::prs_c0_output_vsize_reg::W
• csic::csic_parser0::prs_c1_infmt_reg::PRS_C1_INFMT_REG_SPEC
• csic::csic_parser0::prs_c1_infmt_reg::R
• csic::csic_parser0::prs_c1_infmt_reg::W
• csic::csic_parser0::prs_c1_input_para0_reg::PRS_C1_INPUT_PARA0_REG_SPEC
• csic::csic_parser0::prs_c1_input_para0_reg::R
• csic::csic_parser0::prs_c1_input_para0_reg::W
• csic::csic_parser0::prs_c1_input_para1_reg::PRS_C1_INPUT_PARA1_REG_SPEC
• csic::csic_parser0::prs_c1_input_para1_reg::R
• csic::csic_parser0::prs_c1_input_para1_reg::W
• csic::csic_parser0::prs_c1_input_para2_reg::PRS_C1_INPUT_PARA2_REG_SPEC
• csic::csic_parser0::prs_c1_input_para2_reg::R
• csic::csic_parser0::prs_c1_input_para2_reg::W
• csic::csic_parser0::prs_c1_input_para3_reg::PRS_C1_INPUT_PARA3_REG_SPEC
• csic::csic_parser0::prs_c1_input_para3_reg::R
• csic::csic_parser0::prs_c1_input_para3_reg::W
• csic::csic_parser0::prs_c1_int_en_reg::PRS_C1_INT_EN_REG_SPEC
• csic::csic_parser0::prs_c1_int_en_reg::R
• csic::csic_parser0::prs_c1_int_en_reg::W
• csic::csic_parser0::prs_c1_int_sta_reg::PRS_C1_INT_STA_REG_SPEC
• csic::csic_parser0::prs_c1_int_sta_reg::R
• csic::csic_parser0::prs_c1_int_sta_reg::W
• csic::csic_parser0::prs_c1_output_hsize_reg::PRS_C1_OUTPUT_HSIZE_REG_SPEC
• csic::csic_parser0::prs_c1_output_hsize_reg::R
• csic::csic_parser0::prs_c1_output_hsize_reg::W
• csic::csic_parser0::prs_c1_output_vsize_reg::PRS_C1_OUTPUT_VSIZE_REG_SPEC
• csic::csic_parser0::prs_c1_output_vsize_reg::R
• csic::csic_parser0::prs_c1_output_vsize_reg::W
• csic::csic_parser0::prs_c2_infmt_reg::PRS_C2_INFMT_REG_SPEC
• csic::csic_parser0::prs_c2_infmt_reg::R
• csic::csic_parser0::prs_c2_infmt_reg::W
• csic::csic_parser0::prs_c2_input_para0_reg::PRS_C2_INPUT_PARA0_REG_SPEC
• csic::csic_parser0::prs_c2_input_para0_reg::R
• csic::csic_parser0::prs_c2_input_para0_reg::W
• csic::csic_parser0::prs_c2_input_para1_reg::PRS_C2_INPUT_PARA1_REG_SPEC
• csic::csic_parser0::prs_c2_input_para1_reg::R
• csic::csic_parser0::prs_c2_input_para1_reg::W
• csic::csic_parser0::prs_c2_input_para2_reg::PRS_C2_INPUT_PARA2_REG_SPEC
• csic::csic_parser0::prs_c2_input_para2_reg::R
• csic::csic_parser0::prs_c2_input_para2_reg::W
• csic::csic_parser0::prs_c2_input_para3_reg::PRS_C2_INPUT_PARA3_REG_SPEC
• csic::csic_parser0::prs_c2_input_para3_reg::R
• csic::csic_parser0::prs_c2_input_para3_reg::W
• csic::csic_parser0::prs_c2_int_en_reg::PRS_C2_INT_EN_REG_SPEC
• csic::csic_parser0::prs_c2_int_en_reg::R
• csic::csic_parser0::prs_c2_int_en_reg::W
• csic::csic_parser0::prs_c2_int_sta_reg::PRS_C2_INT_STA_REG_SPEC
• csic::csic_parser0::prs_c2_int_sta_reg::R
• csic::csic_parser0::prs_c2_int_sta_reg::W
• csic::csic_parser0::prs_c2_output_hsize_reg::PRS_C2_OUTPUT_HSIZE_REG_SPEC
• csic::csic_parser0::prs_c2_output_hsize_reg::R
• csic::csic_parser0::prs_c2_output_hsize_reg::W
• csic::csic_parser0::prs_c2_output_vsize_reg::PRS_C2_OUTPUT_VSIZE_REG_SPEC
• csic::csic_parser0::prs_c2_output_vsize_reg::R
• csic::csic_parser0::prs_c2_output_vsize_reg::W
• csic::csic_parser0::prs_c3_infmt_reg::PRS_C3_INFMT_REG_SPEC
• csic::csic_parser0::prs_c3_infmt_reg::R
• csic::csic_parser0::prs_c3_infmt_reg::W
• csic::csic_parser0::prs_c3_input_para0_reg::PRS_C3_INPUT_PARA0_REG_SPEC
• csic::csic_parser0::prs_c3_input_para0_reg::R
• csic::csic_parser0::prs_c3_input_para0_reg::W
• csic::csic_parser0::prs_c3_input_para1_reg::PRS_C3_INPUT_PARA1_REG_SPEC
• csic::csic_parser0::prs_c3_input_para1_reg::R
• csic::csic_parser0::prs_c3_input_para1_reg::W
• csic::csic_parser0::prs_c3_input_para2_reg::PRS_C3_INPUT_PARA2_REG_SPEC
• csic::csic_parser0::prs_c3_input_para2_reg::R
• csic::csic_parser0::prs_c3_input_para2_reg::W
• csic::csic_parser0::prs_c3_input_para3_reg::PRS_C3_INPUT_PARA3_REG_SPEC
• csic::csic_parser0::prs_c3_input_para3_reg::R
• csic::csic_parser0::prs_c3_input_para3_reg::W
• csic::csic_parser0::prs_c3_int_en_reg::PRS_C3_INT_EN_REG_SPEC
• csic::csic_parser0::prs_c3_int_en_reg::R
• csic::csic_parser0::prs_c3_int_en_reg::W
• csic::csic_parser0::prs_c3_int_sta_reg::PRS_C3_INT_STA_REG_SPEC
• csic::csic_parser0::prs_c3_int_sta_reg::R
• csic::csic_parser0::prs_c3_int_sta_reg::W
• csic::csic_parser0::prs_c3_output_hsize_reg::PRS_C3_OUTPUT_HSIZE_REG_SPEC
• csic::csic_parser0::prs_c3_output_hsize_reg::R
• csic::csic_parser0::prs_c3_output_hsize_reg::W
• csic::csic_parser0::prs_c3_output_vsize_reg::PRS_C3_OUTPUT_VSIZE_REG_SPEC
• csic::csic_parser0::prs_c3_output_vsize_reg::R
• csic::csic_parser0::prs_c3_output_vsize_reg::W
• csic::csic_parser0::prs_cap_reg::PRS_CAP_REG_SPEC
• csic::csic_parser0::prs_cap_reg::R
• csic::csic_parser0::prs_cap_reg::W
• csic::csic_parser0::prs_ch0_line_time_reg::PRS_CH0_LINE_TIME_REG_SPEC
• csic::csic_parser0::prs_ch0_line_time_reg::R
• csic::csic_parser0::prs_ch0_line_time_reg::W
• csic::csic_parser0::prs_ch1_line_time_reg::PRS_CH1_LINE_TIME_REG_SPEC
• csic::csic_parser0::prs_ch1_line_time_reg::R
• csic::csic_parser0::prs_ch1_line_time_reg::W
• csic::csic_parser0::prs_ch2_line_time_reg::PRS_CH2_LINE_TIME_REG_SPEC
• csic::csic_parser0::prs_ch2_line_time_reg::R
• csic::csic_parser0::prs_ch2_line_time_reg::W
• csic::csic_parser0::prs_ch3_line_time_reg::PRS_CH3_LINE_TIME_REG_SPEC
• csic::csic_parser0::prs_ch3_line_time_reg::R
• csic::csic_parser0::prs_ch3_line_time_reg::W
• csic::csic_parser0::prs_en_reg::PRS_EN_REG_SPEC
• csic::csic_parser0::prs_en_reg::R
• csic::csic_parser0::prs_en_reg::W
• csic::csic_parser0::prs_ncsic_if_cfg_reg::PRS_NCSIC_IF_CFG_REG_SPEC
• csic::csic_parser0::prs_ncsic_if_cfg_reg::R
• csic::csic_parser0::prs_ncsic_if_cfg_reg::W
• csic::csic_top::csic_bist_control_reg::CSIC_BIST_CONTROL_REG_SPEC
• csic::csic_top::csic_bist_control_reg::R
• csic::csic_top::csic_bist_control_reg::W
• csic::csic_top::csic_bist_cs_reg::CSIC_BIST_CS_REG_SPEC
• csic::csic_top::csic_bist_cs_reg::R
• csic::csic_top::csic_bist_cs_reg::W
• csic::csic_top::csic_bist_data_mask_reg::CSIC_BIST_DATA_MASK_REG_SPEC
• csic::csic_top::csic_bist_data_mask_reg::R
• csic::csic_top::csic_bist_data_mask_reg::W
• csic::csic_top::csic_bist_end_reg::CSIC_BIST_END_REG_SPEC
• csic::csic_top::csic_bist_end_reg::R
• csic::csic_top::csic_bist_end_reg::W
• csic::csic_top::csic_bist_start_reg::CSIC_BIST_START_REG_SPEC
• csic::csic_top::csic_bist_start_reg::R
• csic::csic_top::csic_bist_start_reg::W
• csic::csic_top::csic_dma0_input_sel_reg::CSIC_DMA0_INPUT_SEL_REG_SPEC
• csic::csic_top::csic_dma0_input_sel_reg::R
• csic::csic_top::csic_dma0_input_sel_reg::W
• csic::csic_top::csic_dma1_input_sel_reg::CSIC_DMA1_INPUT_SEL_REG_SPEC
• csic::csic_top::csic_dma1_input_sel_reg::R
• csic::csic_top::csic_dma1_input_sel_reg::W
• csic::csic_top::csic_mbus_req_max_reg::CSIC_MBUS_REQ_MAX_REG_SPEC
• csic::csic_top::csic_mbus_req_max_reg::R
• csic::csic_top::csic_mbus_req_max_reg::W
• csic::csic_top::csic_mulf_int_reg::CSIC_MULF_INT_REG_SPEC
• csic::csic_top::csic_mulf_int_reg::R
• csic::csic_top::csic_mulf_int_reg::W
• csic::csic_top::csic_mulf_mod_reg::CSIC_MULF_MOD_REG_SPEC
• csic::csic_top::csic_mulf_mod_reg::R
• csic::csic_top::csic_mulf_mod_reg::W
• csic::csic_top::csic_ptn_addr_reg::CSIC_PTN_ADDR_REG_SPEC
• csic::csic_top::csic_ptn_addr_reg::R
• csic::csic_top::csic_ptn_addr_reg::W
• csic::csic_top::csic_ptn_ctrl_reg::CSIC_PTN_CTRL_REG_SPEC
• csic::csic_top::csic_ptn_ctrl_reg::R
• csic::csic_top::csic_ptn_ctrl_reg::W
• csic::csic_top::csic_ptn_gen_en_reg::CSIC_PTN_GEN_EN_REG_SPEC
• csic::csic_top::csic_ptn_gen_en_reg::R
• csic::csic_top::csic_ptn_gen_en_reg::W
• csic::csic_top::csic_ptn_isp_size_reg::CSIC_PTN_ISP_SIZE_REG_SPEC
• csic::csic_top::csic_ptn_isp_size_reg::R
• csic::csic_top::csic_ptn_isp_size_reg::W
• csic::csic_top::csic_ptn_len_reg::CSIC_PTN_LEN_REG_SPEC
• csic::csic_top::csic_ptn_len_reg::R
• csic::csic_top::csic_ptn_len_reg::W
• csic::csic_top::csic_top_en_reg::CSIC_TOP_EN_REG_SPEC
• csic::csic_top::csic_top_en_reg::R
• csic::csic_top::csic_top_en_reg::W
• dmac::RegisterBlock
• dmac::dmac_auto_gate_reg::DMAC_AUTO_GATE_REG_SPEC
• dmac::dmac_auto_gate_reg::R
• dmac::dmac_auto_gate_reg::W
• dmac::dmac_bcnt_left_reg::DMAC_BCNT_LEFT_REG_SPEC
• dmac::dmac_bcnt_left_reg::R
• dmac::dmac_cfg_reg::DMAC_CFG_REG_SPEC
• dmac::dmac_cfg_reg::R
• dmac::dmac_cur_dest_reg::DMAC_CUR_DEST_REG_SPEC
• dmac::dmac_cur_dest_reg::R
• dmac::dmac_cur_src_reg::DMAC_CUR_SRC_REG_SPEC
• dmac::dmac_cur_src_reg::R
• dmac::dmac_desc_addr_reg::DMAC_DESC_ADDR_REG_SPEC
• dmac::dmac_desc_addr_reg::R
• dmac::dmac_desc_addr_reg::W
• dmac::dmac_en_reg::DMAC_EN_REG_SPEC
• dmac::dmac_en_reg::R
• dmac::dmac_en_reg::W
• dmac::dmac_fdesc_addr_reg::DMAC_FDESC_ADDR_REG_SPEC
• dmac::dmac_fdesc_addr_reg::R
• dmac::dmac_irq_en_reg0::DMAC_IRQ_EN_REG0_SPEC
• dmac::dmac_irq_en_reg0::R
• dmac::dmac_irq_en_reg0::W
• dmac::dmac_irq_en_reg1::DMAC_IRQ_EN_REG1_SPEC
• dmac::dmac_irq_en_reg1::R
• dmac::dmac_irq_en_reg1::W
• dmac::dmac_irq_pend_reg0::DMAC_IRQ_PEND_REG0_SPEC
• dmac::dmac_irq_pend_reg0::R
• dmac::dmac_irq_pend_reg0::W
• dmac::dmac_irq_pend_reg1::DMAC_IRQ_PEND_REG1_SPEC
• dmac::dmac_irq_pend_reg1::R
• dmac::dmac_irq_pend_reg1::W
• dmac::dmac_mode_reg::DMAC_MODE_REG_SPEC
• dmac::dmac_mode_reg::R
• dmac::dmac_mode_reg::W
• dmac::dmac_para_reg::DMAC_PARA_REG_SPEC
• dmac::dmac_para_reg::R
• dmac::dmac_pau_reg::DMAC_PAU_REG_SPEC
• dmac::dmac_pau_reg::R
• dmac::dmac_pau_reg::W
• dmac::dmac_pkg_num_reg::DMAC_PKG_NUM_REG_SPEC
• dmac::dmac_pkg_num_reg::R
• dmac::dmac_sta_reg::DMAC_STA_REG_SPEC
• dmac::dmac_sta_reg::R
• dmic::RegisterBlock
• dmic::data0_data1_vol_ctr::DATA0_DATA1_VOL_CTR_SPEC
• dmic::data0_data1_vol_ctr::R
• dmic::data0_data1_vol_ctr::W
• dmic::data2_data3_vol_ctr::DATA2_DATA3_VOL_CTR_SPEC
• dmic::data2_data3_vol_ctr::R
• dmic::data2_data3_vol_ctr::W
• dmic::dmic_ch_map::DMIC_CH_MAP_SPEC
• dmic::dmic_ch_map::R
• dmic::dmic_ch_map::W
• dmic::dmic_ch_num::DMIC_CH_NUM_SPEC
• dmic::dmic_ch_num::R
• dmic::dmic_ch_num::W
• dmic::dmic_cnt::DMIC_CNT_SPEC
• dmic::dmic_cnt::R
• dmic::dmic_cnt::W
• dmic::dmic_ctr::DMIC_CTR_SPEC
• dmic::dmic_ctr::R
• dmic::dmic_ctr::W
• dmic::dmic_data::DMIC_DATA_SPEC
• dmic::dmic_data::R
• dmic::dmic_data::W
• dmic::dmic_en::DMIC_EN_SPEC
• dmic::dmic_en::R
• dmic::dmic_en::W
• dmic::dmic_intc::DMIC_INTC_SPEC
• dmic::dmic_intc::R
• dmic::dmic_intc::W
• dmic::dmic_ints::DMIC_INTS_SPEC
• dmic::dmic_ints::R
• dmic::dmic_ints::W
• dmic::dmic_rxfifo_ctr::DMIC_RXFIFO_CTR_SPEC
• dmic::dmic_rxfifo_ctr::R
• dmic::dmic_rxfifo_ctr::W
• dmic::dmic_rxfifo_sta::DMIC_RXFIFO_STA_SPEC
• dmic::dmic_rxfifo_sta::R
• dmic::dmic_rxfifo_sta::W
• dmic::dmic_sr::DMIC_SR_SPEC
• dmic::dmic_sr::R
• dmic::dmic_sr::W
• dmic::hpf_coef_reg::HPF_COEF_REG_SPEC
• dmic::hpf_coef_reg::R
• dmic::hpf_coef_reg::W
• dmic::hpf_en_ctr::HPF_EN_CTR_SPEC
• dmic::hpf_en_ctr::R
• dmic::hpf_en_ctr::W
• dmic::hpf_gain_reg::HPF_GAIN_REG_SPEC
• dmic::hpf_gain_reg::R
• dmic::hpf_gain_reg::W
• dsp_msgbox::MSGBOX
• dsp_msgbox::RegisterBlock
• dsp_msgbox::msgbox::msgbox_debug_reg::MSGBOX_DEBUG_REG_SPEC
• dsp_msgbox::msgbox::msgbox_debug_reg::R
• dsp_msgbox::msgbox::msgbox_debug_reg::W
• dsp_msgbox::msgbox::msgbox_fifo_status_reg::MSGBOX_FIFO_STATUS_REG_SPEC
• dsp_msgbox::msgbox::msgbox_fifo_status_reg::R
• dsp_msgbox::msgbox::msgbox_msg_reg::MSGBOX_MSG_REG_SPEC
• dsp_msgbox::msgbox::msgbox_msg_reg::R
• dsp_msgbox::msgbox::msgbox_msg_reg::W
• dsp_msgbox::msgbox::msgbox_msg_status_reg::MSGBOX_MSG_STATUS_REG_SPEC
• dsp_msgbox::msgbox::msgbox_msg_status_reg::R
• dsp_msgbox::msgbox::msgbox_rd_irq_en_reg::MSGBOX_RD_IRQ_EN_REG_SPEC
• dsp_msgbox::msgbox::msgbox_rd_irq_en_reg::R
• dsp_msgbox::msgbox::msgbox_rd_irq_en_reg::W
• dsp_msgbox::msgbox::msgbox_rd_irq_status_reg::MSGBOX_RD_IRQ_STATUS_REG_SPEC
• dsp_msgbox::msgbox::msgbox_rd_irq_status_reg::R
• dsp_msgbox::msgbox::msgbox_rd_irq_status_reg::W
• dsp_msgbox::msgbox::msgbox_wr_int_threshold_reg::MSGBOX_WR_INT_THRESHOLD_REG_SPEC
• dsp_msgbox::msgbox::msgbox_wr_int_threshold_reg::R
• dsp_msgbox::msgbox::msgbox_wr_int_threshold_reg::W
• dsp_msgbox::msgbox::msgbox_wr_irq_en_reg::MSGBOX_WR_IRQ_EN_REG_SPEC
• dsp_msgbox::msgbox::msgbox_wr_irq_en_reg::R
• dsp_msgbox::msgbox::msgbox_wr_irq_en_reg::W
• dsp_msgbox::msgbox::msgbox_wr_irq_status_reg::MSGBOX_WR_IRQ_STATUS_REG_SPEC
• dsp_msgbox::msgbox::msgbox_wr_irq_status_reg::R
• dsp_msgbox::msgbox::msgbox_wr_irq_status_reg::W
• emac::RegisterBlock
• emac::emac_addr_high0::EMAC_ADDR_HIGH0_SPEC
• emac::emac_addr_high0::R
• emac::emac_addr_high0::W
• emac::emac_addr_high::EMAC_ADDR_HIGH_SPEC
• emac::emac_addr_high::R
• emac::emac_addr_high::W
• emac::emac_addr_low::EMAC_ADDR_LOW_SPEC
• emac::emac_addr_low::R
• emac::emac_addr_low::W
• emac::emac_basic_ctl0::EMAC_BASIC_CTL0_SPEC
• emac::emac_basic_ctl0::R
• emac::emac_basic_ctl0::W
• emac::emac_basic_ctl1::EMAC_BASIC_CTL1_SPEC
• emac::emac_basic_ctl1::R
• emac::emac_basic_ctl1::W
• emac::emac_int_en::EMAC_INT_EN_SPEC
• emac::emac_int_en::R
• emac::emac_int_en::W
• emac::emac_int_sta::EMAC_INT_STA_SPEC
• emac::emac_int_sta::R
• emac::emac_int_sta::W
• emac::emac_mii_cmd::EMAC_MII_CMD_SPEC
• emac::emac_mii_cmd::R
• emac::emac_mii_cmd::W
• emac::emac_mii_data::EMAC_MII_DATA_SPEC
• emac::emac_mii_data::R
• emac::emac_mii_data::W
• emac::emac_rgmii_sta::EMAC_RGMII_STA_SPEC
• emac::emac_rgmii_sta::R
• emac::emac_rgmii_sta::W
• emac::emac_rx_ctl0::EMAC_RX_CTL0_SPEC
• emac::emac_rx_ctl0::R
• emac::emac_rx_ctl0::W
• emac::emac_rx_ctl1::EMAC_RX_CTL1_SPEC
• emac::emac_rx_ctl1::R
• emac::emac_rx_ctl1::W
• emac::emac_rx_cur_buf::EMAC_RX_CUR_BUF_SPEC
• emac::emac_rx_cur_buf::R
• emac::emac_rx_cur_desc::EMAC_RX_CUR_DESC_SPEC
• emac::emac_rx_cur_desc::R
• emac::emac_rx_dma_desc_list::EMAC_RX_DMA_DESC_LIST_SPEC
• emac::emac_rx_dma_desc_list::R
• emac::emac_rx_dma_desc_list::W
• emac::emac_rx_dma_sta::EMAC_RX_DMA_STA_SPEC
• emac::emac_rx_dma_sta::R
• emac::emac_rx_frm_flt::EMAC_RX_FRM_FLT_SPEC
• emac::emac_rx_frm_flt::R
• emac::emac_rx_frm_flt::W
• emac::emac_rx_hash0::EMAC_RX_HASH0_SPEC
• emac::emac_rx_hash0::R
• emac::emac_rx_hash0::W
• emac::emac_rx_hash1::EMAC_RX_HASH1_SPEC
• emac::emac_rx_hash1::R
• emac::emac_rx_hash1::W
• emac::emac_tx_ctl0::EMAC_TX_CTL0_SPEC
• emac::emac_tx_ctl0::R
• emac::emac_tx_ctl0::W
• emac::emac_tx_ctl1::EMAC_TX_CTL1_SPEC
• emac::emac_tx_ctl1::R
• emac::emac_tx_ctl1::W
• emac::emac_tx_cur_buf::EMAC_TX_CUR_BUF_SPEC
• emac::emac_tx_cur_buf::R
• emac::emac_tx_cur_desc::EMAC_TX_CUR_DESC_SPEC
• emac::emac_tx_cur_desc::R
• emac::emac_tx_dma_desc_list::EMAC_TX_DMA_DESC_LIST_SPEC
• emac::emac_tx_dma_desc_list::R
• emac::emac_tx_dma_desc_list::W
• emac::emac_tx_dma_sta::EMAC_TX_DMA_STA_SPEC
• emac::emac_tx_dma_sta::R
• emac::emac_tx_flow_ctl::EMAC_TX_FLOW_CTL_SPEC
• emac::emac_tx_flow_ctl::R
• emac::emac_tx_flow_ctl::W
• generic::ArrayProxy
• generic::R
• generic::Reg
• generic::W
• gpadc::RegisterBlock
• gpadc::gp_cdata::GP_CDATA_SPEC
• gpadc::gp_cdata::R
• gpadc::gp_cdata::W
• gpadc::gp_ch0_cmp_data::GP_CH0_CMP_DATA_SPEC
• gpadc::gp_ch0_cmp_data::R
• gpadc::gp_ch0_cmp_data::W
• gpadc::gp_ch0_data::GP_CH0_DATA_SPEC
• gpadc::gp_ch0_data::R
• gpadc::gp_ch0_data::W
• gpadc::gp_ch1_cmp_data::GP_CH1_CMP_DATA_SPEC
• gpadc::gp_ch1_cmp_data::R
• gpadc::gp_ch1_cmp_data::W
• gpadc::gp_ch1_data::GP_CH1_DATA_SPEC
• gpadc::gp_ch1_data::R
• gpadc::gp_ch1_data::W
• gpadc::gp_cs_en::GP_CS_EN_SPEC
• gpadc::gp_cs_en::R
• gpadc::gp_cs_en::W
• gpadc::gp_ctrl::GP_CTRL_SPEC
• gpadc::gp_ctrl::R
• gpadc::gp_ctrl::W
• gpadc::gp_data_intc::GP_DATA_INTC_SPEC
• gpadc::gp_data_intc::R
• gpadc::gp_data_intc::W
• gpadc::gp_data_ints::GP_DATA_INTS_SPEC
• gpadc::gp_data_ints::R
• gpadc::gp_data_ints::W
• gpadc::gp_datah_intc::GP_DATAH_INTC_SPEC
• gpadc::gp_datah_intc::R
• gpadc::gp_datah_intc::W
• gpadc::gp_datah_ints::GP_DATAH_INTS_SPEC
• gpadc::gp_datah_ints::R
• gpadc::gp_datah_ints::W
• gpadc::gp_datal_intc::GP_DATAL_INTC_SPEC
• gpadc::gp_datal_intc::R
• gpadc::gp_datal_intc::W
• gpadc::gp_datal_ints::GP_DATAL_INTS_SPEC
• gpadc::gp_datal_ints::R
• gpadc::gp_datal_ints::W
• gpadc::gp_fifo_data::GP_FIFO_DATA_SPEC
• gpadc::gp_fifo_data::R
• gpadc::gp_fifo_data::W
• gpadc::gp_fifo_intc::GP_FIFO_INTC_SPEC
• gpadc::gp_fifo_intc::R
• gpadc::gp_fifo_intc::W
• gpadc::gp_fifo_ints::GP_FIFO_INTS_SPEC
• gpadc::gp_fifo_ints::R
• gpadc::gp_fifo_ints::W
• gpadc::gp_sr_con::GP_SR_CON_SPEC
• gpadc::gp_sr_con::R
• gpadc::gp_sr_con::W
• gpio::RegisterBlock
• gpio::pb_cfg0::PB_CFG0_SPEC
• gpio::pb_cfg0::R
• gpio::pb_cfg0::W
• gpio::pb_cfg1::PB_CFG1_SPEC
• gpio::pb_cfg1::R
• gpio::pb_cfg1::W
• gpio::pb_dat::PB_DAT_SPEC
• gpio::pb_dat::R
• gpio::pb_dat::W
• gpio::pb_drv0::PB_DRV0_SPEC
• gpio::pb_drv0::R
• gpio::pb_drv0::W
• gpio::pb_drv1::PB_DRV1_SPEC
• gpio::pb_drv1::R
• gpio::pb_drv1::W
• gpio::pb_eint_cfg0::PB_EINT_CFG0_SPEC
• gpio::pb_eint_cfg0::R
• gpio::pb_eint_cfg0::W
• gpio::pb_eint_cfg1::PB_EINT_CFG1_SPEC
• gpio::pb_eint_cfg1::R
• gpio::pb_eint_cfg1::W
• gpio::pb_eint_ctl::PB_EINT_CTL_SPEC
• gpio::pb_eint_ctl::R
• gpio::pb_eint_ctl::W
• gpio::pb_eint_deb::PB_EINT_DEB_SPEC
• gpio::pb_eint_deb::R
• gpio::pb_eint_deb::W
• gpio::pb_eint_status::PB_EINT_STATUS_SPEC
• gpio::pb_eint_status::R
• gpio::pb_eint_status::W
• gpio::pb_pull0::PB_PULL0_SPEC
• gpio::pb_pull0::R
• gpio::pb_pull0::W
• gpio::pc_cfg0::PC_CFG0_SPEC
• gpio::pc_cfg0::R
• gpio::pc_cfg0::W
• gpio::pc_dat::PC_DAT_SPEC
• gpio::pc_dat::R
• gpio::pc_dat::W
• gpio::pc_drv0::PC_DRV0_SPEC
• gpio::pc_drv0::R
• gpio::pc_drv0::W
• gpio::pc_eint_cfg0::PC_EINT_CFG0_SPEC
• gpio::pc_eint_cfg0::R
• gpio::pc_eint_cfg0::W
• gpio::pc_eint_ctl::PC_EINT_CTL_SPEC
• gpio::pc_eint_ctl::R
• gpio::pc_eint_ctl::W
• gpio::pc_eint_deb::PC_EINT_DEB_SPEC
• gpio::pc_eint_deb::R
• gpio::pc_eint_deb::W
• gpio::pc_eint_status::PC_EINT_STATUS_SPEC
• gpio::pc_eint_status::R
• gpio::pc_eint_status::W
• gpio::pc_pull0::PC_PULL0_SPEC
• gpio::pc_pull0::R
• gpio::pc_pull0::W
• gpio::pd_cfg0::PD_CFG0_SPEC
• gpio::pd_cfg0::R
• gpio::pd_cfg0::W
• gpio::pd_cfg1::PD_CFG1_SPEC
• gpio::pd_cfg1::R
• gpio::pd_cfg1::W
• gpio::pd_cfg2::PD_CFG2_SPEC
• gpio::pd_cfg2::R
• gpio::pd_cfg2::W
• gpio::pd_dat::PD_DAT_SPEC
• gpio::pd_dat::R
• gpio::pd_dat::W
• gpio::pd_drv0::PD_DRV0_SPEC
• gpio::pd_drv0::R
• gpio::pd_drv0::W
• gpio::pd_drv1::PD_DRV1_SPEC
• gpio::pd_drv1::R
• gpio::pd_drv1::W
• gpio::pd_drv2::PD_DRV2_SPEC
• gpio::pd_drv2::R
• gpio::pd_drv2::W
• gpio::pd_eint_cfg0::PD_EINT_CFG0_SPEC
• gpio::pd_eint_cfg0::R
• gpio::pd_eint_cfg0::W
• gpio::pd_eint_cfg1::PD_EINT_CFG1_SPEC
• gpio::pd_eint_cfg1::R
• gpio::pd_eint_cfg1::W
• gpio::pd_eint_cfg2::PD_EINT_CFG2_SPEC
• gpio::pd_eint_cfg2::R
• gpio::pd_eint_cfg2::W
• gpio::pd_eint_ctl::PD_EINT_CTL_SPEC
• gpio::pd_eint_ctl::R
• gpio::pd_eint_ctl::W
• gpio::pd_eint_deb::PD_EINT_DEB_SPEC
• gpio::pd_eint_deb::R
• gpio::pd_eint_deb::W
• gpio::pd_eint_status::PD_EINT_STATUS_SPEC
• gpio::pd_eint_status::R
• gpio::pd_eint_status::W
• gpio::pd_pull0::PD_PULL0_SPEC
• gpio::pd_pull0::R
• gpio::pd_pull0::W
• gpio::pd_pull1::PD_PULL1_SPEC
• gpio::pd_pull1::R
• gpio::pd_pull1::W
• gpio::pe_cfg0::PE_CFG0_SPEC
• gpio::pe_cfg0::R
• gpio::pe_cfg0::W
• gpio::pe_cfg1::PE_CFG1_SPEC
• gpio::pe_cfg1::R
• gpio::pe_cfg1::W
• gpio::pe_cfg2::PE_CFG2_SPEC
• gpio::pe_cfg2::R
• gpio::pe_cfg2::W
• gpio::pe_dat::PE_DAT_SPEC
• gpio::pe_dat::R
• gpio::pe_dat::W
• gpio::pe_drv0::PE_DRV0_SPEC
• gpio::pe_drv0::R
• gpio::pe_drv0::W
• gpio::pe_drv1::PE_DRV1_SPEC
• gpio::pe_drv1::R
• gpio::pe_drv1::W
• gpio::pe_drv2::PE_DRV2_SPEC
• gpio::pe_drv2::R
• gpio::pe_drv2::W
• gpio::pe_eint_cfg0::PE_EINT_CFG0_SPEC
• gpio::pe_eint_cfg0::R
• gpio::pe_eint_cfg0::W
• gpio::pe_eint_cfg1::PE_EINT_CFG1_SPEC
• gpio::pe_eint_cfg1::R
• gpio::pe_eint_cfg1::W
• gpio::pe_eint_cfg2::PE_EINT_CFG2_SPEC
• gpio::pe_eint_cfg2::R
• gpio::pe_eint_cfg2::W
• gpio::pe_eint_ctl::PE_EINT_CTL_SPEC
• gpio::pe_eint_ctl::R
• gpio::pe_eint_ctl::W
• gpio::pe_eint_deb::PE_EINT_DEB_SPEC
• gpio::pe_eint_deb::R
• gpio::pe_eint_deb::W
• gpio::pe_eint_status::PE_EINT_STATUS_SPEC
• gpio::pe_eint_status::R
• gpio::pe_eint_status::W
• gpio::pe_pull0::PE_PULL0_SPEC
• gpio::pe_pull0::R
• gpio::pe_pull0::W
• gpio::pe_pull1::PE_PULL1_SPEC
• gpio::pe_pull1::R
• gpio::pe_pull1::W
• gpio::pf_cfg0::PF_CFG0_SPEC
• gpio::pf_cfg0::R
• gpio::pf_cfg0::W
• gpio::pf_dat::PF_DAT_SPEC
• gpio::pf_dat::R
• gpio::pf_dat::W
• gpio::pf_drv0::PF_DRV0_SPEC
• gpio::pf_drv0::R
• gpio::pf_drv0::W
• gpio::pf_eint_cfg0::PF_EINT_CFG0_SPEC
• gpio::pf_eint_cfg0::R
• gpio::pf_eint_cfg0::W
• gpio::pf_eint_ctl::PF_EINT_CTL_SPEC
• gpio::pf_eint_ctl::R
• gpio::pf_eint_ctl::W
• gpio::pf_eint_deb::PF_EINT_DEB_SPEC
• gpio::pf_eint_deb::R
• gpio::pf_eint_deb::W
• gpio::pf_eint_status::PF_EINT_STATUS_SPEC
• gpio::pf_eint_status::R
• gpio::pf_eint_status::W
• gpio::pf_pull0::PF_PULL0_SPEC
• gpio::pf_pull0::R
• gpio::pf_pull0::W
• gpio::pg_cfg0::PG_CFG0_SPEC
• gpio::pg_cfg0::R
• gpio::pg_cfg0::W
• gpio::pg_cfg1::PG_CFG1_SPEC
• gpio::pg_cfg1::R
• gpio::pg_cfg1::W
• gpio::pg_cfg2::PG_CFG2_SPEC
• gpio::pg_cfg2::R
• gpio::pg_cfg2::W
• gpio::pg_dat::PG_DAT_SPEC
• gpio::pg_dat::R
• gpio::pg_dat::W
• gpio::pg_drv0::PG_DRV0_SPEC
• gpio::pg_drv0::R
• gpio::pg_drv0::W
• gpio::pg_drv1::PG_DRV1_SPEC
• gpio::pg_drv1::R
• gpio::pg_drv1::W
• gpio::pg_drv2::PG_DRV2_SPEC
• gpio::pg_drv2::R
• gpio::pg_drv2::W
• gpio::pg_eint_cfg0::PG_EINT_CFG0_SPEC
• gpio::pg_eint_cfg0::R
• gpio::pg_eint_cfg0::W
• gpio::pg_eint_cfg1::PG_EINT_CFG1_SPEC
• gpio::pg_eint_cfg1::R
• gpio::pg_eint_cfg1::W
• gpio::pg_eint_cfg2::PG_EINT_CFG2_SPEC
• gpio::pg_eint_cfg2::R
• gpio::pg_eint_cfg2::W
• gpio::pg_eint_ctl::PG_EINT_CTL_SPEC
• gpio::pg_eint_ctl::R
• gpio::pg_eint_ctl::W
• gpio::pg_eint_deb::PG_EINT_DEB_SPEC
• gpio::pg_eint_deb::R
• gpio::pg_eint_deb::W
• gpio::pg_eint_status::PG_EINT_STATUS_SPEC
• gpio::pg_eint_status::R
• gpio::pg_eint_status::W
• gpio::pg_pull0::PG_PULL0_SPEC
• gpio::pg_pull0::R
• gpio::pg_pull0::W
• gpio::pg_pull1::PG_PULL1_SPEC
• gpio::pg_pull1::R
• gpio::pg_pull1::W
• gpio::pio_pow_mod_sel::PIO_POW_MOD_SEL_SPEC
• gpio::pio_pow_mod_sel::R
• gpio::pio_pow_mod_sel::W
• gpio::pio_pow_ms_ctl::PIO_POW_MS_CTL_SPEC
• gpio::pio_pow_ms_ctl::R
• gpio::pio_pow_ms_ctl::W
• gpio::pio_pow_val::PIO_POW_VAL_SPEC
• gpio::pio_pow_val::R
• gpio::pio_pow_vol_sel_ctl::PIO_POW_VOL_SEL_CTL_SPEC
• gpio::pio_pow_vol_sel_ctl::R
• gpio::pio_pow_vol_sel_ctl::W
• hstimer::RegisterBlock
• hstimer::hs_tmr_ctrl::HS_TMR_CTRL_SPEC
• hstimer::hs_tmr_ctrl::R
• hstimer::hs_tmr_ctrl::W
• hstimer::hs_tmr_curnt_hi::HS_TMR_CURNT_HI_SPEC
• hstimer::hs_tmr_curnt_hi::R
• hstimer::hs_tmr_curnt_hi::W
• hstimer::hs_tmr_curnt_lo::HS_TMR_CURNT_LO_SPEC
• hstimer::hs_tmr_curnt_lo::R
• hstimer::hs_tmr_curnt_lo::W
• hstimer::hs_tmr_intv_hi::HS_TMR_INTV_HI_SPEC
• hstimer::hs_tmr_intv_hi::R
• hstimer::hs_tmr_intv_hi::W
• hstimer::hs_tmr_intv_lo::HS_TMR_INTV_LO_SPEC
• hstimer::hs_tmr_intv_lo::R
• hstimer::hs_tmr_intv_lo::W
• hstimer::hs_tmr_irq_en::HS_TMR_IRQ_EN_SPEC
• hstimer::hs_tmr_irq_en::R
• hstimer::hs_tmr_irq_en::W
• hstimer::hs_tmr_irq_stas::HS_TMR_IRQ_STAS_SPEC
• hstimer::hs_tmr_irq_stas::R
• hstimer::hs_tmr_irq_stas::W
• i2s_pcm::RegisterBlock
• i2s_pcm::asrccfg::ASRCCFG_SPEC
• i2s_pcm::asrccfg::R
• i2s_pcm::asrccfg::W
• i2s_pcm::asrcfifostat::ASRCFIFOSTAT_SPEC
• i2s_pcm::asrcfifostat::R
• i2s_pcm::asrcfifostat::W
• i2s_pcm::asrcmancfg::ASRCMANCFG_SPEC
• i2s_pcm::asrcmancfg::R
• i2s_pcm::asrcmancfg::W
• i2s_pcm::asrcmbistcfg::ASRCMBISTCFG_SPEC
• i2s_pcm::asrcmbistcfg::R
• i2s_pcm::asrcmbistcfg::W
• i2s_pcm::asrcmbiststat::ASRCMBISTSTAT_SPEC
• i2s_pcm::asrcmbiststat::R
• i2s_pcm::asrcmbiststat::W
• i2s_pcm::asrcratiostat::ASRCRATIOSTAT_SPEC
• i2s_pcm::asrcratiostat::R
• i2s_pcm::asrcratiostat::W
• i2s_pcm::fsin_extcfg::FSINEXTCFG_SPEC
• i2s_pcm::fsin_extcfg::R
• i2s_pcm::fsin_extcfg::W
• i2s_pcm::fsout_cfg::FSOUTCFG_SPEC
• i2s_pcm::fsout_cfg::R
• i2s_pcm::fsout_cfg::W
• i2s_pcm::i2s_pcm_chcfg::I2S_PCM_CHCFG_SPEC
• i2s_pcm::i2s_pcm_chcfg::R
• i2s_pcm::i2s_pcm_chcfg::W
• i2s_pcm::i2s_pcm_clkd::I2S_PCM_CLKD_SPEC
• i2s_pcm::i2s_pcm_clkd::R
• i2s_pcm::i2s_pcm_clkd::W
• i2s_pcm::i2s_pcm_ctl::I2S_PCM_CTL_SPEC
• i2s_pcm::i2s_pcm_ctl::R
• i2s_pcm::i2s_pcm_ctl::W
• i2s_pcm::i2s_pcm_fctl::I2S_PCM_FCTL_SPEC
• i2s_pcm::i2s_pcm_fctl::R
• i2s_pcm::i2s_pcm_fctl::W
• i2s_pcm::i2s_pcm_fmt0::I2S_PCM_FMT0_SPEC
• i2s_pcm::i2s_pcm_fmt0::R
• i2s_pcm::i2s_pcm_fmt0::W
• i2s_pcm::i2s_pcm_fmt1::I2S_PCM_FMT1_SPEC
• i2s_pcm::i2s_pcm_fmt1::R
• i2s_pcm::i2s_pcm_fmt1::W
• i2s_pcm::i2s_pcm_fsta::I2S_PCM_FSTA_SPEC
• i2s_pcm::i2s_pcm_fsta::R
• i2s_pcm::i2s_pcm_fsta::W
• i2s_pcm::i2s_pcm_int::I2S_PCM_INT_SPEC
• i2s_pcm::i2s_pcm_int::R
• i2s_pcm::i2s_pcm_int::W
• i2s_pcm::i2s_pcm_ista::I2S_PCM_ISTA_SPEC
• i2s_pcm::i2s_pcm_ista::R
• i2s_pcm::i2s_pcm_ista::W
• i2s_pcm::i2s_pcm_rxchmap0::I2S_PCM_RXCHMAP0_SPEC
• i2s_pcm::i2s_pcm_rxchmap0::R
• i2s_pcm::i2s_pcm_rxchmap0::W
• i2s_pcm::i2s_pcm_rxchmap1::I2S_PCM_RXCHMAP1_SPEC
• i2s_pcm::i2s_pcm_rxchmap1::R
• i2s_pcm::i2s_pcm_rxchmap1::W
• i2s_pcm::i2s_pcm_rxchmap2::I2S_PCM_RXCHMAP2_SPEC
• i2s_pcm::i2s_pcm_rxchmap2::R
• i2s_pcm::i2s_pcm_rxchmap2::W
• i2s_pcm::i2s_pcm_rxchmap3::I2S_PCM_RXCHMAP3_SPEC
• i2s_pcm::i2s_pcm_rxchmap3::R
• i2s_pcm::i2s_pcm_rxchmap3::W
• i2s_pcm::i2s_pcm_rxchsel::I2S_PCM_RXCHSEL_SPEC
• i2s_pcm::i2s_pcm_rxchsel::R
• i2s_pcm::i2s_pcm_rxchsel::W
• i2s_pcm::i2s_pcm_rxcnt::I2S_PCM_RXCNT_SPEC
• i2s_pcm::i2s_pcm_rxcnt::R
• i2s_pcm::i2s_pcm_rxcnt::W
• i2s_pcm::i2s_pcm_rxfifo::I2S_PCM_RXFIFO_SPEC
• i2s_pcm::i2s_pcm_rxfifo::R
• i2s_pcm::i2s_pcm_rxfifo::W
• i2s_pcm::i2s_pcm_tx0chmap0::I2S_PCM_TX0CHMAP0_SPEC
• i2s_pcm::i2s_pcm_tx0chmap0::R
• i2s_pcm::i2s_pcm_tx0chmap0::W
• i2s_pcm::i2s_pcm_tx0chmap1::I2S_PCM_TX0CHMAP1_SPEC
• i2s_pcm::i2s_pcm_tx0chmap1::R
• i2s_pcm::i2s_pcm_tx0chmap1::W
• i2s_pcm::i2s_pcm_tx0chsel::I2S_PCM_TX0CHSEL_SPEC
• i2s_pcm::i2s_pcm_tx0chsel::R
• i2s_pcm::i2s_pcm_tx0chsel::W
• i2s_pcm::i2s_pcm_tx1chmap0::I2S_PCM_TX1CHMAP0_SPEC
• i2s_pcm::i2s_pcm_tx1chmap0::R
• i2s_pcm::i2s_pcm_tx1chmap0::W
• i2s_pcm::i2s_pcm_tx1chmap1::I2S_PCM_TX1CHMAP1_SPEC
• i2s_pcm::i2s_pcm_tx1chmap1::R
• i2s_pcm::i2s_pcm_tx1chmap1::W
• i2s_pcm::i2s_pcm_tx1chsel::I2S_PCM_TX1CHSEL_SPEC
• i2s_pcm::i2s_pcm_tx1chsel::R
• i2s_pcm::i2s_pcm_tx1chsel::W
• i2s_pcm::i2s_pcm_tx2chmap0::I2S_PCM_TX2CHMAP0_SPEC
• i2s_pcm::i2s_pcm_tx2chmap0::R
• i2s_pcm::i2s_pcm_tx2chmap0::W
• i2s_pcm::i2s_pcm_tx2chmap1::I2S_PCM_TX2CHMAP1_SPEC
• i2s_pcm::i2s_pcm_tx2chmap1::R
• i2s_pcm::i2s_pcm_tx2chmap1::W
• i2s_pcm::i2s_pcm_tx2chsel::I2S_PCM_TX2CHSEL_SPEC
• i2s_pcm::i2s_pcm_tx2chsel::R
• i2s_pcm::i2s_pcm_tx2chsel::W
• i2s_pcm::i2s_pcm_tx3chmap0::I2S_PCM_TX3CHMAP0_SPEC
• i2s_pcm::i2s_pcm_tx3chmap0::R
• i2s_pcm::i2s_pcm_tx3chmap0::W
• i2s_pcm::i2s_pcm_tx3chmap1::I2S_PCM_TX3CHMAP1_SPEC
• i2s_pcm::i2s_pcm_tx3chmap1::R
• i2s_pcm::i2s_pcm_tx3chmap1::W
• i2s_pcm::i2s_pcm_tx3chsel::I2S_PCM_TX3CHSEL_SPEC
• i2s_pcm::i2s_pcm_tx3chsel::R
• i2s_pcm::i2s_pcm_tx3chsel::W
• i2s_pcm::i2s_pcm_txcnt::I2S_PCM_TXCNT_SPEC
• i2s_pcm::i2s_pcm_txcnt::R
• i2s_pcm::i2s_pcm_txcnt::W
• i2s_pcm::i2s_pcm_txfifo::I2S_PCM_TXFIFO_SPEC
• i2s_pcm::i2s_pcm_txfifo::R
• i2s_pcm::i2s_pcm_txfifo::W
• i2s_pcm::mclkcfg::MCLKCFG_SPEC
• i2s_pcm::mclkcfg::R
• i2s_pcm::mclkcfg::W
• iommu::RegisterBlock
• iommu::iommu_4kb_bdy_prt_ctrl_reg::IOMMU_4KB_BDY_PRT_CTRL_REG_SPEC
• iommu::iommu_4kb_bdy_prt_ctrl_reg::R
• iommu::iommu_4kb_bdy_prt_ctrl_reg::W
• iommu::iommu_auto_gating_reg::IOMMU_AUTO_GATING_REG_SPEC
• iommu::iommu_auto_gating_reg::R
• iommu::iommu_auto_gating_reg::W
• iommu::iommu_bypass_reg::IOMMU_BYPASS_REG_SPEC
• iommu::iommu_bypass_reg::R
• iommu::iommu_bypass_reg::W
• iommu::iommu_dm_aut_ctrl0_reg::IOMMU_DM_AUT_CTRL0_REG_SPEC
• iommu::iommu_dm_aut_ctrl0_reg::R
• iommu::iommu_dm_aut_ctrl0_reg::W
• iommu::iommu_dm_aut_ctrl1_reg::IOMMU_DM_AUT_CTRL1_REG_SPEC
• iommu::iommu_dm_aut_ctrl1_reg::R
• iommu::iommu_dm_aut_ctrl1_reg::W
• iommu::iommu_dm_aut_ctrl2_reg::IOMMU_DM_AUT_CTRL2_REG_SPEC
• iommu::iommu_dm_aut_ctrl2_reg::R
• iommu::iommu_dm_aut_ctrl2_reg::W
• iommu::iommu_dm_aut_ctrl3_reg::IOMMU_DM_AUT_CTRL3_REG_SPEC
• iommu::iommu_dm_aut_ctrl3_reg::R
• iommu::iommu_dm_aut_ctrl3_reg::W
• iommu::iommu_dm_aut_ctrl4_reg::IOMMU_DM_AUT_CTRL4_REG_SPEC
• iommu::iommu_dm_aut_ctrl4_reg::R
• iommu::iommu_dm_aut_ctrl4_reg::W
• iommu::iommu_dm_aut_ctrl5_reg::IOMMU_DM_AUT_CTRL5_REG_SPEC
• iommu::iommu_dm_aut_ctrl5_reg::R
• iommu::iommu_dm_aut_ctrl5_reg::W
• iommu::iommu_dm_aut_ctrl6_reg::IOMMU_DM_AUT_CTRL6_REG_SPEC
• iommu::iommu_dm_aut_ctrl6_reg::R
• iommu::iommu_dm_aut_ctrl6_reg::W
• iommu::iommu_dm_aut_ctrl7_reg::IOMMU_DM_AUT_CTRL7_REG_SPEC
• iommu::iommu_dm_aut_ctrl7_reg::R
• iommu::iommu_dm_aut_ctrl7_reg::W
• iommu::iommu_dm_aut_ovwt_reg::IOMMU_DM_AUT_OVWT_REG_SPEC
• iommu::iommu_dm_aut_ovwt_reg::R
• iommu::iommu_dm_aut_ovwt_reg::W
• iommu::iommu_enable_reg::IOMMU_ENABLE_REG_SPEC
• iommu::iommu_enable_reg::R
• iommu::iommu_enable_reg::W
• iommu::iommu_int_clr_reg::IOMMU_INT_CLR_REG_SPEC
• iommu::iommu_int_clr_reg::R
• iommu::iommu_int_clr_reg::W
• iommu::iommu_int_enable_reg::IOMMU_INT_ENABLE_REG_SPEC
• iommu::iommu_int_enable_reg::R
• iommu::iommu_int_enable_reg::W
• iommu::iommu_int_err_addr0_reg::IOMMU_INT_ERR_ADDR0_REG_SPEC
• iommu::iommu_int_err_addr0_reg::R
• iommu::iommu_int_err_addr0_reg::W
• iommu::iommu_int_err_addr1_reg::IOMMU_INT_ERR_ADDR1_REG_SPEC
• iommu::iommu_int_err_addr1_reg::R
• iommu::iommu_int_err_addr1_reg::W
• iommu::iommu_int_err_addr2_reg::IOMMU_INT_ERR_ADDR2_REG_SPEC
• iommu::iommu_int_err_addr2_reg::R
• iommu::iommu_int_err_addr2_reg::W
• iommu::iommu_int_err_addr3_reg::IOMMU_INT_ERR_ADDR3_REG_SPEC
• iommu::iommu_int_err_addr3_reg::R
• iommu::iommu_int_err_addr3_reg::W
• iommu::iommu_int_err_addr4_reg::IOMMU_INT_ERR_ADDR4_REG_SPEC
• iommu::iommu_int_err_addr4_reg::R
• iommu::iommu_int_err_addr4_reg::W
• iommu::iommu_int_err_addr5_reg::IOMMU_INT_ERR_ADDR5_REG_SPEC
• iommu::iommu_int_err_addr5_reg::R
• iommu::iommu_int_err_addr5_reg::W
• iommu::iommu_int_err_addr6_reg::IOMMU_INT_ERR_ADDR6_REG_SPEC
• iommu::iommu_int_err_addr6_reg::R
• iommu::iommu_int_err_addr6_reg::W
• iommu::iommu_int_err_addr7_reg::IOMMU_INT_ERR_ADDR7_REG_SPEC
• iommu::iommu_int_err_addr7_reg::R
• iommu::iommu_int_err_addr7_reg::W
• iommu::iommu_int_err_addr8_reg::IOMMU_INT_ERR_ADDR8_REG_SPEC
• iommu::iommu_int_err_addr8_reg::R
• iommu::iommu_int_err_addr8_reg::W
• iommu::iommu_int_err_data0_reg::IOMMU_INT_ERR_DATA0_REG_SPEC
• iommu::iommu_int_err_data0_reg::R
• iommu::iommu_int_err_data0_reg::W
• iommu::iommu_int_err_data1_reg::IOMMU_INT_ERR_DATA1_REG_SPEC
• iommu::iommu_int_err_data1_reg::R
• iommu::iommu_int_err_data1_reg::W
• iommu::iommu_int_err_data2_reg::IOMMU_INT_ERR_DATA2_REG_SPEC
• iommu::iommu_int_err_data2_reg::R
• iommu::iommu_int_err_data2_reg::W
• iommu::iommu_int_err_data3_reg::IOMMU_INT_ERR_DATA3_REG_SPEC
• iommu::iommu_int_err_data3_reg::R
• iommu::iommu_int_err_data3_reg::W
• iommu::iommu_int_err_data4_reg::IOMMU_INT_ERR_DATA4_REG_SPEC
• iommu::iommu_int_err_data4_reg::R
• iommu::iommu_int_err_data4_reg::W
• iommu::iommu_int_err_data5_reg::IOMMU_INT_ERR_DATA5_REG_SPEC
• iommu::iommu_int_err_data5_reg::R
• iommu::iommu_int_err_data5_reg::W
• iommu::iommu_int_err_data6_reg::IOMMU_INT_ERR_DATA6_REG_SPEC
• iommu::iommu_int_err_data6_reg::R
• iommu::iommu_int_err_data6_reg::W
• iommu::iommu_int_err_data7_reg::IOMMU_INT_ERR_DATA7_REG_SPEC
• iommu::iommu_int_err_data7_reg::R
• iommu::iommu_int_err_data7_reg::W
• iommu::iommu_int_err_data8_reg::IOMMU_INT_ERR_DATA8_REG_SPEC
• iommu::iommu_int_err_data8_reg::R
• iommu::iommu_int_err_data8_reg::W
• iommu::iommu_int_sta_reg::IOMMU_INT_STA_REG_SPEC
• iommu::iommu_int_sta_reg::R
• iommu::iommu_int_sta_reg::W
• iommu::iommu_l1pg_int_reg::IOMMU_L1PG_INT_REG_SPEC
• iommu::iommu_l1pg_int_reg::R
• iommu::iommu_l1pg_int_reg::W
• iommu::iommu_l2pg_int_reg::IOMMU_L2PG_INT_REG_SPEC
• iommu::iommu_l2pg_int_reg::R
• iommu::iommu_l2pg_int_reg::W
• iommu::iommu_ooo_ctrl_reg::IOMMU_OOO_CTRL_REG_SPEC
• iommu::iommu_ooo_ctrl_reg::R
• iommu::iommu_ooo_ctrl_reg::W
• iommu::iommu_pc_ivld_addr_reg::IOMMU_PC_IVLD_ADDR_REG_SPEC
• iommu::iommu_pc_ivld_addr_reg::R
• iommu::iommu_pc_ivld_addr_reg::W
• iommu::iommu_pc_ivld_enable_reg::IOMMU_PC_IVLD_ENABLE_REG_SPEC
• iommu::iommu_pc_ivld_enable_reg::R
• iommu::iommu_pc_ivld_enable_reg::W
• iommu::iommu_pc_ivld_end_addr_reg::IOMMU_PC_IVLD_END_ADDR_REG_SPEC
• iommu::iommu_pc_ivld_end_addr_reg::R
• iommu::iommu_pc_ivld_end_addr_reg::W
• iommu::iommu_pc_ivld_mode_sel_reg::IOMMU_PC_IVLD_MODE_SEL_REG_SPEC
• iommu::iommu_pc_ivld_mode_sel_reg::R
• iommu::iommu_pc_ivld_mode_sel_reg::W
• iommu::iommu_pc_ivld_sta_addr_reg::IOMMU_PC_IVLD_STA_ADDR_REG_SPEC
• iommu::iommu_pc_ivld_sta_addr_reg::R
• iommu::iommu_pc_ivld_sta_addr_reg::W
• iommu::iommu_pmu_access_high0_reg::IOMMU_PMU_ACCESS_HIGH0_REG_SPEC
• iommu::iommu_pmu_access_high0_reg::R
• iommu::iommu_pmu_access_high0_reg::W
• iommu::iommu_pmu_access_high1_reg::IOMMU_PMU_ACCESS_HIGH1_REG_SPEC
• iommu::iommu_pmu_access_high1_reg::R
• iommu::iommu_pmu_access_high1_reg::W
• iommu::iommu_pmu_access_high2_reg::IOMMU_PMU_ACCESS_HIGH2_REG_SPEC
• iommu::iommu_pmu_access_high2_reg::R
• iommu::iommu_pmu_access_high2_reg::W
• iommu::iommu_pmu_access_high3_reg::IOMMU_PMU_ACCESS_HIGH3_REG_SPEC
• iommu::iommu_pmu_access_high3_reg::R
• iommu::iommu_pmu_access_high3_reg::W
• iommu::iommu_pmu_access_high4_reg::IOMMU_PMU_ACCESS_HIGH4_REG_SPEC
• iommu::iommu_pmu_access_high4_reg::R
• iommu::iommu_pmu_access_high4_reg::W
• iommu::iommu_pmu_access_high5_reg::IOMMU_PMU_ACCESS_HIGH5_REG_SPEC
• iommu::iommu_pmu_access_high5_reg::R
• iommu::iommu_pmu_access_high5_reg::W
• iommu::iommu_pmu_access_high6_reg::IOMMU_PMU_ACCESS_HIGH6_REG_SPEC
• iommu::iommu_pmu_access_high6_reg::R
• iommu::iommu_pmu_access_high6_reg::W
• iommu::iommu_pmu_access_high7_reg::IOMMU_PMU_ACCESS_HIGH7_REG_SPEC
• iommu::iommu_pmu_access_high7_reg::R
• iommu::iommu_pmu_access_high7_reg::W
• iommu::iommu_pmu_access_high8_reg::IOMMU_PMU_ACCESS_HIGH8_REG_SPEC
• iommu::iommu_pmu_access_high8_reg::R
• iommu::iommu_pmu_access_high8_reg::W
• iommu::iommu_pmu_access_low0_reg::IOMMU_PMU_ACCESS_LOW0_REG_SPEC
• iommu::iommu_pmu_access_low0_reg::R
• iommu::iommu_pmu_access_low0_reg::W
• iommu::iommu_pmu_access_low1_reg::IOMMU_PMU_ACCESS_LOW1_REG_SPEC
• iommu::iommu_pmu_access_low1_reg::R
• iommu::iommu_pmu_access_low1_reg::W
• iommu::iommu_pmu_access_low2_reg::IOMMU_PMU_ACCESS_LOW2_REG_SPEC
• iommu::iommu_pmu_access_low2_reg::R
• iommu::iommu_pmu_access_low2_reg::W
• iommu::iommu_pmu_access_low3_reg::IOMMU_PMU_ACCESS_LOW3_REG_SPEC
• iommu::iommu_pmu_access_low3_reg::R
• iommu::iommu_pmu_access_low3_reg::W
• iommu::iommu_pmu_access_low4_reg::IOMMU_PMU_ACCESS_LOW4_REG_SPEC
• iommu::iommu_pmu_access_low4_reg::R
• iommu::iommu_pmu_access_low4_reg::W
• iommu::iommu_pmu_access_low5_reg::IOMMU_PMU_ACCESS_LOW5_REG_SPEC
• iommu::iommu_pmu_access_low5_reg::R
• iommu::iommu_pmu_access_low5_reg::W
• iommu::iommu_pmu_access_low6_reg::IOMMU_PMU_ACCESS_LOW6_REG_SPEC
• iommu::iommu_pmu_access_low6_reg::R
• iommu::iommu_pmu_access_low6_reg::W
• iommu::iommu_pmu_access_low7_reg::IOMMU_PMU_ACCESS_LOW7_REG_SPEC
• iommu::iommu_pmu_access_low7_reg::R
• iommu::iommu_pmu_access_low7_reg::W
• iommu::iommu_pmu_access_low8_reg::IOMMU_PMU_ACCESS_LOW8_REG_SPEC
• iommu::iommu_pmu_access_low8_reg::R
• iommu::iommu_pmu_access_low8_reg::W
• iommu::iommu_pmu_clr_reg::IOMMU_PMU_CLR_REG_SPEC
• iommu::iommu_pmu_clr_reg::R
• iommu::iommu_pmu_clr_reg::W
• iommu::iommu_pmu_enable_reg::IOMMU_PMU_ENABLE_REG_SPEC
• iommu::iommu_pmu_enable_reg::R
• iommu::iommu_pmu_enable_reg::W
• iommu::iommu_pmu_hit_high0_reg::IOMMU_PMU_HIT_HIGH0_REG_SPEC
• iommu::iommu_pmu_hit_high0_reg::R
• iommu::iommu_pmu_hit_high0_reg::W
• iommu::iommu_pmu_hit_high1_reg::IOMMU_PMU_HIT_HIGH1_REG_SPEC
• iommu::iommu_pmu_hit_high1_reg::R
• iommu::iommu_pmu_hit_high1_reg::W
• iommu::iommu_pmu_hit_high2_reg::IOMMU_PMU_HIT_HIGH2_REG_SPEC
• iommu::iommu_pmu_hit_high2_reg::R
• iommu::iommu_pmu_hit_high2_reg::W
• iommu::iommu_pmu_hit_high3_reg::IOMMU_PMU_HIT_HIGH3_REG_SPEC
• iommu::iommu_pmu_hit_high3_reg::R
• iommu::iommu_pmu_hit_high3_reg::W
• iommu::iommu_pmu_hit_high4_reg::IOMMU_PMU_HIT_HIGH4_REG_SPEC
• iommu::iommu_pmu_hit_high4_reg::R
• iommu::iommu_pmu_hit_high4_reg::W
• iommu::iommu_pmu_hit_high5_reg::IOMMU_PMU_HIT_HIGH5_REG_SPEC
• iommu::iommu_pmu_hit_high5_reg::R
• iommu::iommu_pmu_hit_high5_reg::W
• iommu::iommu_pmu_hit_high6_reg::IOMMU_PMU_HIT_HIGH6_REG_SPEC
• iommu::iommu_pmu_hit_high6_reg::R
• iommu::iommu_pmu_hit_high6_reg::W
• iommu::iommu_pmu_hit_high7_reg::IOMMU_PMU_HIT_HIGH7_REG_SPEC
• iommu::iommu_pmu_hit_high7_reg::R
• iommu::iommu_pmu_hit_high7_reg::W
• iommu::iommu_pmu_hit_high8_reg::IOMMU_PMU_HIT_HIGH8_REG_SPEC
• iommu::iommu_pmu_hit_high8_reg::R
• iommu::iommu_pmu_hit_high8_reg::W
• iommu::iommu_pmu_hit_low0_reg::IOMMU_PMU_HIT_LOW0_REG_SPEC
• iommu::iommu_pmu_hit_low0_reg::R
• iommu::iommu_pmu_hit_low0_reg::W
• iommu::iommu_pmu_hit_low1_reg::IOMMU_PMU_HIT_LOW1_REG_SPEC
• iommu::iommu_pmu_hit_low1_reg::R
• iommu::iommu_pmu_hit_low1_reg::W
• iommu::iommu_pmu_hit_low2_reg::IOMMU_PMU_HIT_LOW2_REG_SPEC
• iommu::iommu_pmu_hit_low2_reg::R
• iommu::iommu_pmu_hit_low2_reg::W
• iommu::iommu_pmu_hit_low3_reg::IOMMU_PMU_HIT_LOW3_REG_SPEC
• iommu::iommu_pmu_hit_low3_reg::R
• iommu::iommu_pmu_hit_low3_reg::W
• iommu::iommu_pmu_hit_low4_reg::IOMMU_PMU_HIT_LOW4_REG_SPEC
• iommu::iommu_pmu_hit_low4_reg::R
• iommu::iommu_pmu_hit_low4_reg::W
• iommu::iommu_pmu_hit_low5_reg::IOMMU_PMU_HIT_LOW5_REG_SPEC
• iommu::iommu_pmu_hit_low5_reg::R
• iommu::iommu_pmu_hit_low5_reg::W
• iommu::iommu_pmu_hit_low6_reg::IOMMU_PMU_HIT_LOW6_REG_SPEC
• iommu::iommu_pmu_hit_low6_reg::R
• iommu::iommu_pmu_hit_low6_reg::W
• iommu::iommu_pmu_hit_low7_reg::IOMMU_PMU_HIT_LOW7_REG_SPEC
• iommu::iommu_pmu_hit_low7_reg::R
• iommu::iommu_pmu_hit_low7_reg::W
• iommu::iommu_pmu_hit_low8_reg::IOMMU_PMU_HIT_LOW8_REG_SPEC
• iommu::iommu_pmu_hit_low8_reg::R
• iommu::iommu_pmu_hit_low8_reg::W
• iommu::iommu_pmu_ml0_reg::IOMMU_PMU_ML0_REG_SPEC
• iommu::iommu_pmu_ml0_reg::R
• iommu::iommu_pmu_ml0_reg::W
• iommu::iommu_pmu_ml1_reg::IOMMU_PMU_ML1_REG_SPEC
• iommu::iommu_pmu_ml1_reg::R
• iommu::iommu_pmu_ml1_reg::W
• iommu::iommu_pmu_ml2_reg::IOMMU_PMU_ML2_REG_SPEC
• iommu::iommu_pmu_ml2_reg::R
• iommu::iommu_pmu_ml2_reg::W
• iommu::iommu_pmu_ml3_reg::IOMMU_PMU_ML3_REG_SPEC
• iommu::iommu_pmu_ml3_reg::R
• iommu::iommu_pmu_ml3_reg::W
• iommu::iommu_pmu_ml4_reg::IOMMU_PMU_ML4_REG_SPEC
• iommu::iommu_pmu_ml4_reg::R
• iommu::iommu_pmu_ml4_reg::W
• iommu::iommu_pmu_ml5_reg::IOMMU_PMU_ML5_REG_SPEC
• iommu::iommu_pmu_ml5_reg::R
• iommu::iommu_pmu_ml5_reg::W
• iommu::iommu_pmu_ml6_reg::IOMMU_PMU_ML6_REG_SPEC
• iommu::iommu_pmu_ml6_reg::R
• iommu::iommu_pmu_ml6_reg::W
• iommu::iommu_pmu_tl_high0_reg::IOMMU_PMU_TL_HIGH0_REG_SPEC
• iommu::iommu_pmu_tl_high0_reg::R
• iommu::iommu_pmu_tl_high0_reg::W
• iommu::iommu_pmu_tl_high1_reg::IOMMU_PMU_TL_HIGH1_REG_SPEC
• iommu::iommu_pmu_tl_high1_reg::R
• iommu::iommu_pmu_tl_high1_reg::W
• iommu::iommu_pmu_tl_high2_reg::IOMMU_PMU_TL_HIGH2_REG_SPEC
• iommu::iommu_pmu_tl_high2_reg::R
• iommu::iommu_pmu_tl_high2_reg::W
• iommu::iommu_pmu_tl_high3_reg::IOMMU_PMU_TL_HIGH3_REG_SPEC
• iommu::iommu_pmu_tl_high3_reg::R
• iommu::iommu_pmu_tl_high3_reg::W
• iommu::iommu_pmu_tl_high4_reg::IOMMU_PMU_TL_HIGH4_REG_SPEC
• iommu::iommu_pmu_tl_high4_reg::R
• iommu::iommu_pmu_tl_high4_reg::W
• iommu::iommu_pmu_tl_high5_reg::IOMMU_PMU_TL_HIGH5_REG_SPEC
• iommu::iommu_pmu_tl_high5_reg::R
• iommu::iommu_pmu_tl_high5_reg::W
• iommu::iommu_pmu_tl_high6_reg::IOMMU_PMU_TL_HIGH6_REG_SPEC
• iommu::iommu_pmu_tl_high6_reg::R
• iommu::iommu_pmu_tl_high6_reg::W
• iommu::iommu_pmu_tl_low0_reg::IOMMU_PMU_TL_LOW0_REG_SPEC
• iommu::iommu_pmu_tl_low0_reg::R
• iommu::iommu_pmu_tl_low0_reg::W
• iommu::iommu_pmu_tl_low1_reg::IOMMU_PMU_TL_LOW1_REG_SPEC
• iommu::iommu_pmu_tl_low1_reg::R
• iommu::iommu_pmu_tl_low1_reg::W
• iommu::iommu_pmu_tl_low2_reg::IOMMU_PMU_TL_LOW2_REG_SPEC
• iommu::iommu_pmu_tl_low2_reg::R
• iommu::iommu_pmu_tl_low2_reg::W
• iommu::iommu_pmu_tl_low3_reg::IOMMU_PMU_TL_LOW3_REG_SPEC
• iommu::iommu_pmu_tl_low3_reg::R
• iommu::iommu_pmu_tl_low3_reg::W
• iommu::iommu_pmu_tl_low4_reg::IOMMU_PMU_TL_LOW4_REG_SPEC
• iommu::iommu_pmu_tl_low4_reg::R
• iommu::iommu_pmu_tl_low4_reg::W
• iommu::iommu_pmu_tl_low5_reg::IOMMU_PMU_TL_LOW5_REG_SPEC
• iommu::iommu_pmu_tl_low5_reg::R
• iommu::iommu_pmu_tl_low5_reg::W
• iommu::iommu_pmu_tl_low6_reg::IOMMU_PMU_TL_LOW6_REG_SPEC
• iommu::iommu_pmu_tl_low6_reg::R
• iommu::iommu_pmu_tl_low6_reg::W
• iommu::iommu_reset_reg::IOMMU_RESET_REG_SPEC
• iommu::iommu_reset_reg::R
• iommu::iommu_reset_reg::W
• iommu::iommu_tlb_enable_reg::IOMMU_TLB_ENABLE_REG_SPEC
• iommu::iommu_tlb_enable_reg::R
• iommu::iommu_tlb_enable_reg::W
• iommu::iommu_tlb_flush_enable_reg::IOMMU_TLB_FLUSH_ENABLE_REG_SPEC
• iommu::iommu_tlb_flush_enable_reg::R
• iommu::iommu_tlb_flush_enable_reg::W
• iommu::iommu_tlb_ivld_addr_mask_reg::IOMMU_TLB_IVLD_ADDR_MASK_REG_SPEC
• iommu::iommu_tlb_ivld_addr_mask_reg::R
• iommu::iommu_tlb_ivld_addr_mask_reg::W
• iommu::iommu_tlb_ivld_addr_reg::IOMMU_TLB_IVLD_ADDR_REG_SPEC
• iommu::iommu_tlb_ivld_addr_reg::R
• iommu::iommu_tlb_ivld_addr_reg::W
• iommu::iommu_tlb_ivld_enable_reg::IOMMU_TLB_IVLD_ENABLE_REG_SPEC
• iommu::iommu_tlb_ivld_enable_reg::R
• iommu::iommu_tlb_ivld_enable_reg::W
• iommu::iommu_tlb_ivld_end_addr_reg::IOMMU_TLB_IVLD_END_ADDR_REG_SPEC
• iommu::iommu_tlb_ivld_end_addr_reg::R
• iommu::iommu_tlb_ivld_end_addr_reg::W
• iommu::iommu_tlb_ivld_mode_sel_reg::IOMMU_TLB_IVLD_MODE_SEL_REG_SPEC
• iommu::iommu_tlb_ivld_mode_sel_reg::R
• iommu::iommu_tlb_ivld_mode_sel_reg::W
• iommu::iommu_tlb_ivld_sta_addr_reg::IOMMU_TLB_IVLD_STA_ADDR_REG_SPEC
• iommu::iommu_tlb_ivld_sta_addr_reg::R
• iommu::iommu_tlb_ivld_sta_addr_reg::W
• iommu::iommu_tlb_prefetch_reg::IOMMU_TLB_PREFETCH_REG_SPEC
• iommu::iommu_tlb_prefetch_reg::R
• iommu::iommu_tlb_prefetch_reg::W
• iommu::iommu_ttb_reg::IOMMU_TTB_REG_SPEC
• iommu::iommu_ttb_reg::R
• iommu::iommu_ttb_reg::W
• iommu::iommu_va_config_reg::IOMMU_VA_CONFIG_REG_SPEC
• iommu::iommu_va_config_reg::R
• iommu::iommu_va_config_reg::W
• iommu::iommu_va_data_reg::IOMMU_VA_DATA_REG_SPEC
• iommu::iommu_va_data_reg::R
• iommu::iommu_va_data_reg::W
• iommu::iommu_va_reg::IOMMU_VA_REG_SPEC
• iommu::iommu_va_reg::R
• iommu::iommu_va_reg::W
• iommu::iommu_wbuf_ctrl_reg::IOMMU_WBUF_CTRL_REG_SPEC
• iommu::iommu_wbuf_ctrl_reg::R
• iommu::iommu_wbuf_ctrl_reg::W
• ledc::RegisterBlock
• ledc::led_reset_timing_ctrl::LED_RESET_TIMING_CTRL_SPEC
• ledc::led_reset_timing_ctrl::R
• ledc::led_reset_timing_ctrl::W
• ledc::led_t01_timing_ctrl::LED_T01_TIMING_CTRL_SPEC
• ledc::led_t01_timing_ctrl::R
• ledc::led_t01_timing_ctrl::W
• ledc::ledc_ctrl::LEDC_CTRL_SPEC
• ledc::ledc_ctrl::R
• ledc::ledc_ctrl::W
• ledc::ledc_data::LEDC_DATA_SPEC
• ledc::ledc_data::W
• ledc::ledc_data_finish_cnt::LEDC_DATA_FINISH_CNT_SPEC
• ledc::ledc_data_finish_cnt::R
• ledc::ledc_data_finish_cnt::W
• ledc::ledc_dma_ctrl::LEDC_DMA_CTRL_SPEC
• ledc::ledc_dma_ctrl::R
• ledc::ledc_dma_ctrl::W
• ledc::ledc_fifo_data::LEDC_FIFO_DATA_SPEC
• ledc::ledc_fifo_data::R
• ledc::ledc_int_ctrl::LEDC_INT_CTRL_SPEC
• ledc::ledc_int_ctrl::R
• ledc::ledc_int_ctrl::W
• ledc::ledc_int_sts::LEDC_INT_STS_SPEC
• ledc::ledc_int_sts::R
• ledc::ledc_int_sts::W
• ledc::ledc_wait_time0_ctrl::LEDC_WAIT_TIME0_CTRL_SPEC
• ledc::ledc_wait_time0_ctrl::R
• ledc::ledc_wait_time0_ctrl::W
• ledc::ledc_wait_time1_ctrl::LEDC_WAIT_TIME1_CTRL_SPEC
• ledc::ledc_wait_time1_ctrl::R
• ledc::ledc_wait_time1_ctrl::W
• lradc::RegisterBlock
• lradc::lradc_ctrl::LRADC_CTRL_SPEC
• lradc::lradc_ctrl::R
• lradc::lradc_ctrl::W
• lradc::lradc_data::LRADC_DATA_SPEC
• lradc::lradc_data::R
• lradc::lradc_intc::LRADC_INTC_SPEC
• lradc::lradc_intc::R
• lradc::lradc_intc::W
• lradc::lradc_ints::LRADC_INTS_SPEC
• lradc::lradc_ints::R
• lradc::lradc_ints::W
• owa::RegisterBlock
• owa::owa_exp_ctl::OWA_EXP_CTL_SPEC
• owa::owa_exp_ctl::R
• owa::owa_exp_ctl::W
• owa::owa_exp_dbg_0::OWA_EXP_DBG_0_SPEC
• owa::owa_exp_dbg_0::R
• owa::owa_exp_dbg_0::W
• owa::owa_exp_dbg_1::OWA_EXP_DBG_1_SPEC
• owa::owa_exp_dbg_1::R
• owa::owa_exp_dbg_1::W
• owa::owa_exp_info_0::OWA_EXP_INFO_0_SPEC
• owa::owa_exp_info_0::R
• owa::owa_exp_info_0::W
• owa::owa_exp_info_1::OWA_EXP_INFO_1_SPEC
• owa::owa_exp_info_1::R
• owa::owa_exp_info_1::W
• owa::owa_exp_ista::OWA_EXP_ISTA_SPEC
• owa::owa_exp_ista::R
• owa::owa_exp_ista::W
• owa::owa_fctl::OWA_FCTL_SPEC
• owa::owa_fctl::R
• owa::owa_fctl::W
• owa::owa_fsta::OWA_FSTA_SPEC
• owa::owa_fsta::R
• owa::owa_fsta::W
• owa::owa_gen_ctl::OWA_GEN_CTL_SPEC
• owa::owa_gen_ctl::R
• owa::owa_gen_ctl::W
• owa::owa_int::OWA_INT_SPEC
• owa::owa_int::R
• owa::owa_int::W
• owa::owa_ista::OWA_ISTA_SPEC
• owa::owa_ista::R
• owa::owa_ista::W
• owa::owa_rx_cfig::OWA_RX_CFIG_SPEC
• owa::owa_rx_cfig::R
• owa::owa_rx_cfig::W
• owa::owa_rx_cnt::OWA_RX_CNT_SPEC
• owa::owa_rx_cnt::R
• owa::owa_rx_cnt::W
• owa::owa_rxchsta0::OWA_RXCHSTA0_SPEC
• owa::owa_rxchsta0::R
• owa::owa_rxchsta0::W
• owa::owa_rxchsta1::OWA_RXCHSTA1_SPEC
• owa::owa_rxchsta1::R
• owa::owa_rxchsta1::W
• owa::owa_rxfifo::OWA_RXFIFO_SPEC
• owa::owa_rxfifo::R
• owa::owa_rxfifo::W
• owa::owa_tx_cfig::OWA_TX_CFIG_SPEC
• owa::owa_tx_cfig::R
• owa::owa_tx_cfig::W
• owa::owa_tx_chsta0::OWA_TX_CHSTA0_SPEC
• owa::owa_tx_chsta0::R
• owa::owa_tx_chsta0::W
• owa::owa_tx_chsta1::OWA_TX_CHSTA1_SPEC
• owa::owa_tx_chsta1::R
• owa::owa_tx_chsta1::W
• owa::owa_tx_cnt::OWA_TX_CNT_SPEC
• owa::owa_tx_cnt::R
• owa::owa_tx_cnt::W
• owa::owa_tx_fifo::OWA_TX_FIFO_SPEC
• owa::owa_tx_fifo::R
• owa::owa_tx_fifo::W
• plic::RegisterBlock
• plic::ctrl::CTRL_SPEC
• plic::ctrl::R
• plic::ctrl::W
• plic::ip::IP_SPEC
• plic::ip::R
• plic::ip::W
• plic::mclaim::MCLAIM_SPEC
• plic::mclaim::R
• plic::mclaim::W
• plic::mie::MIE_SPEC
• plic::mie::R
• plic::mie::W
• plic::mth::MTH_SPEC
• plic::mth::R
• plic::mth::W
• plic::prio::PRIO_SPEC
• plic::prio::R
• plic::prio::W
• plic::sclaim::R
• plic::sclaim::SCLAIM_SPEC
• plic::sclaim::W
• plic::sie::R
• plic::sie::SIE_SPEC
• plic::sie::W
• plic::sth::R
• plic::sth::STH_SPEC
• plic::sth::W
• pwm::RegisterBlock
• pwm::ccr::CCR_SPEC
• pwm::ccr::R
• pwm::ccr::W
• pwm::cer::CER_SPEC
• pwm::cer::R
• pwm::cer::W
• pwm::cflr::CFLR_SPEC
• pwm::cflr::R
• pwm::cier::CIER_SPEC
• pwm::cier::R
• pwm::cier::W
• pwm::cisr::CISR_SPEC
• pwm::cisr::R
• pwm::cisr::W
• pwm::crlr::CRLR_SPEC
• pwm::crlr::R
• pwm::pccr01::PCCR01_SPEC
• pwm::pccr01::R
• pwm::pccr01::W
• pwm::pccr23::PCCR23_SPEC
• pwm::pccr23::R
• pwm::pccr23::W
• pwm::pccr45::PCCR45_SPEC
• pwm::pccr45::R
• pwm::pccr45::W
• pwm::pccr67::PCCR67_SPEC
• pwm::pccr67::R
• pwm::pccr67::W
• pwm::pcgr::PCGR_SPEC
• pwm::pcgr::R
• pwm::pcgr::W
• pwm::pcntr::PCNTR_SPEC
• pwm::pcntr::R
• pwm::pcntr::W
• pwm::pcr::PCR_SPEC
• pwm::pcr::R
• pwm::pcr::W
• pwm::pdzcr01::PDZCR01_SPEC
• pwm::pdzcr01::R
• pwm::pdzcr01::W
• pwm::pdzcr23::PDZCR23_SPEC
• pwm::pdzcr23::R
• pwm::pdzcr23::W
• pwm::pdzcr45::PDZCR45_SPEC
• pwm::pdzcr45::R
• pwm::pdzcr45::W
• pwm::pdzcr67::PDZCR67_SPEC
• pwm::pdzcr67::R
• pwm::pdzcr67::W
• pwm::per::PER_SPEC
• pwm::per::R
• pwm::per::W
• pwm::pgr::PGR_SPEC
• pwm::pgr::R
• pwm::pgr::W
• pwm::pier::PIER_SPEC
• pwm::pier::R
• pwm::pier::W
• pwm::pisr::PISR_SPEC
• pwm::pisr::R
• pwm::pisr::W
• pwm::ppcntr::PPCNTR_SPEC
• pwm::ppcntr::R
• pwm::ppr::PPR_SPEC
• pwm::ppr::R
• pwm::ppr::W
• rtc::RegisterBlock
• rtc::_32k_fout_ctrl_gating_reg::R
• rtc::_32k_fout_ctrl_gating_reg::W
• rtc::_32k_fout_ctrl_gating_reg::_32K_FOUT_CTRL_GATING_REG_SPEC
• rtc::alarm0_cur_vlu_reg::ALARM0_CUR_VLU_REG_SPEC
• rtc::alarm0_cur_vlu_reg::R
• rtc::alarm0_cur_vlu_reg::W
• rtc::alarm0_day_set_reg::ALARM0_DAY_SET_REG_SPEC
• rtc::alarm0_day_set_reg::R
• rtc::alarm0_day_set_reg::W
• rtc::alarm0_enable_reg::ALARM0_ENABLE_REG_SPEC
• rtc::alarm0_enable_reg::R
• rtc::alarm0_enable_reg::W
• rtc::alarm0_irq_en::ALARM0_IRQ_EN_SPEC
• rtc::alarm0_irq_en::R
• rtc::alarm0_irq_en::W
• rtc::alarm0_irq_sta_reg::ALARM0_IRQ_STA_REG_SPEC
• rtc::alarm0_irq_sta_reg::R
• rtc::alarm0_irq_sta_reg::W
• rtc::alarm_config_reg::ALARM_CONFIG_REG_SPEC
• rtc::alarm_config_reg::R
• rtc::alarm_config_reg::W
• rtc::dcxo_ctrl_reg::DCXO_CTRL_REG_SPEC
• rtc::dcxo_ctrl_reg::R
• rtc::dcxo_ctrl_reg::W
• rtc::efuse_hv_pwrswt_ctrl_reg::EFUSE_HV_PWRSWT_CTRL_REG_SPEC
• rtc::efuse_hv_pwrswt_ctrl_reg::R
• rtc::efuse_hv_pwrswt_ctrl_reg::W
• rtc::fboot_info_reg0::FBOOT_INFO_REG0_SPEC
• rtc::fboot_info_reg0::R
• rtc::fboot_info_reg0::W
• rtc::fboot_info_reg1::FBOOT_INFO_REG1_SPEC
• rtc::fboot_info_reg1::R
• rtc::fboot_info_reg1::W
• rtc::gp_data_reg::GP_DATA_REG_SPEC
• rtc::gp_data_reg::R
• rtc::gp_data_reg::W
• rtc::ic_chara_reg::IC_CHARA_REG_SPEC
• rtc::ic_chara_reg::R
• rtc::ic_chara_reg::W
• rtc::intosc_clk_prescal_reg::INTOSC_CLK_PRESCAL_REG_SPEC
• rtc::intosc_clk_prescal_reg::R
• rtc::intosc_clk_prescal_reg::W
• rtc::losc_auto_swt_sta_reg::LOSC_AUTO_SWT_STA_REG_SPEC
• rtc::losc_auto_swt_sta_reg::R
• rtc::losc_auto_swt_sta_reg::W
• rtc::losc_ctrl_reg::LOSC_CTRL_REG_SPEC
• rtc::losc_ctrl_reg::R
• rtc::losc_ctrl_reg::W
• rtc::rtc_day_reg::R
• rtc::rtc_day_reg::RTC_DAY_REG_SPEC
• rtc::rtc_day_reg::W
• rtc::rtc_hh_mm_ss_reg::R
• rtc::rtc_hh_mm_ss_reg::RTC_HH_MM_SS_REG_SPEC
• rtc::rtc_hh_mm_ss_reg::W
• rtc::rtc_spi_clk_ctrl_reg::R
• rtc::rtc_spi_clk_ctrl_reg::RTC_SPI_CLK_CTRL_REG_SPEC
• rtc::rtc_spi_clk_ctrl_reg::W
• rtc::rtc_vio_reg::R
• rtc::rtc_vio_reg::RTC_VIO_REG_SPEC
• rtc::rtc_vio_reg::W
• rtc::vdd_off_gating_ctrl_reg::R
• rtc::vdd_off_gating_ctrl_reg::VDD_OFF_GATING_CTRL_REG_SPEC
• rtc::vdd_off_gating_ctrl_reg::W
• smhc::RegisterBlock
• smhc::emmc_ddr_sbit_det::EMMC_DDR_SBIT_DET_SPEC
• smhc::emmc_ddr_sbit_det::R
• smhc::emmc_ddr_sbit_det::W
• smhc::smhc_a12a::R
• smhc::smhc_a12a::SMHC_A12A_SPEC
• smhc::smhc_a12a::W
• smhc::smhc_a23a::R
• smhc::smhc_a23a::SMHC_A23A_SPEC
• smhc::smhc_a23a::W
• smhc::smhc_blksiz::R
• smhc::smhc_blksiz::SMHC_BLKSIZ_SPEC
• smhc::smhc_blksiz::W
• smhc::smhc_bytcnt::R
• smhc::smhc_bytcnt::SMHC_BYTCNT_SPEC
• smhc::smhc_bytcnt::W
• smhc::smhc_clkdiv::R
• smhc::smhc_clkdiv::SMHC_CLKDIV_SPEC
• smhc::smhc_clkdiv::W
• smhc::smhc_cmd::R
• smhc::smhc_cmd::SMHC_CMD_SPEC
• smhc::smhc_cmd::W
• smhc::smhc_cmdarg::R
• smhc::smhc_cmdarg::SMHC_CMDARG_SPEC
• smhc::smhc_cmdarg::W
• smhc::smhc_csdc::R
• smhc::smhc_csdc::SMHC_CSDC_SPEC
• smhc::smhc_csdc::W
• smhc::smhc_ctrl::R
• smhc::smhc_ctrl::SMHC_CTRL_SPEC
• smhc::smhc_ctrl::W
• smhc::smhc_ctype::R
• smhc::smhc_ctype::SMHC_CTYPE_SPEC
• smhc::smhc_ctype::W
• smhc::smhc_dbgc::R
• smhc::smhc_dbgc::SMHC_DBGC_SPEC
• smhc::smhc_dbgc::W
• smhc::smhc_dlba::R
• smhc::smhc_dlba::SMHC_DLBA_SPEC
• smhc::smhc_dlba::W
• smhc::smhc_drv_dl::R
• smhc::smhc_drv_dl::SMHC_DRV_DL_SPEC
• smhc::smhc_drv_dl::W
• smhc::smhc_ds_dl::R
• smhc::smhc_ds_dl::SMHC_DS_DL_SPEC
• smhc::smhc_ds_dl::W
• smhc::smhc_ext_cmd::R
• smhc::smhc_ext_cmd::SMHC_EXT_CMD_SPEC
• smhc::smhc_ext_cmd::W
• smhc::smhc_ext_resp::R
• smhc::smhc_ext_resp::SMHC_EXT_RESP_SPEC
• smhc::smhc_fifo::R
• smhc::smhc_fifo::SMHC_FIFO_SPEC
• smhc::smhc_fifo::W
• smhc::smhc_fifoth::R
• smhc::smhc_fifoth::SMHC_FIFOTH_SPEC
• smhc::smhc_fifoth::W
• smhc::smhc_funs::R
• smhc::smhc_funs::SMHC_FUNS_SPEC
• smhc::smhc_funs::W
• smhc::smhc_hs400_dl::R
• smhc::smhc_hs400_dl::SMHC_HS400_DL_SPEC
• smhc::smhc_hs400_dl::W
• smhc::smhc_hwrst::R
• smhc::smhc_hwrst::SMHC_HWRST_SPEC
• smhc::smhc_hwrst::W
• smhc::smhc_idie::R
• smhc::smhc_idie::SMHC_IDIE_SPEC
• smhc::smhc_idie::W
• smhc::smhc_idmac::R
• smhc::smhc_idmac::SMHC_IDMAC_SPEC
• smhc::smhc_idmac::W
• smhc::smhc_idst::R
• smhc::smhc_idst::SMHC_IDST_SPEC
• smhc::smhc_idst::W
• smhc::smhc_intmask::R
• smhc::smhc_intmask::SMHC_INTMASK_SPEC
• smhc::smhc_intmask::W
• smhc::smhc_mintsts::R
• smhc::smhc_mintsts::SMHC_MINTSTS_SPEC
• smhc::smhc_ntsr::R
• smhc::smhc_ntsr::SMHC_NTSR_SPEC
• smhc::smhc_ntsr::W
• smhc::smhc_resp0::R
• smhc::smhc_resp0::SMHC_RESP0_SPEC
• smhc::smhc_resp1::R
• smhc::smhc_resp1::SMHC_RESP1_SPEC
• smhc::smhc_resp2::R
• smhc::smhc_resp2::SMHC_RESP2_SPEC
• smhc::smhc_resp3::R
• smhc::smhc_resp3::SMHC_RESP3_SPEC
• smhc::smhc_rintsts::R
• smhc::smhc_rintsts::SMHC_RINTSTS_SPEC
• smhc::smhc_rintsts::W
• smhc::smhc_sfc::R
• smhc::smhc_sfc::SMHC_SFC_SPEC
• smhc::smhc_sfc::W
• smhc::smhc_smap_dl::R
• smhc::smhc_smap_dl::SMHC_SMAP_DL_SPEC
• smhc::smhc_smap_dl::W
• smhc::smhc_status::R
• smhc::smhc_status::SMHC_STATUS_SPEC
• smhc::smhc_tbc0::R
• smhc::smhc_tbc0::SMHC_TBC0_SPEC
• smhc::smhc_tbc1::R
• smhc::smhc_tbc1::SMHC_TBC1_SPEC
• smhc::smhc_thld::R
• smhc::smhc_thld::SMHC_THLD_SPEC
• smhc::smhc_thld::W
• smhc::smhc_tmout::R
• smhc::smhc_tmout::SMHC_TMOUT_SPEC
• smhc::smhc_tmout::W
• spi0::RegisterBlock
• spi0::spi_ba_ccr::R
• spi0::spi_ba_ccr::SPI_BA_CCR_SPEC
• spi0::spi_ba_ccr::W
• spi0::spi_batc::R
• spi0::spi_batc::SPI_BATC_SPEC
• spi0::spi_batc::W
• spi0::spi_bcc::R
• spi0::spi_bcc::SPI_BCC_SPEC
• spi0::spi_bcc::W
• spi0::spi_fcr::R
• spi0::spi_fcr::SPI_FCR_SPEC
• spi0::spi_fcr::W
• spi0::spi_fsr::R
• spi0::spi_fsr::SPI_FSR_SPEC
• spi0::spi_gcr::R
• spi0::spi_gcr::SPI_GCR_SPEC
• spi0::spi_gcr::W
• spi0::spi_ier::R
• spi0::spi_ier::SPI_IER_SPEC
• spi0::spi_ier::W
• spi0::spi_isr::R
• spi0::spi_isr::SPI_ISR_SPEC
• spi0::spi_isr::W
• spi0::spi_mbc::R
• spi0::spi_mbc::SPI_MBC_SPEC
• spi0::spi_mbc::W
• spi0::spi_mtc::R
• spi0::spi_mtc::SPI_MTC_SPEC
• spi0::spi_mtc::W
• spi0::spi_ndma_mode_ctl::R
• spi0::spi_ndma_mode_ctl::SPI_NDMA_MODE_CTL_SPEC
• spi0::spi_ndma_mode_ctl::W
• spi0::spi_rbr::R
• spi0::spi_rbr::SPI_RBR_SPEC
• spi0::spi_rbr::W
• spi0::spi_rxd::R
• spi0::spi_rxd::SPI_RXD_SPEC
• spi0::spi_rxd::W
• spi0::spi_rxd_16::R
• spi0::spi_rxd_16::SPI_RXD_16_SPEC
• spi0::spi_rxd_16::W
• spi0::spi_rxd_8::R
• spi0::spi_rxd_8::SPI_RXD_8_SPEC
• spi0::spi_rxd_8::W
• spi0::spi_samp_dl::R
• spi0::spi_samp_dl::SPI_SAMP_DL_SPEC
• spi0::spi_samp_dl::W
• spi0::spi_tbr::R
• spi0::spi_tbr::SPI_TBR_SPEC
• spi0::spi_tbr::W
• spi0::spi_tcr::R
• spi0::spi_tcr::SPI_TCR_SPEC
• spi0::spi_tcr::W
• spi0::spi_txd::R
• spi0::spi_txd::SPI_TXD_SPEC
• spi0::spi_txd::W
• spi0::spi_txd_16::R
• spi0::spi_txd_16::SPI_TXD_16_SPEC
• spi0::spi_txd_16::W
• spi0::spi_txd_8::R
• spi0::spi_txd_8::SPI_TXD_8_SPEC
• spi0::spi_txd_8::W
• spi0::spi_wcr::R
• spi0::spi_wcr::SPI_WCR_SPEC
• spi0::spi_wcr::W
• spi_dbi::RegisterBlock
• spi_dbi::dbi_ctl_0::DBI_CTL_0_SPEC
• spi_dbi::dbi_ctl_0::R
• spi_dbi::dbi_ctl_0::W
• spi_dbi::dbi_ctl_1::DBI_CTL_1_SPEC
• spi_dbi::dbi_ctl_1::R
• spi_dbi::dbi_ctl_1::W
• spi_dbi::dbi_ctl_2::DBI_CTL_2_SPEC
• spi_dbi::dbi_ctl_2::R
• spi_dbi::dbi_ctl_2::W
• spi_dbi::dbi_debug_0::DBI_DEBUG_0_SPEC
• spi_dbi::dbi_debug_0::R
• spi_dbi::dbi_debug_1::DBI_DEBUG_1_SPEC
• spi_dbi::dbi_debug_1::R
• spi_dbi::dbi_int::DBI_INT_SPEC
• spi_dbi::dbi_int::R
• spi_dbi::dbi_int::W
• spi_dbi::dbi_timer::DBI_TIMER_SPEC
• spi_dbi::dbi_timer::R
• spi_dbi::dbi_timer::W
• spi_dbi::dbi_video_szie::DBI_VIDEO_SZIE_SPEC
• spi_dbi::dbi_video_szie::R
• spi_dbi::dbi_video_szie::W
• spi_dbi::spi_ba_ccr::R
• spi_dbi::spi_ba_ccr::SPI_BA_CCR_SPEC
• spi_dbi::spi_ba_ccr::W
• spi_dbi::spi_batc::R
• spi_dbi::spi_batc::SPI_BATC_SPEC
• spi_dbi::spi_batc::W
• spi_dbi::spi_bcc::R
• spi_dbi::spi_bcc::SPI_BCC_SPEC
• spi_dbi::spi_bcc::W
• spi_dbi::spi_fcr::R
• spi_dbi::spi_fcr::SPI_FCR_SPEC
• spi_dbi::spi_fcr::W
• spi_dbi::spi_fsr::R
• spi_dbi::spi_fsr::SPI_FSR_SPEC
• spi_dbi::spi_gcr::R
• spi_dbi::spi_gcr::SPI_GCR_SPEC
• spi_dbi::spi_gcr::W
• spi_dbi::spi_ier::R
• spi_dbi::spi_ier::SPI_IER_SPEC
• spi_dbi::spi_ier::W
• spi_dbi::spi_isr::R
• spi_dbi::spi_isr::SPI_ISR_SPEC
• spi_dbi::spi_isr::W
• spi_dbi::spi_mbc::R
• spi_dbi::spi_mbc::SPI_MBC_SPEC
• spi_dbi::spi_mbc::W
• spi_dbi::spi_mtc::R
• spi_dbi::spi_mtc::SPI_MTC_SPEC
• spi_dbi::spi_mtc::W
• spi_dbi::spi_ndma_mode_ctl::R
• spi_dbi::spi_ndma_mode_ctl::SPI_NDMA_MODE_CTL_SPEC
• spi_dbi::spi_ndma_mode_ctl::W
• spi_dbi::spi_rbr::R
• spi_dbi::spi_rbr::SPI_RBR_SPEC
• spi_dbi::spi_rbr::W
• spi_dbi::spi_rxd::R
• spi_dbi::spi_rxd::SPI_RXD_SPEC
• spi_dbi::spi_rxd::W
• spi_dbi::spi_samp_dl::R
• spi_dbi::spi_samp_dl::SPI_SAMP_DL_SPEC
• spi_dbi::spi_samp_dl::W
• spi_dbi::spi_tbr::R
• spi_dbi::spi_tbr::SPI_TBR_SPEC
• spi_dbi::spi_tbr::W
• spi_dbi::spi_tcr::R
• spi_dbi::spi_tcr::SPI_TCR_SPEC
• spi_dbi::spi_tcr::W
• spi_dbi::spi_txd::R
• spi_dbi::spi_txd::SPI_TXD_SPEC
• spi_dbi::spi_txd::W
• spi_dbi::spi_wcr::R
• spi_dbi::spi_wcr::SPI_WCR_SPEC
• spi_dbi::spi_wcr::W
• spinlock::RegisterBlock
• spinlock::spinlock_irq_en_reg::R
• spinlock::spinlock_irq_en_reg::SPINLOCK_IRQ_EN_REG_SPEC
• spinlock::spinlock_irq_en_reg::W
• spinlock::spinlock_irq_sta_reg::R
• spinlock::spinlock_irq_sta_reg::SPINLOCK_IRQ_STA_REG_SPEC
• spinlock::spinlock_irq_sta_reg::W
• spinlock::spinlock_lock_reg::R
• spinlock::spinlock_lock_reg::SPINLOCK_LOCK_REG_SPEC
• spinlock::spinlock_lock_reg::W
• spinlock::spinlock_lockid_reg::R
• spinlock::spinlock_lockid_reg::SPINLOCK_LOCKID_REG_SPEC
• spinlock::spinlock_status_reg::R
• spinlock::spinlock_status_reg::SPINLOCK_STATUS_REG_SPEC
• spinlock::spinlock_systatus_reg::R
• spinlock::spinlock_systatus_reg::SPINLOCK_SYSTATUS_REG_SPEC
• sys_cfg::RegisterBlock
• sys_cfg::dsp_boot_rammap::DSP_BOOT_RAMMAP_SPEC
• sys_cfg::dsp_boot_rammap::R
• sys_cfg::dsp_boot_rammap::W
• sys_cfg::emac_ephy_clk0::EMAC_EPHY_CLK0_SPEC
• sys_cfg::emac_ephy_clk0::R
• sys_cfg::emac_ephy_clk0::W
• sys_cfg::res240_ctrl::R
• sys_cfg::res240_ctrl::RES240_CTRL_SPEC
• sys_cfg::res240_ctrl::W
• sys_cfg::rescal_ctrl::R
• sys_cfg::rescal_ctrl::RESCAL_CTRL_SPEC
• sys_cfg::rescal_ctrl::W
• sys_cfg::rescal_status::R
• sys_cfg::rescal_status::RESCAL_STATUS_SPEC
• sys_cfg::sys_ldo_ctrl::R
• sys_cfg::sys_ldo_ctrl::SYS_LDO_CTRL_SPEC
• sys_cfg::sys_ldo_ctrl::W
• sys_cfg::ver::R
• sys_cfg::ver::VER_SPEC
• tcon_lcd0::RegisterBlock
• tcon_lcd0::lcd_3d_fifo_reg::LCD_3D_FIFO_REG_SPEC
• tcon_lcd0::lcd_3d_fifo_reg::R
• tcon_lcd0::lcd_3d_fifo_reg::W
• tcon_lcd0::lcd_basic0_reg::LCD_BASIC0_REG_SPEC
• tcon_lcd0::lcd_basic0_reg::R
• tcon_lcd0::lcd_basic0_reg::W
• tcon_lcd0::lcd_basic1_reg::LCD_BASIC1_REG_SPEC
• tcon_lcd0::lcd_basic1_reg::R
• tcon_lcd0::lcd_basic1_reg::W
• tcon_lcd0::lcd_basic2_reg::LCD_BASIC2_REG_SPEC
• tcon_lcd0::lcd_basic2_reg::R
• tcon_lcd0::lcd_basic2_reg::W
• tcon_lcd0::lcd_basic3_reg::LCD_BASIC3_REG_SPEC
• tcon_lcd0::lcd_basic3_reg::R
• tcon_lcd0::lcd_basic3_reg::W
• tcon_lcd0::lcd_ceu_coef_add_reg::LCD_CEU_COEF_ADD_REG_SPEC
• tcon_lcd0::lcd_ceu_coef_add_reg::R
• tcon_lcd0::lcd_ceu_coef_add_reg::W
• tcon_lcd0::lcd_ceu_coef_mul_reg::LCD_CEU_COEF_MUL_REG_SPEC
• tcon_lcd0::lcd_ceu_coef_mul_reg::R
• tcon_lcd0::lcd_ceu_coef_mul_reg::W
• tcon_lcd0::lcd_ceu_coef_rang_reg::LCD_CEU_COEF_RANG_REG_SPEC
• tcon_lcd0::lcd_ceu_coef_rang_reg::R
• tcon_lcd0::lcd_ceu_coef_rang_reg::W
• tcon_lcd0::lcd_ceu_ctl_reg::LCD_CEU_CTL_REG_SPEC
• tcon_lcd0::lcd_ceu_ctl_reg::R
• tcon_lcd0::lcd_ceu_ctl_reg::W
• tcon_lcd0::lcd_cmap_ctl_reg::LCD_CMAP_CTL_REG_SPEC
• tcon_lcd0::lcd_cmap_ctl_reg::R
• tcon_lcd0::lcd_cmap_ctl_reg::W
• tcon_lcd0::lcd_cmap_even0_reg::LCD_CMAP_EVEN0_REG_SPEC
• tcon_lcd0::lcd_cmap_even0_reg::R
• tcon_lcd0::lcd_cmap_even0_reg::W
• tcon_lcd0::lcd_cmap_even1_reg::LCD_CMAP_EVEN1_REG_SPEC
• tcon_lcd0::lcd_cmap_even1_reg::R
• tcon_lcd0::lcd_cmap_even1_reg::W
• tcon_lcd0::lcd_cmap_odd0_reg::LCD_CMAP_ODD0_REG_SPEC
• tcon_lcd0::lcd_cmap_odd0_reg::R
• tcon_lcd0::lcd_cmap_odd0_reg::W
• tcon_lcd0::lcd_cmap_odd1_reg::LCD_CMAP_ODD1_REG_SPEC
• tcon_lcd0::lcd_cmap_odd1_reg::R
• tcon_lcd0::lcd_cmap_odd1_reg::W
• tcon_lcd0::lcd_cpu_if_reg::LCD_CPU_IF_REG_SPEC
• tcon_lcd0::lcd_cpu_if_reg::R
• tcon_lcd0::lcd_cpu_if_reg::W
• tcon_lcd0::lcd_cpu_rd0_reg::LCD_CPU_RD0_REG_SPEC
• tcon_lcd0::lcd_cpu_rd0_reg::R
• tcon_lcd0::lcd_cpu_rd0_reg::W
• tcon_lcd0::lcd_cpu_rd1_reg::LCD_CPU_RD1_REG_SPEC
• tcon_lcd0::lcd_cpu_rd1_reg::R
• tcon_lcd0::lcd_cpu_rd1_reg::W
• tcon_lcd0::lcd_cpu_tri0_reg::LCD_CPU_TRI0_REG_SPEC
• tcon_lcd0::lcd_cpu_tri0_reg::R
• tcon_lcd0::lcd_cpu_tri0_reg::W
• tcon_lcd0::lcd_cpu_tri1_reg::LCD_CPU_TRI1_REG_SPEC
• tcon_lcd0::lcd_cpu_tri1_reg::R
• tcon_lcd0::lcd_cpu_tri1_reg::W
• tcon_lcd0::lcd_cpu_tri2_reg::LCD_CPU_TRI2_REG_SPEC
• tcon_lcd0::lcd_cpu_tri2_reg::R
• tcon_lcd0::lcd_cpu_tri2_reg::W
• tcon_lcd0::lcd_cpu_tri3_reg::LCD_CPU_TRI3_REG_SPEC
• tcon_lcd0::lcd_cpu_tri3_reg::R
• tcon_lcd0::lcd_cpu_tri3_reg::W
• tcon_lcd0::lcd_cpu_tri4_reg::LCD_CPU_TRI4_REG_SPEC
• tcon_lcd0::lcd_cpu_tri4_reg::R
• tcon_lcd0::lcd_cpu_tri4_reg::W
• tcon_lcd0::lcd_cpu_tri5_reg::LCD_CPU_TRI5_REG_SPEC
• tcon_lcd0::lcd_cpu_tri5_reg::R
• tcon_lcd0::lcd_cpu_tri5_reg::W
• tcon_lcd0::lcd_cpu_wr_reg::LCD_CPU_WR_REG_SPEC
• tcon_lcd0::lcd_cpu_wr_reg::R
• tcon_lcd0::lcd_cpu_wr_reg::W
• tcon_lcd0::lcd_ctl_reg::LCD_CTL_REG_SPEC
• tcon_lcd0::lcd_ctl_reg::R
• tcon_lcd0::lcd_ctl_reg::W
• tcon_lcd0::lcd_dclk_reg::LCD_DCLK_REG_SPEC
• tcon_lcd0::lcd_dclk_reg::R
• tcon_lcd0::lcd_dclk_reg::W
• tcon_lcd0::lcd_debug_reg::LCD_DEBUG_REG_SPEC
• tcon_lcd0::lcd_debug_reg::R
• tcon_lcd0::lcd_debug_reg::W
• tcon_lcd0::lcd_frm_ctl_reg::LCD_FRM_CTL_REG_SPEC
• tcon_lcd0::lcd_frm_ctl_reg::R
• tcon_lcd0::lcd_frm_ctl_reg::W
• tcon_lcd0::lcd_frm_seed_reg::LCD_FRM_SEED_REG_SPEC
• tcon_lcd0::lcd_frm_seed_reg::R
• tcon_lcd0::lcd_frm_seed_reg::W
• tcon_lcd0::lcd_frm_tab_reg::LCD_FRM_TAB_REG_SPEC
• tcon_lcd0::lcd_frm_tab_reg::R
• tcon_lcd0::lcd_frm_tab_reg::W
• tcon_lcd0::lcd_gamma_table_reg::LCD_GAMMA_TABLE_REG_SPEC
• tcon_lcd0::lcd_gamma_table_reg::R
• tcon_lcd0::lcd_gamma_table_reg::W
• tcon_lcd0::lcd_gctl_reg::LCD_GCTL_REG_SPEC
• tcon_lcd0::lcd_gctl_reg::R
• tcon_lcd0::lcd_gctl_reg::W
• tcon_lcd0::lcd_gint0_reg::LCD_GINT0_REG_SPEC
• tcon_lcd0::lcd_gint0_reg::R
• tcon_lcd0::lcd_gint0_reg::W
• tcon_lcd0::lcd_gint1_reg::LCD_GINT1_REG_SPEC
• tcon_lcd0::lcd_gint1_reg::R
• tcon_lcd0::lcd_gint1_reg::W
• tcon_lcd0::lcd_hv_if_reg::LCD_HV_IF_REG_SPEC
• tcon_lcd0::lcd_hv_if_reg::R
• tcon_lcd0::lcd_hv_if_reg::W
• tcon_lcd0::lcd_io_pol_reg::LCD_IO_POL_REG_SPEC
• tcon_lcd0::lcd_io_pol_reg::R
• tcon_lcd0::lcd_io_pol_reg::W
• tcon_lcd0::lcd_io_tri_reg::LCD_IO_TRI_REG_SPEC
• tcon_lcd0::lcd_io_tri_reg::R
• tcon_lcd0::lcd_io_tri_reg::W
• tcon_lcd0::lcd_lvds0_ana_reg::LCD_LVDS0_ANA_REG_SPEC
• tcon_lcd0::lcd_lvds0_ana_reg::R
• tcon_lcd0::lcd_lvds0_ana_reg::W
• tcon_lcd0::lcd_lvds1_ana_reg::LCD_LVDS1_ANA_REG_SPEC
• tcon_lcd0::lcd_lvds1_ana_reg::R
• tcon_lcd0::lcd_lvds1_ana_reg::W
• tcon_lcd0::lcd_lvds1_if_reg::LCD_LVDS1_IF_REG_SPEC
• tcon_lcd0::lcd_lvds1_if_reg::R
• tcon_lcd0::lcd_lvds1_if_reg::W
• tcon_lcd0::lcd_lvds_if_reg::LCD_LVDS_IF_REG_SPEC
• tcon_lcd0::lcd_lvds_if_reg::R
• tcon_lcd0::lcd_lvds_if_reg::W
• tcon_lcd0::lcd_safe_period_reg::LCD_SAFE_PERIOD_REG_SPEC
• tcon_lcd0::lcd_safe_period_reg::R
• tcon_lcd0::lcd_safe_period_reg::W
• tcon_lcd0::lcd_slave_stop_pos_reg::LCD_SLAVE_STOP_POS_REG_SPEC
• tcon_lcd0::lcd_slave_stop_pos_reg::R
• tcon_lcd0::lcd_slave_stop_pos_reg::W
• tcon_lcd0::lcd_sync_ctl_reg::LCD_SYNC_CTL_REG_SPEC
• tcon_lcd0::lcd_sync_ctl_reg::R
• tcon_lcd0::lcd_sync_ctl_reg::W
• tcon_lcd0::lcd_sync_pos_reg::LCD_SYNC_POS_REG_SPEC
• tcon_lcd0::lcd_sync_pos_reg::R
• tcon_lcd0::lcd_sync_pos_reg::W
• tcon_tv0::RegisterBlock
• tcon_tv0::tv_basic0_reg::R
• tcon_tv0::tv_basic0_reg::TV_BASIC0_REG_SPEC
• tcon_tv0::tv_basic0_reg::W
• tcon_tv0::tv_basic1_reg::R
• tcon_tv0::tv_basic1_reg::TV_BASIC1_REG_SPEC
• tcon_tv0::tv_basic1_reg::W
• tcon_tv0::tv_basic2_reg::R
• tcon_tv0::tv_basic2_reg::TV_BASIC2_REG_SPEC
• tcon_tv0::tv_basic2_reg::W
• tcon_tv0::tv_basic3_reg::R
• tcon_tv0::tv_basic3_reg::TV_BASIC3_REG_SPEC
• tcon_tv0::tv_basic3_reg::W
• tcon_tv0::tv_basic4_reg::R
• tcon_tv0::tv_basic4_reg::TV_BASIC4_REG_SPEC
• tcon_tv0::tv_basic4_reg::W
• tcon_tv0::tv_basic5_reg::R
• tcon_tv0::tv_basic5_reg::TV_BASIC5_REG_SPEC
• tcon_tv0::tv_basic5_reg::W
• tcon_tv0::tv_ceu_coef_mul_reg::R
• tcon_tv0::tv_ceu_coef_mul_reg::TV_CEU_COEF_MUL_REG_SPEC
• tcon_tv0::tv_ceu_coef_mul_reg::W
• tcon_tv0::tv_ceu_coef_rang_reg::R
• tcon_tv0::tv_ceu_coef_rang_reg::TV_CEU_COEF_RANG_REG_SPEC
• tcon_tv0::tv_ceu_coef_rang_reg::W
• tcon_tv0::tv_ceu_ctl_reg::R
• tcon_tv0::tv_ceu_ctl_reg::TV_CEU_CTL_REG_SPEC
• tcon_tv0::tv_ceu_ctl_reg::W
• tcon_tv0::tv_ctl_reg::R
• tcon_tv0::tv_ctl_reg::TV_CTL_REG_SPEC
• tcon_tv0::tv_ctl_reg::W
• tcon_tv0::tv_data_io_pol0_reg::R
• tcon_tv0::tv_data_io_pol0_reg::TV_DATA_IO_POL0_REG_SPEC
• tcon_tv0::tv_data_io_pol0_reg::W
• tcon_tv0::tv_data_io_pol1_reg::R
• tcon_tv0::tv_data_io_pol1_reg::TV_DATA_IO_POL1_REG_SPEC
• tcon_tv0::tv_data_io_pol1_reg::W
• tcon_tv0::tv_data_io_tri0_reg::R
• tcon_tv0::tv_data_io_tri0_reg::TV_DATA_IO_TRI0_REG_SPEC
• tcon_tv0::tv_data_io_tri0_reg::W
• tcon_tv0::tv_data_io_tri1_reg::R
• tcon_tv0::tv_data_io_tri1_reg::TV_DATA_IO_TRI1_REG_SPEC
• tcon_tv0::tv_data_io_tri1_reg::W
• tcon_tv0::tv_debug_reg::R
• tcon_tv0::tv_debug_reg::TV_DEBUG_REG_SPEC
• tcon_tv0::tv_debug_reg::W
• tcon_tv0::tv_fill_begin_reg::R
• tcon_tv0::tv_fill_begin_reg::TV_FILL_BEGIN_REG_SPEC
• tcon_tv0::tv_fill_begin_reg::W
• tcon_tv0::tv_fill_ctl_reg::R
• tcon_tv0::tv_fill_ctl_reg::TV_FILL_CTL_REG_SPEC
• tcon_tv0::tv_fill_ctl_reg::W
• tcon_tv0::tv_fill_data_reg::R
• tcon_tv0::tv_fill_data_reg::TV_FILL_DATA_REG_SPEC
• tcon_tv0::tv_fill_data_reg::W
• tcon_tv0::tv_fill_end_reg::R
• tcon_tv0::tv_fill_end_reg::TV_FILL_END_REG_SPEC
• tcon_tv0::tv_fill_end_reg::W
• tcon_tv0::tv_gctl_reg::R
• tcon_tv0::tv_gctl_reg::TV_GCTL_REG_SPEC
• tcon_tv0::tv_gctl_reg::W
• tcon_tv0::tv_gint0_reg::R
• tcon_tv0::tv_gint0_reg::TV_GINT0_REG_SPEC
• tcon_tv0::tv_gint0_reg::W
• tcon_tv0::tv_gint1_reg::R
• tcon_tv0::tv_gint1_reg::TV_GINT1_REG_SPEC
• tcon_tv0::tv_gint1_reg::W
• tcon_tv0::tv_io_pol_reg::R
• tcon_tv0::tv_io_pol_reg::TV_IO_POL_REG_SPEC
• tcon_tv0::tv_io_pol_reg::W
• tcon_tv0::tv_io_tri_reg::R
• tcon_tv0::tv_io_tri_reg::TV_IO_TRI_REG_SPEC
• tcon_tv0::tv_io_tri_reg::W
• tcon_tv0::tv_pixeldepth_mode_reg::R
• tcon_tv0::tv_pixeldepth_mode_reg::TV_PIXELDEPTH_MODE_REG_SPEC
• tcon_tv0::tv_pixeldepth_mode_reg::W
• tcon_tv0::tv_safe_period_reg::R
• tcon_tv0::tv_safe_period_reg::TV_SAFE_PERIOD_REG_SPEC
• tcon_tv0::tv_safe_period_reg::W
• tcon_tv0::tv_src_ctl_reg::R
• tcon_tv0::tv_src_ctl_reg::TV_SRC_CTL_REG_SPEC
• tcon_tv0::tv_src_ctl_reg::W
• ths::RegisterBlock
• ths::ths_alarm_ctrl::R
• ths::ths_alarm_ctrl::THS_ALARM_CTRL_SPEC
• ths::ths_alarm_ctrl::W
• ths::ths_alarm_intc::R
• ths::ths_alarm_intc::THS_ALARM_INTC_SPEC
• ths::ths_alarm_intc::W
• ths::ths_alarm_ints::R
• ths::ths_alarm_ints::THS_ALARM_INTS_SPEC
• ths::ths_alarm_ints::W
• ths::ths_alarmo_ints::R
• ths::ths_alarmo_ints::THS_ALARMO_INTS_SPEC
• ths::ths_alarmo_ints::W
• ths::ths_cdata::R
• ths::ths_cdata::THS_CDATA_SPEC
• ths::ths_cdata::W
• ths::ths_ctrl::R
• ths::ths_ctrl::THS_CTRL_SPEC
• ths::ths_ctrl::W
• ths::ths_data::R
• ths::ths_data::THS_DATA_SPEC
• ths::ths_data_intc::R
• ths::ths_data_intc::THS_DATA_INTC_SPEC
• ths::ths_data_intc::W
• ths::ths_data_ints::R
• ths::ths_data_ints::THS_DATA_INTS_SPEC
• ths::ths_data_ints::W
• ths::ths_en::R
• ths::ths_en::THS_EN_SPEC
• ths::ths_en::W
• ths::ths_filter::R
• ths::ths_filter::THS_FILTER_SPEC
• ths::ths_filter::W
• ths::ths_per::R
• ths::ths_per::THS_PER_SPEC
• ths::ths_per::W
• ths::ths_shut_intc::R
• ths::ths_shut_intc::THS_SHUT_INTC_SPEC
• ths::ths_shut_intc::W
• ths::ths_shut_ints::R
• ths::ths_shut_ints::THS_SHUT_INTS_SPEC
• ths::ths_shut_ints::W
• ths::ths_shutdown_ctrl::R
• ths::ths_shutdown_ctrl::THS_SHUTDOWN_CTRL_SPEC
• ths::ths_shutdown_ctrl::W
• timer::RegisterBlock
• timer::avs_cnt0::AVS_CNT0_SPEC
• timer::avs_cnt0::R
• timer::avs_cnt0::W
• timer::avs_cnt1::AVS_CNT1_SPEC
• timer::avs_cnt1::R
• timer::avs_cnt1::W
• timer::avs_cnt_ctl::AVS_CNT_CTL_SPEC
• timer::avs_cnt_ctl::R
• timer::avs_cnt_ctl::W
• timer::avs_cnt_div::AVS_CNT_DIV_SPEC
• timer::avs_cnt_div::R
• timer::avs_cnt_div::W
• timer::tmr_ctrl::R
• timer::tmr_ctrl::TMR_CTRL_SPEC
• timer::tmr_ctrl::W
• timer::tmr_cur_value::R
• timer::tmr_cur_value::TMR_CUR_VALUE_SPEC
• timer::tmr_cur_value::W
• timer::tmr_intv_value::R
• timer::tmr_intv_value::TMR_INTV_VALUE_SPEC
• timer::tmr_intv_value::W
• timer::tmr_irq_en::R
• timer::tmr_irq_en::TMR_IRQ_EN_SPEC
• timer::tmr_irq_en::W
• timer::tmr_irq_sta::R
• timer::tmr_irq_sta::TMR_IRQ_STA_SPEC
• timer::tmr_irq_sta::W
• timer::wdog_cfg::R
• timer::wdog_cfg::W
• timer::wdog_cfg::WDOG_CFG_SPEC
• timer::wdog_ctrl::R
• timer::wdog_ctrl::W
• timer::wdog_ctrl::WDOG_CTRL_SPEC
• timer::wdog_irq_en::R
• timer::wdog_irq_en::W
• timer::wdog_irq_en::WDOG_IRQ_EN_SPEC
• timer::wdog_irq_sta::R
• timer::wdog_irq_sta::W
• timer::wdog_irq_sta::WDOG_IRQ_STA_SPEC
• timer::wdog_mode::R
• timer::wdog_mode::W
• timer::wdog_mode::WDOG_MODE_SPEC
• timer::wdog_output_cfg::R
• timer::wdog_output_cfg::W
• timer::wdog_output_cfg::WDOG_OUTPUT_CFG_SPEC
• timer::wdog_soft_rst::R
• timer::wdog_soft_rst::W
• timer::wdog_soft_rst::WDOG_SOFT_RST_SPEC
• tpadc::RegisterBlock
• tpadc::tp_cali_data::R
• tpadc::tp_cali_data::TP_CALI_DATA_SPEC
• tpadc::tp_cali_data::W
• tpadc::tp_ctrl0::R
• tpadc::tp_ctrl0::TP_CTRL0_SPEC
• tpadc::tp_ctrl0::W
• tpadc::tp_ctrl1::R
• tpadc::tp_ctrl1::TP_CTRL1_SPEC
• tpadc::tp_ctrl1::W
• tpadc::tp_ctrl2::R
• tpadc::tp_ctrl2::TP_CTRL2_SPEC
• tpadc::tp_ctrl2::W
• tpadc::tp_ctrl3::R
• tpadc::tp_ctrl3::TP_CTRL3_SPEC
• tpadc::tp_ctrl3::W
• tpadc::tp_data::R
• tpadc::tp_data::TP_DATA_SPEC
• tpadc::tp_int_fifo_ctrl::R
• tpadc::tp_int_fifo_ctrl::TP_INT_FIFO_CTRL_SPEC
• tpadc::tp_int_fifo_ctrl::W
• tpadc::tp_int_fifo_stat::R
• tpadc::tp_int_fifo_stat::TP_INT_FIFO_STAT_SPEC
• tpadc::tp_int_fifo_stat::W
• tvd0::RegisterBlock
• tvd0::tvd_clamp_agc1::R
• tvd0::tvd_clamp_agc1::TVD_CLAMP_AGC1_SPEC
• tvd0::tvd_clamp_agc1::W
• tvd0::tvd_clamp_agc2::R
• tvd0::tvd_clamp_agc2::TVD_CLAMP_AGC2_SPEC
• tvd0::tvd_clamp_agc2::W
• tvd0::tvd_clock1::R
• tvd0::tvd_clock1::TVD_CLOCK1_SPEC
• tvd0::tvd_clock1::W
• tvd0::tvd_clock2::R
• tvd0::tvd_clock2::TVD_CLOCK2_SPEC
• tvd0::tvd_clock2::W
• tvd0::tvd_debug1::R
• tvd0::tvd_debug1::TVD_DEBUG1_SPEC
• tvd0::tvd_debug1::W
• tvd0::tvd_en::R
• tvd0::tvd_en::TVD_EN_SPEC
• tvd0::tvd_en::W
• tvd0::tvd_enhance1::R
• tvd0::tvd_enhance1::TVD_ENHANCE1_SPEC
• tvd0::tvd_enhance1::W
• tvd0::tvd_enhance2::R
• tvd0::tvd_enhance2::TVD_ENHANCE2_SPEC
• tvd0::tvd_enhance2::W
• tvd0::tvd_enhance3::R
• tvd0::tvd_enhance3::TVD_ENHANCE3_SPEC
• tvd0::tvd_enhance3::W
• tvd0::tvd_hlock1::R
• tvd0::tvd_hlock1::TVD_HLOCK1_SPEC
• tvd0::tvd_hlock1::W
• tvd0::tvd_hlock2::R
• tvd0::tvd_hlock2::TVD_HLOCK2_SPEC
• tvd0::tvd_hlock2::W
• tvd0::tvd_hlock3::R
• tvd0::tvd_hlock3::TVD_HLOCK3_SPEC
• tvd0::tvd_hlock3::W
• tvd0::tvd_hlock4::R
• tvd0::tvd_hlock4::TVD_HLOCK4_SPEC
• tvd0::tvd_hlock4::W
• tvd0::tvd_hlock5::R
• tvd0::tvd_hlock5::TVD_HLOCK5_SPEC
• tvd0::tvd_hlock5::W
• tvd0::tvd_irq_ctl::R
• tvd0::tvd_irq_ctl::TVD_IRQ_CTL_SPEC
• tvd0::tvd_irq_ctl::W
• tvd0::tvd_irq_status::R
• tvd0::tvd_irq_status::TVD_IRQ_STATUS_SPEC
• tvd0::tvd_irq_status::W
• tvd0::tvd_mode::R
• tvd0::tvd_mode::TVD_MODE_SPEC
• tvd0::tvd_mode::W
• tvd0::tvd_status1::R
• tvd0::tvd_status1::TVD_STATUS1_SPEC
• tvd0::tvd_status1::W
• tvd0::tvd_status2::R
• tvd0::tvd_status2::TVD_STATUS2_SPEC
• tvd0::tvd_status2::W
• tvd0::tvd_status3::R
• tvd0::tvd_status3::TVD_STATUS3_SPEC
• tvd0::tvd_status3::W
• tvd0::tvd_status4::R
• tvd0::tvd_status4::TVD_STATUS4_SPEC
• tvd0::tvd_status4::W
• tvd0::tvd_status5::R
• tvd0::tvd_status5::TVD_STATUS5_SPEC
• tvd0::tvd_status5::W
• tvd0::tvd_status6::R
• tvd0::tvd_status6::TVD_STATUS6_SPEC
• tvd0::tvd_status6::W
• tvd0::tvd_vlock1::R
• tvd0::tvd_vlock1::TVD_VLOCK1_SPEC
• tvd0::tvd_vlock1::W
• tvd0::tvd_vlock2::R
• tvd0::tvd_vlock2::TVD_VLOCK2_SPEC
• tvd0::tvd_vlock2::W
• tvd0::tvd_wb1::R
• tvd0::tvd_wb1::TVD_WB1_SPEC
• tvd0::tvd_wb1::W
• tvd0::tvd_wb2::R
• tvd0::tvd_wb2::TVD_WB2_SPEC
• tvd0::tvd_wb2::W
• tvd0::tvd_wb3::R
• tvd0::tvd_wb3::TVD_WB3_SPEC
• tvd0::tvd_wb3::W
• tvd0::tvd_wb4::R
• tvd0::tvd_wb4::TVD_WB4_SPEC
• tvd0::tvd_wb4::W
• tvd0::tvd_yc_sep1::R
• tvd0::tvd_yc_sep1::TVD_YC_SEP1_SPEC
• tvd0::tvd_yc_sep1::W
• tvd0::tvd_yc_sep2::R
• tvd0::tvd_yc_sep2::TVD_YC_SEP2_SPEC
• tvd0::tvd_yc_sep2::W
• tvd_top::RegisterBlock
• tvd_top::tvd_3d_ctl1::R
• tvd_top::tvd_3d_ctl1::TVD_3D_CTL1_SPEC
• tvd_top::tvd_3d_ctl1::W
• tvd_top::tvd_3d_ctl2::R
• tvd_top::tvd_3d_ctl2::TVD_3D_CTL2_SPEC
• tvd_top::tvd_3d_ctl2::W
• tvd_top::tvd_3d_ctl3::R
• tvd_top::tvd_3d_ctl3::TVD_3D_CTL3_SPEC
• tvd_top::tvd_3d_ctl3::W
• tvd_top::tvd_3d_ctl4::R
• tvd_top::tvd_3d_ctl4::TVD_3D_CTL4_SPEC
• tvd_top::tvd_3d_ctl4::W
• tvd_top::tvd_3d_ctl5::R
• tvd_top::tvd_3d_ctl5::TVD_3D_CTL5_SPEC
• tvd_top::tvd_3d_ctl5::W
• tvd_top::tvd_adc_cfg::R
• tvd_top::tvd_adc_cfg::TVD_ADC_CFG_SPEC
• tvd_top::tvd_adc_cfg::W
• tvd_top::tvd_adc_ctl::R
• tvd_top::tvd_adc_ctl::TVD_ADC_CTL_SPEC
• tvd_top::tvd_adc_ctl::W
• tvd_top::tvd_top_ctl::R
• tvd_top::tvd_top_ctl::TVD_TOP_CTL_SPEC
• tvd_top::tvd_top_ctl::W
• tvd_top::tvd_top_map::R
• tvd_top::tvd_top_map::TVD_TOP_MAP_SPEC
• tvd_top::tvd_top_map::W
• tve::RegisterBlock
• tve::tve_000_reg::R
• tve::tve_000_reg::TVE_000_REG_SPEC
• tve::tve_000_reg::W
• tve::tve_004_reg::R
• tve::tve_004_reg::TVE_004_REG_SPEC
• tve::tve_004_reg::W
• tve::tve_008_reg::R
• tve::tve_008_reg::TVE_008_REG_SPEC
• tve::tve_008_reg::W
• tve::tve_00c_reg::R
• tve::tve_00c_reg::TVE_00C_REG_SPEC
• tve::tve_00c_reg::W
• tve::tve_010_reg::R
• tve::tve_010_reg::TVE_010_REG_SPEC
• tve::tve_010_reg::W
• tve::tve_014_reg::R
• tve::tve_014_reg::TVE_014_REG_SPEC
• tve::tve_014_reg::W
• tve::tve_018_reg::R
• tve::tve_018_reg::TVE_018_REG_SPEC
• tve::tve_018_reg::W
• tve::tve_01c_reg::R
• tve::tve_01c_reg::TVE_01C_REG_SPEC
• tve::tve_01c_reg::W
• tve::tve_020_reg::R
• tve::tve_020_reg::TVE_020_REG_SPEC
• tve::tve_020_reg::W
• tve::tve_024_reg::R
• tve::tve_024_reg::TVE_024_REG_SPEC
• tve::tve_024_reg::W
• tve::tve_030_reg::R
• tve::tve_030_reg::TVE_030_REG_SPEC
• tve::tve_030_reg::W
• tve::tve_034_reg::R
• tve::tve_034_reg::TVE_034_REG_SPEC
• tve::tve_034_reg::W
• tve::tve_038_reg::R
• tve::tve_038_reg::TVE_038_REG_SPEC
• tve::tve_038_reg::W
• tve::tve_03c_reg::R
• tve::tve_03c_reg::TVE_03C_REG_SPEC
• tve::tve_03c_reg::W
• tve::tve_0f8_reg::R
• tve::tve_0f8_reg::TVE_0F8_REG_SPEC
• tve::tve_0f8_reg::W
• tve::tve_0fc_reg::R
• tve::tve_0fc_reg::TVE_0FC_REG_SPEC
• tve::tve_0fc_reg::W
• tve::tve_100_reg::R
• tve::tve_100_reg::TVE_100_REG_SPEC
• tve::tve_100_reg::W
• tve::tve_104_reg::R
• tve::tve_104_reg::TVE_104_REG_SPEC
• tve::tve_104_reg::W
• tve::tve_108_reg::R
• tve::tve_108_reg::TVE_108_REG_SPEC
• tve::tve_108_reg::W
• tve::tve_10c_reg::R
• tve::tve_10c_reg::TVE_10C_REG_SPEC
• tve::tve_10c_reg::W
• tve::tve_110_reg::R
• tve::tve_110_reg::TVE_110_REG_SPEC
• tve::tve_110_reg::W
• tve::tve_114_reg::R
• tve::tve_114_reg::TVE_114_REG_SPEC
• tve::tve_114_reg::W
• tve::tve_118_reg::R
• tve::tve_118_reg::TVE_118_REG_SPEC
• tve::tve_118_reg::W
• tve::tve_11c_reg::R
• tve::tve_11c_reg::TVE_11C_REG_SPEC
• tve::tve_11c_reg::W
• tve::tve_120_reg::R
• tve::tve_120_reg::TVE_120_REG_SPEC
• tve::tve_120_reg::W
• tve::tve_124_reg::R
• tve::tve_124_reg::TVE_124_REG_SPEC
• tve::tve_124_reg::W
• tve::tve_128_reg::R
• tve::tve_128_reg::TVE_128_REG_SPEC
• tve::tve_128_reg::W
• tve::tve_12c_reg::R
• tve::tve_12c_reg::TVE_12C_REG_SPEC
• tve::tve_12c_reg::W
• tve::tve_130_reg::R
• tve::tve_130_reg::TVE_130_REG_SPEC
• tve::tve_130_reg::W
• tve::tve_134_reg::R
• tve::tve_134_reg::TVE_134_REG_SPEC
• tve::tve_134_reg::W
• tve::tve_138_reg::R
• tve::tve_138_reg::TVE_138_REG_SPEC
• tve::tve_138_reg::W
• tve::tve_13c_reg::R
• tve::tve_13c_reg::TVE_13C_REG_SPEC
• tve::tve_13c_reg::W
• tve::tve_380_reg::R
• tve::tve_380_reg::TVE_380_REG_SPEC
• tve::tve_380_reg::W
• tve::tve_384_reg::R
• tve::tve_384_reg::TVE_384_REG_SPEC
• tve::tve_384_reg::W
• tve_top::RegisterBlock
• tve_top::tve_dac_cfg0::R
• tve_top::tve_dac_cfg0::TVE_DAC_CFG0_SPEC
• tve_top::tve_dac_cfg0::W
• tve_top::tve_dac_cfg1::R
• tve_top::tve_dac_cfg1::TVE_DAC_CFG1_SPEC
• tve_top::tve_dac_cfg1::W
• tve_top::tve_dac_cfg2::R
• tve_top::tve_dac_cfg2::TVE_DAC_CFG2_SPEC
• tve_top::tve_dac_cfg2::W
• tve_top::tve_dac_cfg3::R
• tve_top::tve_dac_cfg3::TVE_DAC_CFG3_SPEC
• tve_top::tve_dac_cfg3::W
• tve_top::tve_dac_map::R
• tve_top::tve_dac_map::TVE_DAC_MAP_SPEC
• tve_top::tve_dac_map::W
• tve_top::tve_dac_status::R
• tve_top::tve_dac_status::TVE_DAC_STATUS_SPEC
• tve_top::tve_dac_status::W
• tve_top::tve_dac_test::R
• tve_top::tve_dac_test::TVE_DAC_TEST_SPEC
• tve_top::tve_dac_test::W
• twi::RegisterBlock
• twi::twi_addr::R
• twi::twi_addr::TWI_ADDR_SPEC
• twi::twi_addr::W
• twi::twi_ccr::R
• twi::twi_ccr::TWI_CCR_SPEC
• twi::twi_ccr::W
• twi::twi_cntr::R
• twi::twi_cntr::TWI_CNTR_SPEC
• twi::twi_cntr::W
• twi::twi_data::R
• twi::twi_data::TWI_DATA_SPEC
• twi::twi_data::W
• twi::twi_drv_bus_ctrl::R
• twi::twi_drv_bus_ctrl::TWI_DRV_BUS_CTRL_SPEC
• twi::twi_drv_bus_ctrl::W
• twi::twi_drv_cfg::R
• twi::twi_drv_cfg::TWI_DRV_CFG_SPEC
• twi::twi_drv_cfg::W
• twi::twi_drv_ctrl::R
• twi::twi_drv_ctrl::TWI_DRV_CTRL_SPEC
• twi::twi_drv_ctrl::W
• twi::twi_drv_dma_cfg::R
• twi::twi_drv_dma_cfg::TWI_DRV_DMA_CFG_SPEC
• twi::twi_drv_dma_cfg::W
• twi::twi_drv_fifo_con::R
• twi::twi_drv_fifo_con::TWI_DRV_FIFO_CON_SPEC
• twi::twi_drv_fifo_con::W
• twi::twi_drv_fmt::R
• twi::twi_drv_fmt::TWI_DRV_FMT_SPEC
• twi::twi_drv_fmt::W
• twi::twi_drv_int_ctrl::R
• twi::twi_drv_int_ctrl::TWI_DRV_INT_CTRL_SPEC
• twi::twi_drv_int_ctrl::W
• twi::twi_drv_recv_fifo_acc::R
• twi::twi_drv_recv_fifo_acc::TWI_DRV_RECV_FIFO_ACC_SPEC
• twi::twi_drv_send_fifo_acc::TWI_DRV_SEND_FIFO_ACC_SPEC
• twi::twi_drv_send_fifo_acc::W
• twi::twi_drv_slv::R
• twi::twi_drv_slv::TWI_DRV_SLV_SPEC
• twi::twi_drv_slv::W
• twi::twi_efr::R
• twi::twi_efr::TWI_EFR_SPEC
• twi::twi_efr::W
• twi::twi_lcr::R
• twi::twi_lcr::TWI_LCR_SPEC
• twi::twi_lcr::W
• twi::twi_srst::R
• twi::twi_srst::TWI_SRST_SPEC
• twi::twi_srst::W
• twi::twi_stat::R
• twi::twi_stat::TWI_STAT_SPEC
• twi::twi_xaddr::R
• twi::twi_xaddr::TWI_XADDR_SPEC
• twi::twi_xaddr::W
• uart::RegisterBlock
• uart::dbg_dlh::DBG_DLH_SPEC
• uart::dbg_dlh::R
• uart::dbg_dll::DBG_DLL_SPEC
• uart::dbg_dll::R
• uart::dlh::DLH_SPEC
• uart::dlh::R
• uart::dlh::W
• uart::dll::DLL_SPEC
• uart::dll::R
• uart::dll::W
• uart::dma_req_en::DMA_REQ_EN_SPEC
• uart::dma_req_en::R
• uart::dma_req_en::W
• uart::fcc::FCC_SPEC
• uart::fcc::R
• uart::fcc::W
• uart::fcr::FCR_SPEC
• uart::fcr::W
• uart::halt::HALT_SPEC
• uart::halt::R
• uart::halt::W
• uart::hsk::HSK_SPEC
• uart::hsk::R
• uart::hsk::W
• uart::ier::IER_SPEC
• uart::ier::R
• uart::ier::W
• uart::iir::IIR_SPEC
• uart::iir::R
• uart::lcr::LCR_SPEC
• uart::lcr::R
• uart::lcr::W
• uart::lsr::LSR_SPEC
• uart::lsr::R
• uart::mcr::MCR_SPEC
• uart::mcr::R
• uart::mcr::W
• uart::msr::MSR_SPEC
• uart::msr::R
• uart::rbr::R
• uart::rbr::RBR_SPEC
• uart::rfl::R
• uart::rfl::RFL_SPEC
• uart::rxdma_bl::R
• uart::rxdma_bl::RXDMA_BL_SPEC
• uart::rxdma_bl::W
• uart::rxdma_ctrl::R
• uart::rxdma_ctrl::RXDMA_CTRL_SPEC
• uart::rxdma_ctrl::W
• uart::rxdma_dcnt::R
• uart::rxdma_dcnt::RXDMA_DCNT_SPEC
• uart::rxdma_dcnt::W
• uart::rxdma_ie::R
• uart::rxdma_ie::RXDMA_IE_SPEC
• uart::rxdma_ie::W
• uart::rxdma_is::R
• uart::rxdma_is::RXDMA_IS_SPEC
• uart::rxdma_is::W
• uart::rxdma_lmt::R
• uart::rxdma_lmt::RXDMA_LMT_SPEC
• uart::rxdma_lmt::W
• uart::rxdma_raddrh::R
• uart::rxdma_raddrh::RXDMA_RADDRH_SPEC
• uart::rxdma_raddrh::W
• uart::rxdma_raddrl::R
• uart::rxdma_raddrl::RXDMA_RADDRL_SPEC
• uart::rxdma_raddrl::W
• uart::rxdma_saddrh::R
• uart::rxdma_saddrh::RXDMA_SADDRH_SPEC
• uart::rxdma_saddrh::W
• uart::rxdma_saddrl::R
• uart::rxdma_saddrl::RXDMA_SADDRL_SPEC
• uart::rxdma_saddrl::W
• uart::rxdma_sta::R
• uart::rxdma_sta::RXDMA_STA_SPEC
• uart::rxdma_sta::W
• uart::rxdma_str::R
• uart::rxdma_str::RXDMA_STR_SPEC
• uart::rxdma_str::W
• uart::rxdma_waddrh::R
• uart::rxdma_waddrh::RXDMA_WADDRH_SPEC
• uart::rxdma_waddrl::R
• uart::rxdma_waddrl::RXDMA_WADDRL_SPEC
• uart::sch::R
• uart::sch::SCH_SPEC
• uart::sch::W
• uart::tfl::R
• uart::tfl::TFL_SPEC
• uart::thr::THR_SPEC
• uart::thr::W
• uart::usr::R
• uart::usr::USR_SPEC
• usb1::EHCI_CAPABILITY
• usb1::EHCI_OPERATIONAL
• usb1::HCI_CONTROLLER_PHY_INTERFACE
• usb1::OHCI_CONTROL_STATUS_PARTITION
• usb1::OHCI_FRAME_COUNTER_PARTITION
• usb1::OHCI_MEMORY_POINTER_PARTITION
• usb1::OHCI_ROOT_HUB_PARTITION
• usb1::RegisterBlock
• usb1::ehci_capability::caplength::CAPLENGTH_SPEC
• usb1::ehci_capability::caplength::R
• usb1::ehci_capability::hccparams::HCCPARAMS_SPEC
• usb1::ehci_capability::hccparams::R
• usb1::ehci_capability::hciversion::HCIVERSION_SPEC
• usb1::ehci_capability::hciversion::R
• usb1::ehci_capability::hcsp_portroute::HCSP_PORTROUTE_SPEC
• usb1::ehci_capability::hcsp_portroute::R
• usb1::ehci_capability::hcsparams::HCSPARAMS_SPEC
• usb1::ehci_capability::hcsparams::R
• usb1::ehci_operational::asynclistaddr::ASYNCLISTADDR_SPEC
• usb1::ehci_operational::asynclistaddr::R
• usb1::ehci_operational::asynclistaddr::W
• usb1::ehci_operational::configflag::CONFIGFLAG_SPEC
• usb1::ehci_operational::configflag::R
• usb1::ehci_operational::configflag::W
• usb1::ehci_operational::ctrldssegment::CTRLDSSEGMENT_SPEC
• usb1::ehci_operational::ctrldssegment::R
• usb1::ehci_operational::ctrldssegment::W
• usb1::ehci_operational::frindex::FRINDEX_SPEC
• usb1::ehci_operational::frindex::R
• usb1::ehci_operational::frindex::W
• usb1::ehci_operational::periodiclistbase::PERIODICLISTBASE_SPEC
• usb1::ehci_operational::periodiclistbase::R
• usb1::ehci_operational::periodiclistbase::W
• usb1::ehci_operational::portsc::PORTSC_SPEC
• usb1::ehci_operational::portsc::R
• usb1::ehci_operational::portsc::W
• usb1::ehci_operational::usbcmd::R
• usb1::ehci_operational::usbcmd::USBCMD_SPEC
• usb1::ehci_operational::usbcmd::W
• usb1::ehci_operational::usbintr::R
• usb1::ehci_operational::usbintr::USBINTR_SPEC
• usb1::ehci_operational::usbintr::W
• usb1::ehci_operational::usbsts::R
• usb1::ehci_operational::usbsts::USBSTS_SPEC
• usb1::ehci_operational::usbsts::W
• usb1::hci_controller_phy_interface::hci_ctrl3::HCI_CTRL3_SPEC
• usb1::hci_controller_phy_interface::hci_ctrl3::R
• usb1::hci_controller_phy_interface::hci_ctrl3::W
• usb1::hci_controller_phy_interface::hci_interface::HCI_INTERFACE_SPEC
• usb1::hci_controller_phy_interface::hci_interface::R
• usb1::hci_controller_phy_interface::hci_interface::W
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::HCI_SIE_PORT_DISABLE_CONTROL_SPEC
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::R
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::W
• usb1::hci_controller_phy_interface::phy_control::PHY_CONTROL_SPEC
• usb1::hci_controller_phy_interface::phy_control::R
• usb1::hci_controller_phy_interface::phy_control::W
• usb1::hci_controller_phy_interface::phy_status::PHY_STATUS_SPEC
• usb1::hci_controller_phy_interface::phy_status::R
• usb1::ohci_control_status_partition::hc_command_status::HC_COMMAND_STATUS_SPEC
• usb1::ohci_control_status_partition::hc_command_status::R
• usb1::ohci_control_status_partition::hc_command_status::W
• usb1::ohci_control_status_partition::hc_control::HC_CONTROL_SPEC
• usb1::ohci_control_status_partition::hc_control::R
• usb1::ohci_control_status_partition::hc_control::W
• usb1::ohci_control_status_partition::hc_interrupt_disable::HC_INTERRUPT_DISABLE_SPEC
• usb1::ohci_control_status_partition::hc_interrupt_disable::R
• usb1::ohci_control_status_partition::hc_interrupt_disable::W
• usb1::ohci_control_status_partition::hc_interrupt_enable::HC_INTERRUPT_ENABLE_SPEC
• usb1::ohci_control_status_partition::hc_interrupt_enable::R
• usb1::ohci_control_status_partition::hc_interrupt_enable::W
• usb1::ohci_control_status_partition::hc_interrupt_status::HC_INTERRUPT_STATUS_SPEC
• usb1::ohci_control_status_partition::hc_interrupt_status::R
• usb1::ohci_control_status_partition::hc_interrupt_status::W
• usb1::ohci_frame_counter_partition::hc_fm_interval::HC_FM_INTERVAL_SPEC
• usb1::ohci_frame_counter_partition::hc_fm_interval::R
• usb1::ohci_frame_counter_partition::hc_fm_interval::W
• usb1::ohci_frame_counter_partition::hc_fm_number::HC_FM_NUMBER_SPEC
• usb1::ohci_frame_counter_partition::hc_fm_number::R
• usb1::ohci_frame_counter_partition::hc_fm_number::W
• usb1::ohci_frame_counter_partition::hc_fm_remaining::HC_FM_REMAINING_SPEC
• usb1::ohci_frame_counter_partition::hc_fm_remaining::R
• usb1::ohci_frame_counter_partition::hc_fm_remaining::W
• usb1::ohci_frame_counter_partition::hc_ls_threshold::HC_LS_THRESHOLD_SPEC
• usb1::ohci_frame_counter_partition::hc_ls_threshold::R
• usb1::ohci_frame_counter_partition::hc_ls_threshold::W
• usb1::ohci_frame_counter_partition::hc_periodic_start::HC_PERIODIC_START_SPEC
• usb1::ohci_frame_counter_partition::hc_periodic_start::R
• usb1::ohci_frame_counter_partition::hc_periodic_start::W
• usb1::ohci_memory_pointer_partition::hc_bulk_current_ed::HC_BULK_CURRENT_ED_SPEC
• usb1::ohci_memory_pointer_partition::hc_bulk_current_ed::R
• usb1::ohci_memory_pointer_partition::hc_bulk_current_ed::W
• usb1::ohci_memory_pointer_partition::hc_bulk_head_ed::HC_BULK_HEAD_ED_SPEC
• usb1::ohci_memory_pointer_partition::hc_bulk_head_ed::R
• usb1::ohci_memory_pointer_partition::hc_bulk_head_ed::W
• usb1::ohci_memory_pointer_partition::hc_control_current_ed::HC_CONTROL_CURRENT_ED_SPEC
• usb1::ohci_memory_pointer_partition::hc_control_current_ed::R
• usb1::ohci_memory_pointer_partition::hc_control_current_ed::W
• usb1::ohci_memory_pointer_partition::hc_control_head_ed::HC_CONTROL_HEAD_ED_SPEC
• usb1::ohci_memory_pointer_partition::hc_control_head_ed::R
• usb1::ohci_memory_pointer_partition::hc_control_head_ed::W
• usb1::ohci_memory_pointer_partition::hc_done_head::HC_DONE_HEAD_SPEC
• usb1::ohci_memory_pointer_partition::hc_done_head::R
• usb1::ohci_memory_pointer_partition::hc_done_head::W
• usb1::ohci_memory_pointer_partition::hc_hcca::HC_HCCA_SPEC
• usb1::ohci_memory_pointer_partition::hc_hcca::R
• usb1::ohci_memory_pointer_partition::hc_hcca::W
• usb1::ohci_memory_pointer_partition::hc_period_current_ed::HC_PERIOD_CURRENT_ED_SPEC
• usb1::ohci_memory_pointer_partition::hc_period_current_ed::R
• usb1::ohci_memory_pointer_partition::hc_period_current_ed::W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::HC_RH_DESCRIPTOR_A_SPEC
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_b::HC_RH_DESCRIPTOR_B_SPEC
• usb1::ohci_root_hub_partition::hc_rh_descriptor_b::R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_b::W
• usb1::ohci_root_hub_partition::hc_rh_port_status::HC_RH_PORT_STATUS_SPEC
• usb1::ohci_root_hub_partition::hc_rh_port_status::R
• usb1::ohci_root_hub_partition::hc_rh_port_status::W
• usb1::ohci_root_hub_partition::hc_rh_status::HC_RH_STATUS_SPEC
• usb1::ohci_root_hub_partition::hc_rh_status::R
• usb1::ohci_root_hub_partition::hc_rh_status::W

Enums

• Interrupt
• ccu::apb_clk::CLK_SRC_SEL_A
• ccu::apb_clk::FACTOR_N_A
• ccu::audio_codec_adc_clk::CLK_GATING_A
• ccu::audio_codec_adc_clk::CLK_SRC_SEL_A
• ccu::audio_codec_adc_clk::FACTOR_N_A
• ccu::audio_codec_bgr::GATING_A
• ccu::audio_codec_bgr::RST_A
• ccu::audio_codec_dac_clk::CLK_GATING_A
• ccu::audio_codec_dac_clk::CLK_SRC_SEL_A
• ccu::audio_codec_dac_clk::FACTOR_N_A
• ccu::avs_clk::CLK_GATING_A
• ccu::ccu_fan::CLK_FANOUT_EN_A
• ccu::ccu_fan::CLK_FANOUT_SEL_A
• ccu::ccu_fan_gate::CLK12M_EN_A
• ccu::ccu_fan_gate::CLK16M_EN_A
• ccu::ccu_fan_gate::CLK24M_EN_A
• ccu::ccu_fan_gate::CLK25M_EN_A
• ccu::ccu_fan_gate::CLK32K_EN_A
• ccu::ce_bgr::GATING_A
• ccu::ce_bgr::RST_A
• ccu::ce_clk::CLK_GATING_A
• ccu::ce_clk::CLK_SRC_SEL_A
• ccu::ce_clk::FACTOR_N_A
• ccu::clk27m_fan::CLK_SRC_SEL_A
• ccu::clk27m_fan::GATING_A
• ccu::cpu_axi_cfg::CPU_CLK_SEL_A
• ccu::cpu_axi_cfg::PLL_CPU_OUT_EXT_DIVP_A
• ccu::cpu_gating::CPU_GATING_A
• ccu::csi_bgr::GATING_A
• ccu::csi_bgr::RST_A
• ccu::csi_clk::CLK_GATING_A
• ccu::csi_clk::CLK_SRC_SEL_A
• ccu::csi_master_clk::CLK_GATING_A
• ccu::csi_master_clk::CLK_SRC_SEL_A
• ccu::dbgsys_bgr::GATING_A
• ccu::dbgsys_bgr::RST_A
• ccu::de_bgr::GATING_A
• ccu::de_bgr::RST_A
• ccu::de_clk::CLK_GATING_A
• ccu::de_clk::CLK_SRC_SEL_A
• ccu::di_bgr::GATING_A
• ccu::di_bgr::RST_A
• ccu::di_clk::CLK_GATING_A
• ccu::di_clk::CLK_SRC_SEL_A
• ccu::dma_bgr::GATING_A
• ccu::dma_bgr::RST_A
• ccu::dmic_bgr::GATING_A
• ccu::dmic_bgr::RST_A
• ccu::dmic_clk::CLK_GATING_A
• ccu::dmic_clk::CLK_SRC_SEL_A
• ccu::dmic_clk::FACTOR_N_A
• ccu::dpss_top_bgr::GATING_A
• ccu::dpss_top_bgr::RST_A
• ccu::dram_bgr::GATING_A
• ccu::dram_bgr::RST_A
• ccu::dram_clk::CLK_GATING_A
• ccu::dram_clk::CLK_SRC_SEL_A
• ccu::dram_clk::DRAM_DIV2_A
• ccu::dram_clk::SDRCLK_UPD_A
• ccu::dsi_bgr::GATING_A
• ccu::dsi_bgr::RST_A
• ccu::dsi_clk::CLK_GATING_A
• ccu::dsi_clk::CLK_SRC_SEL_A
• ccu::dsp_bgr::CFG_GATING_A
• ccu::dsp_bgr::CFG_RST_A
• ccu::dsp_bgr::DBG_RST_A
• ccu::dsp_bgr::RST_A
• ccu::dsp_clk::CLK_GATING_A
• ccu::dsp_clk::CLK_SRC_SEL_A
• ccu::emac_25m_clk::CLK_GATING_A
• ccu::emac_25m_clk::CLK_SRC_GATING_A
• ccu::emac_bgr::GATING_A
• ccu::emac_bgr::RST_A
• ccu::fre_det_ctrl::ERROR_FLAG_A
• ccu::fre_det_ctrl::FRE_DET_FUN_EN_A
• ccu::fre_det_ctrl::FRE_DET_IRQ_EN_A
• ccu::g2d_bgr::GATING_A
• ccu::g2d_bgr::RST_A
• ccu::g2d_clk::CLK_GATING_A
• ccu::g2d_clk::CLK_SRC_SEL_A
• ccu::gpadc_bgr::GATING_A
• ccu::gpadc_bgr::RST_A
• ccu::hstimer_bgr::GATING_A
• ccu::hstimer_bgr::RST_A
• ccu::i2s2_asrc_clk::CLK_GATING_A
• ccu::i2s2_asrc_clk::CLK_SRC_SEL_A
• ccu::i2s2_asrc_clk::FACTOR_N_A
• ccu::i2s_bgr::I2S_GATING_A
• ccu::i2s_bgr::I2S_RST_A
• ccu::i2s_clk::CLK_GATING_A
• ccu::i2s_clk::CLK_SRC_SEL_A
• ccu::i2s_clk::FACTOR_N_A
• ccu::iommu_bgr::GATING_A
• ccu::irtx_bgr::GATING_A
• ccu::irtx_bgr::RST_A
• ccu::irtx_clk::CLK_GATING_A
• ccu::irtx_clk::CLK_SRC_SEL_A
• ccu::irtx_clk::FACTOR_N_A
• ccu::ledc_bgr::GATING_A
• ccu::ledc_bgr::RST_A
• ccu::ledc_clk::CLK_GATING_A
• ccu::ledc_clk::CLK_SRC_SEL_A
• ccu::ledc_clk::FACTOR_N_A
• ccu::lradc_bgr::GATING_A
• ccu::lradc_bgr::RST_A
• ccu::lvds_bgr::RST_A
• ccu::mbus_clk::MBUS_RST_A
• ccu::mbus_mat_clk_gating::CE_MCLK_EN_A
• ccu::mbus_mat_clk_gating::CSI_MCLK_EN_A
• ccu::mbus_mat_clk_gating::DMA_MCLK_EN_A
• ccu::mbus_mat_clk_gating::G2D_MCLK_EN_A
• ccu::mbus_mat_clk_gating::RISCV_MCLK_EN_A
• ccu::mbus_mat_clk_gating::TVIN_MCLK_EN_A
• ccu::mbus_mat_clk_gating::VE_MCLK_EN_A
• ccu::msgbox_bgr::MSGBOX_GATING_A
• ccu::msgbox_bgr::MSGBOX_RST_A
• ccu::owa_bgr::GATING_A
• ccu::owa_bgr::RST_A
• ccu::owa_rx_clk::CLK_GATING_A
• ccu::owa_rx_clk::CLK_SRC_SEL_A
• ccu::owa_rx_clk::FACTOR_N_A
• ccu::owa_tx_clk::CLK_GATING_A
• ccu::owa_tx_clk::CLK_SRC_SEL_A
• ccu::owa_tx_clk::FACTOR_N_A
• ccu::pclk_fan::GATING_A
• ccu::pll_audio0_ctrl::LOCK_A
• ccu::pll_audio0_ctrl::LOCK_ENABLE_A
• ccu::pll_audio0_ctrl::PLL_EN_A
• ccu::pll_audio0_ctrl::PLL_LDO_EN_A
• ccu::pll_audio0_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_audio0_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_audio0_ctrl::PLL_SDM_EN_A
• ccu::pll_audio0_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_audio0_pat0_ctrl::FREQ_A
• ccu::pll_audio0_pat0_ctrl::SDM_CLK_SEL_A
• ccu::pll_audio0_pat0_ctrl::SPR_FREQ_MODE_A
• ccu::pll_audio1_ctrl::LOCK_A
• ccu::pll_audio1_ctrl::LOCK_ENABLE_A
• ccu::pll_audio1_ctrl::PLL_EN_A
• ccu::pll_audio1_ctrl::PLL_LDO_EN_A
• ccu::pll_audio1_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_audio1_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_audio1_ctrl::PLL_SDM_EN_A
• ccu::pll_audio1_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_audio1_pat0_ctrl::FREQ_A
• ccu::pll_audio1_pat0_ctrl::SDM_CLK_SEL_A
• ccu::pll_audio1_pat0_ctrl::SPR_FREQ_MODE_A
• ccu::pll_cpu_ctrl::LOCK_A
• ccu::pll_cpu_ctrl::LOCK_ENABLE_A
• ccu::pll_cpu_ctrl::PLL_EN_A
• ccu::pll_cpu_ctrl::PLL_LDO_EN_A
• ccu::pll_cpu_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_cpu_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_cpu_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_ddr_ctrl::LOCK_A
• ccu::pll_ddr_ctrl::LOCK_ENABLE_A
• ccu::pll_ddr_ctrl::PLL_EN_A
• ccu::pll_ddr_ctrl::PLL_LDO_EN_A
• ccu::pll_ddr_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_ddr_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_ddr_ctrl::PLL_SDM_EN_A
• ccu::pll_ddr_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_ddr_pat0_ctrl::FREQ_A
• ccu::pll_ddr_pat0_ctrl::SDM_CLK_SEL_A
• ccu::pll_ddr_pat0_ctrl::SPR_FREQ_MODE_A
• ccu::pll_lock_dbg_ctrl::CLK_SRC_SEL_A
• ccu::pll_lock_dbg_ctrl::PLL_LOCK_FLAG_EN_A
• ccu::pll_peri_ctrl::LOCK_A
• ccu::pll_peri_ctrl::LOCK_ENABLE_A
• ccu::pll_peri_ctrl::PLL_EN_A
• ccu::pll_peri_ctrl::PLL_LDO_EN_A
• ccu::pll_peri_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_peri_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_peri_ctrl::PLL_SDM_EN_A
• ccu::pll_peri_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_peri_pat0_ctrl::FREQ_A
• ccu::pll_peri_pat0_ctrl::SDM_CLK_SEL_A
• ccu::pll_peri_pat0_ctrl::SPR_FREQ_MODE_A
• ccu::pll_ve_ctrl::LOCK_A
• ccu::pll_ve_ctrl::LOCK_ENABLE_A
• ccu::pll_ve_ctrl::PLL_EN_A
• ccu::pll_ve_ctrl::PLL_LDO_EN_A
• ccu::pll_ve_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_ve_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_ve_ctrl::PLL_SDM_EN_A
• ccu::pll_ve_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_ve_pat0_ctrl::FREQ_A
• ccu::pll_ve_pat0_ctrl::SDM_CLK_SEL_A
• ccu::pll_ve_pat0_ctrl::SPR_FREQ_MODE_A
• ccu::pll_video0_ctrl::LOCK_A
• ccu::pll_video0_ctrl::LOCK_ENABLE_A
• ccu::pll_video0_ctrl::PLL_EN_A
• ccu::pll_video0_ctrl::PLL_LDO_EN_A
• ccu::pll_video0_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_video0_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_video0_ctrl::PLL_SDM_EN_A
• ccu::pll_video0_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_video0_pat0_ctrl::FREQ_A
• ccu::pll_video0_pat0_ctrl::SDM_CLK_SEL_A
• ccu::pll_video0_pat0_ctrl::SPR_FREQ_MODE_A
• ccu::pll_video1_ctrl::LOCK_A
• ccu::pll_video1_ctrl::LOCK_ENABLE_A
• ccu::pll_video1_ctrl::PLL_EN_A
• ccu::pll_video1_ctrl::PLL_LDO_EN_A
• ccu::pll_video1_ctrl::PLL_LOCK_MDSEL_A
• ccu::pll_video1_ctrl::PLL_OUTPUT_GATE_A
• ccu::pll_video1_ctrl::PLL_SDM_EN_A
• ccu::pll_video1_ctrl::PLL_UNLOCK_MDSEL_A
• ccu::pll_video1_pat0_ctrl::FREQ_A
• ccu::pll_video1_pat0_ctrl::SDM_CLK_SEL_A
• ccu::pll_video1_pat0_ctrl::SPR_FREQ_MODE_A
• ccu::psi_clk::CLK_SRC_SEL_A
• ccu::psi_clk::FACTOR_N_A
• ccu::pwm_bgr::GATING_A
• ccu::pwm_bgr::RST_A
• ccu::riscv_cfg_bgr::GATING_A
• ccu::riscv_cfg_bgr::RST_A
• ccu::riscv_clk::CLK_SRC_SEL_A
• ccu::riscv_gating::GATING_A
• ccu::smhc0_clk::CLK_GATING_A
• ccu::smhc0_clk::CLK_SRC_SEL_A
• ccu::smhc0_clk::FACTOR_N_A
• ccu::smhc1_clk::CLK_GATING_A
• ccu::smhc1_clk::CLK_SRC_SEL_A
• ccu::smhc1_clk::FACTOR_N_A
• ccu::smhc2_clk::CLK_GATING_A
• ccu::smhc2_clk::CLK_SRC_SEL_A
• ccu::smhc2_clk::FACTOR_N_A
• ccu::smhc_bgr::SMHC_GATING_A
• ccu::smhc_bgr::SMHC_RST_A
• ccu::spi0_clk::CLK_GATING_A
• ccu::spi0_clk::CLK_SRC_SEL_A
• ccu::spi0_clk::FACTOR_N_A
• ccu::spi1_clk::CLK_GATING_A
• ccu::spi1_clk::CLK_SRC_SEL_A
• ccu::spi1_clk::FACTOR_N_A
• ccu::spi_bgr::SPI_GATING_A
• ccu::spi_bgr::SPI_RST_A
• ccu::spinlock_bgr::GATING_A
• ccu::spinlock_bgr::RST_A
• ccu::tconlcd_bgr::GATING_A
• ccu::tconlcd_bgr::RST_A
• ccu::tconlcd_clk::CLK_GATING_A
• ccu::tconlcd_clk::CLK_SRC_SEL_A
• ccu::tconlcd_clk::FACTOR_N_A
• ccu::tcontv_bgr::GATING_A
• ccu::tcontv_bgr::RST_A
• ccu::tcontv_clk::CLK_GATING_A
• ccu::tcontv_clk::CLK_SRC_SEL_A
• ccu::tcontv_clk::FACTOR_N_A
• ccu::ths_bgr::GATING_A
• ccu::ths_bgr::RST_A
• ccu::tpadc_bgr::GATING_A
• ccu::tpadc_bgr::RST_A
• ccu::tpadc_clk::CLK_GATING_A
• ccu::tpadc_clk::CLK_SRC_SEL_A
• ccu::tvd_bgr::GATING_A
• ccu::tvd_bgr::RST_A
• ccu::tvd_bgr::TOP_GATING_A
• ccu::tvd_bgr::TOP_RST_A
• ccu::tvd_clk::CLK_GATING_A
• ccu::tvd_clk::CLK_SRC_SEL_A
• ccu::tve_bgr::GATING_A
• ccu::tve_bgr::RST_A
• ccu::tve_bgr::TOP_GATING_A
• ccu::tve_bgr::TOP_RST_A
• ccu::tve_clk::CLK_GATING_A
• ccu::tve_clk::CLK_SRC_SEL_A
• ccu::tve_clk::FACTOR_N_A
• ccu::twi_bgr::TWI_GATING_A
• ccu::twi_bgr::TWI_RST_A
• ccu::uart_bgr::UART_GATING_A
• ccu::uart_bgr::UART_RST_A
• ccu::usb0_clk::CLK12M_SEL_A
• ccu::usb0_clk::CLKEN_A
• ccu::usb0_clk::RSTN_A
• ccu::usb1_clk::CLK12M_SEL_A
• ccu::usb1_clk::CLKEN_A
• ccu::usb1_clk::RSTN_A
• ccu::usb_bgr::USBEHCI_GATING_A
• ccu::usb_bgr::USBEHCI_RST_A
• ccu::usb_bgr::USBOHCI_GATING_A
• ccu::usb_bgr::USBOHCI_RST_A
• ccu::usb_bgr::USBOTG0_GATING_A
• ccu::usb_bgr::USBOTG0_RST_A
• ccu::ve_bgr::GATING_A
• ccu::ve_bgr::RST_A
• ccu::ve_clk::CLK_GATING_A
• ccu::ve_clk::CLK_SRC_SEL_A
• ce_ns::ce_esr::TASK_CHANNEL_ERROR_TYPE_A
• ce_ns::ce_icr::TASK_IRQ_EN_A
• ce_ns::ce_isr::TASK_PENDING_A
• ce_ns::ce_tsr::RUNNING_CHANNEL_NUMBER_A
• cir_rx::cir_ctl::APAM_A
• cir_rx::cir_ctl::CIREN_A
• cir_rx::cir_ctl::GEN_A
• cir_rx::cir_ctl::RXEN_A
• cir_rx::cir_rxcfg::ATHC_A
• cir_rx::cir_rxcfg::NTHR_A
• cir_rx::cir_rxint::DRQ_EN_A
• cir_rx::cir_rxint::RAI_EN_A
• cir_rx::cir_rxint::ROI_EN_A
• cir_rx::cir_rxint::RPEI_EN_A
• cir_rx::cir_rxpcfg::RPPI_A
• cir_rx::cir_rxsta::RAC_A
• cir_rx::cir_rxsta::RA_A
• cir_rx::cir_rxsta::ROI_A
• cir_rx::cir_rxsta::RPE_A
• cir_rx::cir_rxsta::STAT_A
• cir_tx::cir_dma_ctl::DMA_A
• cir_tx::cir_tac::TAC_A
• cir_tx::cir_tcr::CSS_A
• cir_tx::cir_tcr::RCS_A
• cir_tx::cir_tcr::TTS_A
• cir_tx::cir_tglr::DRMC_A
• cir_tx::cir_tglr::IMS_A
• cir_tx::cir_tglr::TPPI_A
• cir_tx::cir_tglr::TXEN_A
• cir_tx::cir_txint::DRQ_EN_A
• cir_tx::cir_txint::TAI_EN_A
• cir_tx::cir_txint::TPEI_TUI_EN_A
• cir_tx::cir_txsta::STCT_A
• cir_tx::cir_txsta::TAI_A
• cir_tx::cir_txsta::TPE_TUR_A
• dmac::dmac_auto_gate_reg::DMA_CHAN_CIRCUIT_A
• dmac::dmac_auto_gate_reg::DMA_COMMON_CIRCUIT_A
• dmac::dmac_auto_gate_reg::DMA_MCLK_CIRCUIT_A
• dmac::dmac_cfg_reg::BMODE_SEL_A
• dmac::dmac_cfg_reg::DMA_ADDR_MODE_A
• dmac::dmac_cfg_reg::DMA_DEST_BLOCK_SIZE_A
• dmac::dmac_cfg_reg::DMA_DEST_DATA_WIDTH_A
• dmac::dmac_cfg_reg::DMA_SRC_ADDR_MODE_A
• dmac::dmac_cfg_reg::DMA_SRC_BLOCK_SIZE_A
• dmac::dmac_cfg_reg::DMA_SRC_DATA_WIDTH_A
• dmac::dmac_en_reg::DMA_EN_A
• dmac::dmac_irq_en_reg0::DMA_HLAF_IRQ_EN_A
• dmac::dmac_irq_en_reg0::DMA_PKG_IRQ_EN_A
• dmac::dmac_irq_en_reg0::DMA_QUEUE_IRQ_EN_A
• dmac::dmac_irq_en_reg1::DMA_HLAF_IRQ_EN_A
• dmac::dmac_irq_en_reg1::DMA_PKG_IRQ_EN_A
• dmac::dmac_irq_en_reg1::DMA_QUEUE_IRQ_EN_A
• dmac::dmac_irq_pend_reg0::DMA_HLAF_IRQ_PEND_A
• dmac::dmac_irq_pend_reg0::DMA_PKG_IRQ_PEND_A
• dmac::dmac_irq_pend_reg0::DMA_QUEUE_IRQ_PEND_A
• dmac::dmac_irq_pend_reg1::DMA_HLAF_IRQ_PEND_A
• dmac::dmac_irq_pend_reg1::DMA_PKG_IRQ_PEND_A
• dmac::dmac_irq_pend_reg1::DMA_QUEUE_IRQ_PEND_A
• dmac::dmac_mode_reg::DMA_DST_MODE_A
• dmac::dmac_mode_reg::DMA_SRC_MODE_A
• dmac::dmac_pau_reg::DMA_PAUSE_A
• dmac::dmac_sta_reg::DMA_STATUS_A
• dmac::dmac_sta_reg::MBUS_FIFO_STATUS_A
• dsp_msgbox::msgbox::msgbox_fifo_status_reg::FIFO_NOT_AVA_FLAG_A
• dsp_msgbox::msgbox::msgbox_rd_irq_en_reg::RECEPTION_MQ_IRQ_EN_A
• dsp_msgbox::msgbox::msgbox_rd_irq_status_reg::RECEPTION_MQ_IRQ_PEND_A
• dsp_msgbox::msgbox::msgbox_wr_int_threshold_reg::MSG_WR_INT_THRESHOLD_CFG_A
• dsp_msgbox::msgbox::msgbox_wr_irq_en_reg::TRANSMIT_MQ_IRQ_EN_A
• dsp_msgbox::msgbox::msgbox_wr_irq_status_reg::TRANSMIT_MQ_IRQ_PEND_A
• emac::emac_addr_high::MAC_ADDR_CTL_A
• emac::emac_addr_high::MAC_ADDR_TYPE_A
• emac::emac_basic_ctl0::DUPLEX_A
• emac::emac_basic_ctl0::LOOPBACK_A
• emac::emac_basic_ctl0::SPEED_A
• emac::emac_basic_ctl1::RX_TX_PRI_A
• emac::emac_basic_ctl1::SOFT_RST_A
• emac::emac_int_en::RX_BUF_UA_INT_EN_A
• emac::emac_int_en::RX_DMA_STOPPED_INT_EN_A
• emac::emac_int_en::RX_EARLY_INT_EN_A
• emac::emac_int_en::RX_INT_EN_A
• emac::emac_int_en::RX_OVERFLOW_INT_EN_A
• emac::emac_int_en::RX_TIMEOUT_INT_EN_A
• emac::emac_int_en::TX_BUF_UA_INT_EN_A
• emac::emac_int_en::TX_DMA_STOPPED_INT_EN_A
• emac::emac_int_en::TX_EARLY_INT_EN_A
• emac::emac_int_en::TX_INT_EN_A
• emac::emac_int_en::TX_TIMEOUT_INT_EN_A
• emac::emac_int_en::TX_UNDERFLOW_INT_EN_A
• emac::emac_int_sta::RGMII_LINK_STA_P_A
• emac::emac_int_sta::RX_BUF_UA_P_A
• emac::emac_int_sta::RX_EARLY_P_A
• emac::emac_int_sta::RX_OVERFLOW_P_A
• emac::emac_int_sta::RX_P_A
• emac::emac_int_sta::RX_TIMEOUT_P_A
• emac::emac_int_sta::TX_BUF_UA_P_A
• emac::emac_int_sta::TX_DMA_STOPPED_P_A
• emac::emac_int_sta::TX_EARLY_P_A
• emac::emac_int_sta::TX_P_A
• emac::emac_int_sta::TX_TIMEOUT_P_A
• emac::emac_int_sta::TX_UNDERFLOW_P_A
• emac::emac_mii_cmd::MDC_DIV_RATIO_M_A
• emac::emac_mii_cmd::MII_WR_A
• emac::emac_rgmii_sta::RGMII_LINK_A
• emac::emac_rgmii_sta::RGMII_LINK_MD_A
• emac::emac_rgmii_sta::RGMII_LINK_SPD_A
• emac::emac_rx_ctl0::CHECK_CRC_A
• emac::emac_rx_ctl0::JUMBO_FRM_EN_A
• emac::emac_rx_ctl0::RX_EN_A
• emac::emac_rx_ctl0::RX_FRM_LEN_CTL_A
• emac::emac_rx_ctl0::RX_PAUSE_FRM_MD_A
• emac::emac_rx_ctl1::FLUSH_RX_FRM_A
• emac::emac_rx_ctl1::RX_EMA_EN_A
• emac::emac_rx_ctl1::RX_ERR_FRM_A
• emac::emac_rx_ctl1::RX_FIFO_FLOW_CTL_A
• emac::emac_rx_ctl1::RX_FLOW_CTL_TH_ACT_A
• emac::emac_rx_ctl1::RX_FLOW_CTL_TH_DEACT_A
• emac::emac_rx_ctl1::RX_MD_A
• emac::emac_rx_ctl1::RX_TH_A
• emac::emac_rx_dma_sta::RX_DMA_STA_A
• emac::emac_rx_frm_flt::CTL_FRM_FILTER_A
• emac::emac_rx_frm_flt::DA_INV_FILTER_A
• emac::emac_rx_frm_flt::DIS_ADDR_FILTER_A
• emac::emac_rx_frm_flt::DIS_BROADCAST_A
• emac::emac_rx_frm_flt::FLT_MD_A
• emac::emac_rx_frm_flt::HASH_MULTICAST_A
• emac::emac_rx_frm_flt::HASH_UNICAST_A
• emac::emac_rx_frm_flt::RX_ALL_A
• emac::emac_rx_frm_flt::RX_ALL_MULTICAST_A
• emac::emac_rx_frm_flt::SA_FILTER_EN_A
• emac::emac_rx_frm_flt::SA_INV_FILTER_A
• emac::emac_tx_ctl0::TX_EN_A
• emac::emac_tx_ctl0::TX_FRM_LEN_CTL_A
• emac::emac_tx_ctl1::FLUSH_TX_FIFO_A
• emac::emac_tx_ctl1::TX_DMA_EN_A
• emac::emac_tx_ctl1::TX_DMA_START_A
• emac::emac_tx_ctl1::TX_MD_A
• emac::emac_tx_ctl1::TX_TH_A
• emac::emac_tx_dma_sta::TX_DMA_STA_A
• emac::emac_tx_flow_ctl::TX_FLOW_CTL_EN_A
• emac::emac_tx_flow_ctl::ZQP_FRM_EN_A
• gpadc::gp_cs_en::ADC_CH_CMP_EN_A
• gpadc::gp_cs_en::ADC_CH_SELECT_A
• gpadc::gp_ctrl::ADC_CALI_EN_A
• gpadc::gp_ctrl::ADC_EN_A
• gpadc::gp_ctrl::GPADC_WORK_MODE_A
• gpadc::gp_data_intc::CH_DATA_IRQ_EN_A
• gpadc::gp_data_ints::CH_DATA_PENGDING_A
• gpadc::gp_datah_intc::CH_HIG_IRQ_EN_A
• gpadc::gp_datah_ints::CH_HIG_PENGDING_A
• gpadc::gp_datal_intc::CH_LOW_IRQ_EN_A
• gpadc::gp_datal_ints::CH_LOW_PENGDING_A
• gpadc::gp_fifo_intc::FIFO_DATA_DRQ_EN_A
• gpadc::gp_fifo_intc::FIFO_DATA_IRQ_EN_A
• gpadc::gp_fifo_intc::FIFO_OVERRUN_IRQ_EN_A
• gpadc::gp_fifo_ints::FIFO_DATA_PENDING_A
• gpadc::gp_fifo_ints::FIFO_OVERRUN_PENDING_A
• gpio::pb_cfg0::PB0_SELECT_A
• gpio::pb_cfg0::PB1_SELECT_A
• gpio::pb_cfg0::PB2_SELECT_A
• gpio::pb_cfg0::PB3_SELECT_A
• gpio::pb_cfg0::PB4_SELECT_A
• gpio::pb_cfg0::PB5_SELECT_A
• gpio::pb_cfg0::PB6_SELECT_A
• gpio::pb_cfg0::PB7_SELECT_A
• gpio::pb_cfg1::PB10_SELECT_A
• gpio::pb_cfg1::PB11_SELECT_A
• gpio::pb_cfg1::PB12_SELECT_A
• gpio::pb_cfg1::PB8_SELECT_A
• gpio::pb_cfg1::PB9_SELECT_A
• gpio::pb_drv0::PB_DRV_A
• gpio::pb_drv1::PB_DRV_A
• gpio::pb_eint_cfg0::EINT_CFG_A
• gpio::pb_eint_cfg1::EINT_CFG_A
• gpio::pb_eint_ctl::EINT_CTL_A
• gpio::pb_eint_deb::PIO_INT_CLK_SELECT_A
• gpio::pb_eint_status::EINT_STATUS_A
• gpio::pb_pull0::PC_PULL_A
• gpio::pc_cfg0::PC0_SELECT_A
• gpio::pc_cfg0::PC1_SELECT_A
• gpio::pc_cfg0::PC2_SELECT_A
• gpio::pc_cfg0::PC3_SELECT_A
• gpio::pc_cfg0::PC4_SELECT_A
• gpio::pc_cfg0::PC5_SELECT_A
• gpio::pc_cfg0::PC6_SELECT_A
• gpio::pc_cfg0::PC7_SELECT_A
• gpio::pc_drv0::PC_DRV_A
• gpio::pc_eint_cfg0::EINT_CFG_A
• gpio::pc_eint_ctl::EINT_CTL_A
• gpio::pc_eint_deb::PIO_INT_CLK_SELECT_A
• gpio::pc_eint_status::EINT_STATUS_A
• gpio::pc_pull0::PC_PULL_A
• gpio::pd_cfg0::PD0_SELECT_A
• gpio::pd_cfg0::PD1_SELECT_A
• gpio::pd_cfg0::PD2_SELECT_A
• gpio::pd_cfg0::PD3_SELECT_A
• gpio::pd_cfg0::PD4_SELECT_A
• gpio::pd_cfg0::PD5_SELECT_A
• gpio::pd_cfg0::PD6_SELECT_A
• gpio::pd_cfg0::PD7_SELECT_A
• gpio::pd_cfg1::PD10_SELECT_A
• gpio::pd_cfg1::PD11_SELECT_A
• gpio::pd_cfg1::PD12_SELECT_A
• gpio::pd_cfg1::PD13_SELECT_A
• gpio::pd_cfg1::PD14_SELECT_A
• gpio::pd_cfg1::PD15_SELECT_A
• gpio::pd_cfg1::PD8_SELECT_A
• gpio::pd_cfg1::PD9_SELECT_A
• gpio::pd_cfg2::PD16_SELECT_A
• gpio::pd_cfg2::PD17_SELECT_A
• gpio::pd_cfg2::PD18_SELECT_A
• gpio::pd_cfg2::PD19_SELECT_A
• gpio::pd_cfg2::PD20_SELECT_A
• gpio::pd_cfg2::PD21_SELECT_A
• gpio::pd_cfg2::PD22_SELECT_A
• gpio::pd_drv0::PD_DRV_A
• gpio::pd_drv1::PD_DRV_A
• gpio::pd_drv2::PD_DRV_A
• gpio::pd_eint_cfg0::EINT_CFG_A
• gpio::pd_eint_cfg1::EINT_CFG_A
• gpio::pd_eint_cfg2::EINT_CFG_A
• gpio::pd_eint_ctl::EINT_CTL_A
• gpio::pd_eint_deb::PIO_INT_CLK_SELECT_A
• gpio::pd_eint_status::EINT_STATUS_A
• gpio::pd_pull0::PD_PULL_A
• gpio::pd_pull1::PD_PULL_A
• gpio::pe_cfg0::PE0_SELECT_A
• gpio::pe_cfg0::PE1_SELECT_A
• gpio::pe_cfg0::PE2_SELECT_A
• gpio::pe_cfg0::PE3_SELECT_A
• gpio::pe_cfg0::PE4_SELECT_A
• gpio::pe_cfg0::PE5_SELECT_A
• gpio::pe_cfg0::PE6_SELECT_A
• gpio::pe_cfg0::PE7_SELECT_A
• gpio::pe_cfg1::PE10_SELECT_A
• gpio::pe_cfg1::PE11_SELECT_A
• gpio::pe_cfg1::PE12_SELECT_A
• gpio::pe_cfg1::PE13_SELECT_A
• gpio::pe_cfg1::PE14_SELECT_A
• gpio::pe_cfg1::PE15_SELECT_A
• gpio::pe_cfg1::PE8_SELECT_A
• gpio::pe_cfg1::PE9_SELECT_A
• gpio::pe_cfg2::PE16_SELECT_A
• gpio::pe_cfg2::PE17_SELECT_A
• gpio::pe_drv0::PE_DRV_A
• gpio::pe_drv1::PE_DRV_A
• gpio::pe_drv2::PE_DRV_A
• gpio::pe_eint_cfg0::EINT_CFG_A
• gpio::pe_eint_cfg1::EINT_CFG_A
• gpio::pe_eint_cfg2::EINT_CFG_A
• gpio::pe_eint_ctl::EINT_CTL_A
• gpio::pe_eint_deb::PIO_INT_CLK_SELECT_A
• gpio::pe_eint_status::EINT_STATUS_A
• gpio::pe_pull0::PE_PULL_A
• gpio::pe_pull1::PE_PULL_A
• gpio::pf_cfg0::PF0_SELECT_A
• gpio::pf_cfg0::PF1_SELECT_A
• gpio::pf_cfg0::PF2_SELECT_A
• gpio::pf_cfg0::PF3_SELECT_A
• gpio::pf_cfg0::PF4_SELECT_A
• gpio::pf_cfg0::PF5_SELECT_A
• gpio::pf_cfg0::PF6_SELECT_A
• gpio::pf_drv0::PF_DRV_A
• gpio::pf_eint_cfg0::EINT_CFG_A
• gpio::pf_eint_ctl::EINT_CTL_A
• gpio::pf_eint_deb::PIO_INT_CLK_SELECT_A
• gpio::pf_eint_status::EINT_STATUS_A
• gpio::pf_pull0::PF_PULL_A
• gpio::pg_cfg0::PG0_SELECT_A
• gpio::pg_cfg0::PG1_SELECT_A
• gpio::pg_cfg0::PG2_SELECT_A
• gpio::pg_cfg0::PG3_SELECT_A
• gpio::pg_cfg0::PG4_SELECT_A
• gpio::pg_cfg0::PG5_SELECT_A
• gpio::pg_cfg0::PG6_SELECT_A
• gpio::pg_cfg0::PG7_SELECT_A
• gpio::pg_cfg1::PG10_SELECT_A
• gpio::pg_cfg1::PG11_SELECT_A
• gpio::pg_cfg1::PG12_SELECT_A
• gpio::pg_cfg1::PG13_SELECT_A
• gpio::pg_cfg1::PG14_SELECT_A
• gpio::pg_cfg1::PG15_SELECT_A
• gpio::pg_cfg1::PG8_SELECT_A
• gpio::pg_cfg1::PG9_SELECT_A
• gpio::pg_cfg2::PG16_SELECT_A
• gpio::pg_cfg2::PG17_SELECT_A
• gpio::pg_cfg2::PG18_SELECT_A
• gpio::pg_drv0::PG_DRV_A
• gpio::pg_drv1::PG_DRV_A
• gpio::pg_drv2::PG_DRV_A
• gpio::pg_eint_cfg0::EINT_CFG_A
• gpio::pg_eint_cfg1::EINT_CFG_A
• gpio::pg_eint_cfg2::EINT_CFG_A
• gpio::pg_eint_ctl::EINT_CTL_A
• gpio::pg_eint_deb::PIO_INT_CLK_SELECT_A
• gpio::pg_eint_status::EINT_STATUS_A
• gpio::pg_pull0::PG_PULL_A
• gpio::pg_pull1::PG_PULL_A
• gpio::pio_pow_mod_sel::P_PWR_MOD_SEL_A
• gpio::pio_pow_mod_sel::VCC_IO_PWR_MOD_SEL_A
• gpio::pio_pow_ms_ctl::VCCIO_WS_VOL_MOD_SEL_A
• gpio::pio_pow_ms_ctl::VCC_P_WS_VOL_MOD_SEL_A
• gpio::pio_pow_vol_sel_ctl::VCC_PF_PWR_VOL_SEL_A
• hstimer::hs_tmr_ctrl::HS_TMR_CLK_A
• hstimer::hs_tmr_ctrl::HS_TMR_EN_A
• hstimer::hs_tmr_ctrl::HS_TMR_MODE_A
• hstimer::hs_tmr_ctrl::HS_TMR_RELOAD_A
• hstimer::hs_tmr_ctrl::HS_TMR_TEST_A
• hstimer::hs_tmr_irq_en::HS_TMR_INT_EN_A
• hstimer::hs_tmr_irq_stas::HS_TMR_IRQ_PEND_A
• ledc::ledc_ctrl::LEDC_EN_A
• ledc::ledc_ctrl::LED_MSB__A
• ledc::ledc_ctrl::LED_RGB_MODE_A
• ledc::ledc_dma_ctrl::LEDC_DMA_EN_A
• ledc::ledc_int_ctrl::FIFO_CPUREQ_INT_EN_A
• ledc::ledc_int_ctrl::FIFO_OVERFLOW_INT_EN_A
• ledc::ledc_int_ctrl::GLOBAL_INT_EN_A
• ledc::ledc_int_ctrl::LED_TRANS_FINISH_INT_EN_A
• ledc::ledc_int_ctrl::WAITDATA_TIMEOUT_INT_EN_A
• ledc::ledc_int_sts::FIFO_CPUREQ_INT_A
• ledc::ledc_int_sts::FIFO_OVERFLOW_INT_A
• ledc::ledc_int_sts::LEC_TRANS_FINISH_INT_A
• ledc::ledc_int_sts::WAITDATA_TIMEOUT_INT_A
• ledc::ledc_wait_time0_ctrl::WAIT_TIM0_EN_A
• ledc::ledc_wait_time1_ctrl::WAIT_TIM1_EN_A
• lradc::lradc_ctrl::KEY_MODE_SELECT_A
• lradc::lradc_ctrl::LEVELB_VOL_A
• lradc::lradc_ctrl::LRADC_CHANNEL_EN_A
• lradc::lradc_ctrl::LRADC_EN_A
• lradc::lradc_ctrl::LRADC_HOLD_KEY_EN_A
• lradc::lradc_ctrl::LRADC_SAMPLE_RATE_A
• lradc::lradc_intc::ADC0_ALRDY_HOLD_IRQ_EN_A
• lradc::lradc_intc::ADC0_DATA_IRQ_EN_A
• lradc::lradc_intc::ADC0_HOLD_IRQ_EN_A
• lradc::lradc_intc::ADC0_KEYDOWN_IRQ_EN_A
• lradc::lradc_intc::ADC0_KEYUP_IRQ_EN_A
• lradc::lradc_ints::ADC0_ALRDY_HOLD_PENDING_A
• lradc::lradc_ints::ADC0_DATA_PENDING_A
• lradc::lradc_ints::ADC0_HOLD_PENDING_A
• lradc::lradc_ints::ADC0_KEYDOWN_PENDING_A
• lradc::lradc_ints::ADC0_KEYUP_PENDING_A
• plic::ctrl::CTRL_A
• plic::mth::PRIORITY_A
• plic::prio::PRIORITY_A
• plic::sth::PRIORITY_A
• pwm::ccr::CAPINV_A
• pwm::cer::CAP_EN_A
• pwm::cier::CFIE_A
• pwm::cier::CRIE_A
• pwm::cisr::CFIS_A
• pwm::cisr::CRIS_A
• pwm::pccr01::PWM01_CLK_DIV_M_A
• pwm::pccr01::PWM01_CLK_SRC_A
• pwm::pccr23::PWM23_CLK_DIV_M_A
• pwm::pccr23::PWM23_CLK_SRC_SEL_A
• pwm::pccr45::PWM45_CLK_DIV_M_A
• pwm::pccr45::PWM45_CLK_SRC_SEL_A
• pwm::pccr67::PWM67_CLK_DIV_M_A
• pwm::pccr67::PWM67_CLK_SRC_SEL_A
• pwm::pcgr::PWM_CLK_BYPASS_A
• pwm::pcgr::PWM_CLK_GATING_A
• pwm::pcr::PWM_ACT_STA_A
• pwm::pcr::PWM_MODE_A
• pwm::pcr::PWM_PERIOD_RDY_A
• pwm::pcr::PWM_PUL_START_A
• pwm::pdzcr01::PWM01_DZ_EN_A
• pwm::pdzcr23::PWM23_DZ_EN_A
• pwm::pdzcr45::PWM45_DZ_EN_A
• pwm::pdzcr67::PWM67_DZ_EN_A
• pwm::per::PWM_EN_A
• pwm::pier::PCIE_A
• pwm::pier::PGIE_A
• pwm::pisr::PIS_A
• smhc::emmc_ddr_sbit_det::HALF_START_BIT_A
• smhc::emmc_ddr_sbit_det::HS400_MD_EN_A
• smhc::smhc_clkdiv::CCLK_CTRL_A
• smhc::smhc_clkdiv::CCLK_ENB_A
• smhc::smhc_clkdiv::MASK_DATA0_A
• smhc::smhc_cmd::BOOT_MOD_A
• smhc::smhc_cmd::CHK_RESP_CRC_A
• smhc::smhc_cmd::DATA_TRANS_A
• smhc::smhc_cmd::LONG_RESP_A
• smhc::smhc_cmd::PRG_CLK_A
• smhc::smhc_cmd::RESP_RCV_A
• smhc::smhc_cmd::SEND_INIT_SEQ_A
• smhc::smhc_cmd::STOP_ABT_CMD_A
• smhc::smhc_cmd::STOP_CMD_FLAG_A
• smhc::smhc_cmd::TRANS_DIR_A
• smhc::smhc_cmd::TRANS_MODE_A
• smhc::smhc_cmd::VOL_SW_A
• smhc::smhc_cmd::WAIT_PRE_OVER_A
• smhc::smhc_csdc::CRC_DET_PARA_A
• smhc::smhc_ctrl::CD_DBC_ENB_A
• smhc::smhc_ctrl::DDR_MOD_SEL_A
• smhc::smhc_ctrl::DMA_ENB_A
• smhc::smhc_ctrl::FIFO_AC_MOD_A
• smhc::smhc_ctrl::FIFO_RST_A
• smhc::smhc_ctrl::INE_ENB_A
• smhc::smhc_ctrl::SOFT_RST_A
• smhc::smhc_ctrl::TIME_UNIT_CMD_A
• smhc::smhc_ctrl::TIME_UNIT_DAT_A
• smhc::smhc_ctype::CARD_WID_A
• smhc::smhc_fifoth::BSIZE_OF_TRANS_A
• smhc::smhc_funs::ABT_RDATA_A
• smhc::smhc_funs::HOST_SEND_MIMC_IRQRESQ_A
• smhc::smhc_funs::READ_WAIT_A
• smhc::smhc_hwrst::HW_RST_A
• smhc::smhc_idst::IDMAC_ERR_STA_A
• smhc::smhc_ntsr::CMD_DAT_RX_PHASE_CLR_A
• smhc::smhc_ntsr::CMD_SAMPLE_TIMING_PHASE_A
• smhc::smhc_ntsr::CMD_SEND_RX_PHASE_CLR_A
• smhc::smhc_ntsr::DAT_CRC_STATUS_RX_PHASE_CLR_A
• smhc::smhc_ntsr::DAT_RECV_RX_PHASE_CLR_A
• smhc::smhc_ntsr::DAT_SAMPLE_TIMING_PHASE_A
• smhc::smhc_ntsr::DAT_TRANS_RX_PHASE_CLR_A
• smhc::smhc_ntsr::HS400_NEW_SAMPLE_EN_A
• smhc::smhc_ntsr::MODE_SELECT_A
• smhc::smhc_status::CARD_BUSY_A
• smhc::smhc_status::CARD_PRESENT_A
• smhc::smhc_status::FIFO_EMPTY_A
• smhc::smhc_status::FIFO_FULL_A
• smhc::smhc_status::FIFO_RX_LEVEL_A
• smhc::smhc_status::FIFO_TX_LEVEL_A
• smhc::smhc_status::FSM_STA_A
• smhc::smhc_thld::BCIG_A
• smhc::smhc_thld::CARD_RD_THLD_ENB_A
• smhc::smhc_thld::CARD_WR_THLD_ENB_A
• spi0::spi_batc::MSMS_A
• spi0::spi_batc::SPOL_A
• spi0::spi_batc::SS_LEVEL_A
• spi0::spi_batc::SS_OWNER_A
• spi0::spi_batc::SS_SEL_A
• spi0::spi_batc::TBC_A
• spi0::spi_batc::TBC_INT_EN_A
• spi0::spi_batc::TCE_A
• spi0::spi_batc::WMS_A
• spi0::spi_bcc::DRM_A
• spi0::spi_bcc::QUAD_EN_A
• spi0::spi_fcr::RF_DRQ_EN_A
• spi0::spi_fcr::RF_TEST_EN_A
• spi0::spi_fcr::TF_DRQ_EN_A
• spi0::spi_fcr::TF_TEST_EN_A
• spi0::spi_gcr::EN_A
• spi0::spi_gcr::MODE_A
• spi0::spi_gcr::MODE_SELEC_A
• spi0::spi_gcr::TP_EN_A
• spi0::spi_ier::RF_EMP_INT_EN_A
• spi0::spi_ier::RF_FULL_INT_EN_A
• spi0::spi_ier::RF_OVF_INT_EN_A
• spi0::spi_ier::RF_RDY_INT_EN_A
• spi0::spi_ier::RF_UDR_INT_EN_A
• spi0::spi_ier::SS_INT_EN_A
• spi0::spi_ier::TC_INT_EN_A
• spi0::spi_ier::TF_EMP_INT_EN_A
• spi0::spi_ier::TF_ERQ_INT_EN_A
• spi0::spi_ier::TF_FULL_INT_EN_A
• spi0::spi_ier::TF_OVF_INT_EN_A
• spi0::spi_ier::TF_UDR_INT_EN_A
• spi0::spi_isr::RF_EMP_A
• spi0::spi_isr::RF_FULL_A
• spi0::spi_isr::RF_OVF_A
• spi0::spi_isr::RF_UDR_A
• spi0::spi_isr::TC_A
• spi0::spi_isr::TF_EMP_A
• spi0::spi_isr::TF_FULL_A
• spi0::spi_isr::TF_OVF_A
• spi0::spi_isr::TF_UDR_A
• spi0::spi_ndma_mode_ctl::SPI_ACK_M_A
• spi0::spi_ndma_mode_ctl::SPI_ACT_M_A
• spi0::spi_tcr::CPHA_A
• spi0::spi_tcr::CPOL_A
• spi0::spi_tcr::DDB_A
• spi0::spi_tcr::DHB_A
• spi0::spi_tcr::FBS_A
• spi0::spi_tcr::RPSM_A
• spi0::spi_tcr::SDC1_A
• spi0::spi_tcr::SDC_A
• spi0::spi_tcr::SDDM_A
• spi0::spi_tcr::SDM_A
• spi0::spi_tcr::SPOL_A
• spi0::spi_tcr::SSCTL_A
• spi0::spi_tcr::SS_LEVEL_A
• spi0::spi_tcr::SS_OWNER_A
• spi0::spi_tcr::SS_SEL_A
• spi0::spi_tcr::XCH_A
• spi_dbi::dbi_ctl_0::CMDT_A
• spi_dbi::dbi_ctl_0::DAT_FMT_A
• spi_dbi::dbi_ctl_0::DAT_SEQ_A
• spi_dbi::dbi_ctl_0::DBI_INTERFACE_A
• spi_dbi::dbi_ctl_0::ELEMENT_A_POS_A
• spi_dbi::dbi_ctl_0::RGB_BO_A
• spi_dbi::dbi_ctl_0::RGB_SEQ_A
• spi_dbi::dbi_ctl_0::RGB_SRC_FMT_A
• spi_dbi::dbi_ctl_0::TRAN_MOD_A
• spi_dbi::dbi_ctl_0::VI_SRC_TYPE_A
• spi_dbi::dbi_ctl_1::DBI_CLKO_MOD_A
• spi_dbi::dbi_ctl_1::DBI_EN_MODE_SEL_A
• spi_dbi::dbi_ctl_1::DBI_RXCLK_INV_A
• spi_dbi::dbi_ctl_1::RGB666_FMT_A
• spi_dbi::dbi_ctl_2::DBI_SDI_SEL_A
• spi_dbi::dbi_timer::DBI_TM_EN_A
• spi_dbi::spi_batc::MSMS_A
• spi_dbi::spi_batc::SPOL_A
• spi_dbi::spi_batc::SS_LEVEL_A
• spi_dbi::spi_batc::SS_OWNER_A
• spi_dbi::spi_batc::SS_SEL_A
• spi_dbi::spi_batc::TBC_A
• spi_dbi::spi_batc::TBC_INT_EN_A
• spi_dbi::spi_batc::TCE_A
• spi_dbi::spi_batc::WMS_A
• spi_dbi::spi_bcc::DRM_A
• spi_dbi::spi_bcc::QUAD_EN_A
• spi_dbi::spi_fcr::RF_DRQ_EN_A
• spi_dbi::spi_fcr::RF_TEST_EN_A
• spi_dbi::spi_fcr::TF_DRQ_EN_A
• spi_dbi::spi_fcr::TF_TEST_EN_A
• spi_dbi::spi_gcr::EN_A
• spi_dbi::spi_gcr::MODE_A
• spi_dbi::spi_gcr::MODE_SELEC_A
• spi_dbi::spi_gcr::TP_EN_A
• spi_dbi::spi_ier::RF_EMP_INT_EN_A
• spi_dbi::spi_ier::RF_FULL_INT_EN_A
• spi_dbi::spi_ier::RF_OVF_INT_EN_A
• spi_dbi::spi_ier::RF_RDY_INT_EN_A
• spi_dbi::spi_ier::RF_UDR_INT_EN_A
• spi_dbi::spi_ier::SS_INT_EN_A
• spi_dbi::spi_ier::TC_INT_EN_A
• spi_dbi::spi_ier::TF_EMP_INT_EN_A
• spi_dbi::spi_ier::TF_ERQ_INT_EN_A
• spi_dbi::spi_ier::TF_FULL_INT_EN_A
• spi_dbi::spi_ier::TF_OVF_INT_EN_A
• spi_dbi::spi_ier::TF_UDR_INT_EN_A
• spi_dbi::spi_isr::RF_EMP_A
• spi_dbi::spi_isr::RF_FULL_A
• spi_dbi::spi_isr::RF_OVF_A
• spi_dbi::spi_isr::RF_UDR_A
• spi_dbi::spi_isr::TC_A
• spi_dbi::spi_isr::TF_EMP_A
• spi_dbi::spi_isr::TF_FULL_A
• spi_dbi::spi_isr::TF_OVF_A
• spi_dbi::spi_isr::TF_UDR_A
• spi_dbi::spi_ndma_mode_ctl::SPI_ACK_M_A
• spi_dbi::spi_ndma_mode_ctl::SPI_ACT_M_A
• spi_dbi::spi_tcr::CPHA_A
• spi_dbi::spi_tcr::CPOL_A
• spi_dbi::spi_tcr::DDB_A
• spi_dbi::spi_tcr::DHB_A
• spi_dbi::spi_tcr::FBS_A
• spi_dbi::spi_tcr::RPSM_A
• spi_dbi::spi_tcr::SDC1_A
• spi_dbi::spi_tcr::SDC_A
• spi_dbi::spi_tcr::SDDM_A
• spi_dbi::spi_tcr::SDM_A
• spi_dbi::spi_tcr::SPOL_A
• spi_dbi::spi_tcr::SSCTL_A
• spi_dbi::spi_tcr::SS_LEVEL_A
• spi_dbi::spi_tcr::SS_OWNER_A
• spi_dbi::spi_tcr::SS_SEL_A
• spi_dbi::spi_tcr::XCH_A
• spinlock::spinlock_irq_en_reg::LOCK_IRQ_EN_A
• spinlock::spinlock_irq_sta_reg::LOCK_IRQ_STATUS_A
• spinlock::spinlock_lock_reg::TAKEN_A
• spinlock::spinlock_status_reg::LOCK_REG_STATUS_A
• spinlock::spinlock_systatus_reg::IU0_A
• spinlock::spinlock_systatus_reg::LOCKS_NUM_A
• sys_cfg::dsp_boot_rammap::DSP_BOOT_SRAM_REMAP_ENABLE_A
• sys_cfg::emac_ephy_clk0::CLK_SEL_A
• sys_cfg::emac_ephy_clk0::EPHY_MODE_A
• sys_cfg::emac_ephy_clk0::EPIT_A
• sys_cfg::emac_ephy_clk0::ERXIE_A
• sys_cfg::emac_ephy_clk0::ETCS_A
• sys_cfg::emac_ephy_clk0::ETXIE_A
• sys_cfg::emac_ephy_clk0::LED_POL_A
• sys_cfg::emac_ephy_clk0::PHY_SELECT_A
• sys_cfg::emac_ephy_clk0::RMII_EN_A
• sys_cfg::emac_ephy_clk0::SHUTDOWN_A
• sys_cfg::emac_ephy_clk0::XMII_SEL_A
• sys_cfg::rescal_ctrl::CAL_ANA_EN_A
• sys_cfg::rescal_ctrl::CAL_EN_A
• sys_cfg::rescal_ctrl::DDR_RES240_TRIMMING_SEL_A
• sys_cfg::rescal_ctrl::RESCAL_MODE_A
• sys_cfg::sys_ldo_ctrl::LDOA_TRIM_A
• sys_cfg::sys_ldo_ctrl::LDOB_TRIM_A
• sys_cfg::ver::FEL_SEL_PAD_STA_A
• ths::ths_alarm_intc::ALARM_INT_EN_A
• ths::ths_alarm_ints::ALARM_INT_STS_A
• ths::ths_alarmo_ints::ALARM_OFF_STS_A
• ths::ths_data_intc::THS_DATA_IRQ_EN_A
• ths::ths_data_ints::THS_DATA_IRQ_STS_A
• ths::ths_en::THS_EN_A
• ths::ths_filter::FILTER_EN_A
• ths::ths_filter::FILTER_TYPE_A
• ths::ths_shut_intc::SHUT_INT_EN_A
• ths::ths_shut_ints::SHUT_INT_STS_A
• timer::avs_cnt_ctl::AVS_CNT_EN_A
• timer::avs_cnt_ctl::AVS_CNT_PS_A
• timer::tmr_ctrl::TMR_CLK_PRES_A
• timer::tmr_ctrl::TMR_CLK_SRC_A
• timer::tmr_ctrl::TMR_EN_A
• timer::tmr_ctrl::TMR_MODE_A
• timer::tmr_ctrl::TMR_RELOAD_A
• timer::tmr_irq_en::TMR0_IRQ_EN_A
• timer::tmr_irq_en::TMR1_IRQ_EN_A
• timer::tmr_irq_sta::TMR0_IRQ_PEND_A
• timer::tmr_irq_sta::TMR1_IRQ_PEND_A
• timer::wdog_cfg::WDOG_CLK_SRC_A
• timer::wdog_cfg::WDOG_MODE_A
• timer::wdog_ctrl::WDOG_RESTART_A
• timer::wdog_irq_en::WDOG_IRQ_EN_A
• timer::wdog_irq_sta::WDOG_IRQ_PEND_A
• timer::wdog_mode::WDOG_EN_A
• timer::wdog_mode::WDOG_INTV_VALUE_A
• timer::wdog_soft_rst::SOFT_RST_EN_A
• tpadc::tp_ctrl0::ADC_CLK_DIVIDER_A
• tpadc::tp_ctrl0::ADC_FIRST_DLY_MODE_A
• tpadc::tp_ctrl0::FS_DIV_A
• tpadc::tp_ctrl1::ADC_CHAN_SELECT_A
• tpadc::tp_ctrl1::CHOPPER_EN_A
• tpadc::tp_ctrl1::STYLUS_UP_DEBOUNCE_EN_A
• tpadc::tp_ctrl1::TOUCH_PAN_CALI_EN_A
• tpadc::tp_ctrl1::TP_DUAL_EN_A
• tpadc::tp_ctrl1::TP_EN_A
• tpadc::tp_ctrl1::TP_MODE_SELECT_A
• tpadc::tp_ctrl2::PRE_MEA_EN_A
• tpadc::tp_ctrl2::TP_FIFO_MODE_SELECT_A
• tpadc::tp_ctrl3::FILTER_EN_A
• tpadc::tp_ctrl3::FILTER_TYPE_A
• tpadc::tp_int_fifo_ctrl::TP_DATA_ERQ_EN_A
• tpadc::tp_int_fifo_ctrl::TP_DATA_IRQ_EN_A
• tpadc::tp_int_fifo_ctrl::TP_DATA_XY_CHANGE_A
• tpadc::tp_int_fifo_ctrl::TP_DOWN_IRQ_EN_A
• tpadc::tp_int_fifo_ctrl::TP_FIFO_FLUSH_A
• tpadc::tp_int_fifo_ctrl::TP_OVERRUN_IRQ_EN_A
• tpadc::tp_int_fifo_ctrl::TP_UP_IRQ_EN_A
• tpadc::tp_int_fifo_stat::FIFO_DATA_PENDING_A
• tpadc::tp_int_fifo_stat::FIFO_OVERRUN_PENDING_A
• tpadc::tp_int_fifo_stat::TP_DOWN_PENDING_A
• tpadc::tp_int_fifo_stat::TP_IDLE_FLG_A
• tpadc::tp_int_fifo_stat::TP_UP_PENDING_A
• twi::twi_addr::GCE_A
• twi::twi_ccr::CLK_DUTY_A
• twi::twi_cntr::BUS_EN_A
• twi::twi_cntr::CLK_COUNT_MODE_A
• twi::twi_cntr::INT_EN_A
• twi::twi_drv_bus_ctrl::CLK_COUNT_MODE_AW
• twi::twi_drv_bus_ctrl::CLK_DUTY_A
• twi::twi_drv_ctrl::READ_TRAN_MODE_A
• twi::twi_drv_ctrl::RESTART_MODE_A
• twi::twi_drv_ctrl::SOFT_RESET_A
• twi::twi_drv_ctrl::START_TRAN_A
• twi::twi_drv_ctrl::TRAN_RESULT_A
• twi::twi_drv_ctrl::TWI_DRV_EN_A
• twi::twi_drv_ctrl::TWI_STA_A
• twi::twi_drv_slv::CMD_A
• twi::twi_efr::DBN_A
• twi::twi_lcr::SCL_CTL_A
• twi::twi_lcr::SCL_CTL_EN_A
• twi::twi_lcr::SCL_STATE_A
• twi::twi_lcr::SDA_CTL_A
• twi::twi_lcr::SDA_CTL_EN_A
• twi::twi_lcr::SDA_STATE_A
• twi::twi_stat::STA_A
• uart::dma_req_en::RX_REQ_ENABLE_A
• uart::dma_req_en::TIMEOUT_ENABLE_A
• uart::dma_req_en::TX_REQ_ENABLE_A
• uart::fcc::RX_FIFO_CLOCK_ENABLE_A
• uart::fcc::RX_FIFO_CLOCK_MODE_A
• uart::fcc::TX_FIFO_CLOCK_ENABLE_A
• uart::fcr::DMAM_AW
• uart::fcr::RT_AW
• uart::fcr::TFT_AW
• uart::halt::CHANGE_UPDATE_A
• uart::halt::CHCFG_AT_BUSY_A
• uart::halt::HALT_TX_A
• uart::halt::SIR_RX_INVERT_A
• uart::halt::SIR_TX_INVERT_A
• uart::hsk::HSK_A
• uart::ier::EDSSI_A
• uart::ier::ELSI_A
• uart::ier::ERBFI_A
• uart::ier::ETBEI_A
• uart::ier::PTIME_A
• uart::ier::RS485_INT_EN_A
• uart::iir::FEFLAG_A
• uart::iir::IID_A
• uart::lcr::DLAB_A
• uart::lcr::DLS_A
• uart::lcr::EPS_A
• uart::lcr::PEN_A
• uart::lcr::STOP_A
• uart::lsr::DR_A
• uart::lsr::FE_A
• uart::lsr::FIFOERR_A
• uart::lsr::OE_A
• uart::lsr::PE_A
• uart::lsr::TEMT_A
• uart::lsr::THRE_A
• uart::mcr::AFCE_A
• uart::mcr::DTR_A
• uart::mcr::FUNCTION_A
• uart::mcr::LOOP_A
• uart::mcr::RTS_A
• uart::msr::CTS_A
• uart::msr::DCD_A
• uart::msr::DCTS_A
• uart::msr::DDCD_A
• uart::msr::DDSR_A
• uart::msr::DSR_A
• uart::msr::RI_A
• uart::msr::TERI_A
• uart::rxdma_ctrl::AHB_BURST_MODE_A
• uart::rxdma_ctrl::BLK_SIZE_A
• uart::rxdma_ctrl::ENABLE_A
• uart::rxdma_ctrl::MODE_A
• uart::rxdma_sta::BUFFER_READ_ADDRESS_UPDATING_A
• uart::rxdma_sta::BUSY_A
• uart::usr::BUSY_A
• uart::usr::RFF_A
• uart::usr::RFNE_A
• uart::usr::TFE_A
• uart::usr::TFNF_A
• usb1::ehci_operational::portsc::LINE_STATUS_A
• usb1::ehci_operational::portsc::PORT_TEST_CONTROL_A
• usb1::ehci_operational::portsc::SUSPEND_A
• usb1::ehci_operational::usbcmd::ASYNCHRONOUS_SCHEDULE_ENABLE_A
• usb1::ehci_operational::usbcmd::FRAME_LIST_SIZE_A
• usb1::ehci_operational::usbcmd::INTERRUPT_THRESHOLD_CONTROL_A
• usb1::ehci_operational::usbcmd::PERIODIC_SCHEDULE_ENABLE_A
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_DETECT_A
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_DETECT_ENABLE_A
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_INTERRUPT_ENABLE_A
• usb1::hci_controller_phy_interface::hci_ctrl3::REMOTE_WAKEUP_ENABLE_A
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCR16_ENABLE_A
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCR8_ENABLE_A
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A
• usb1::hci_controller_phy_interface::hci_interface::DMA_TRANSFER_STATUS_ENABLE_A
• usb1::hci_controller_phy_interface::hci_interface::OHCI_COUNT_SELECT_A
• usb1::hci_controller_phy_interface::hci_interface::PP2VBUS_A
• usb1::hci_controller_phy_interface::hci_interface::RESUME_K_TO_SE0_TRANSITION_A
• usb1::hci_controller_phy_interface::hci_interface::ULPI_BYPASS_ENABLE_A
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::PORT_DISABLE_CONTROL_A
• usb1::hci_controller_phy_interface::phy_control::SIDDQ_A
• usb1::ohci_control_status_partition::hc_control::CONTROL_BULK_SERVICE_RATIO_A
• usb1::ohci_control_status_partition::hc_control::HOST_CONTROLLER_FUNCTIONAL_STATE_FOR_USB_A
• usb1::ohci_control_status_partition::hc_interrupt_disable::FRAME_NUMBER_OVERFLOW_A
• usb1::ohci_control_status_partition::hc_interrupt_disable::RESUME_DETECTED_A
• usb1::ohci_control_status_partition::hc_interrupt_disable::ROOT_HUB_STATUS_CHANGE_A
• usb1::ohci_control_status_partition::hc_interrupt_disable::SCHEDULING_OVERRUN_A
• usb1::ohci_control_status_partition::hc_interrupt_disable::START_OF_FRAME_A
• usb1::ohci_control_status_partition::hc_interrupt_disable::UNRECOVERABLE_ERROR_A
• usb1::ohci_control_status_partition::hc_interrupt_disable::WRITEBACK_DONE_HEAD_A
• usb1::ohci_control_status_partition::hc_interrupt_enable::FRAME_NUMBER_OVERFLOW_A
• usb1::ohci_control_status_partition::hc_interrupt_enable::RESUME_DETECTED_A
• usb1::ohci_control_status_partition::hc_interrupt_enable::ROOT_HUB_STATUS_CHANGE_A
• usb1::ohci_control_status_partition::hc_interrupt_enable::SCHEDULING_OVERRUN_A
• usb1::ohci_control_status_partition::hc_interrupt_enable::START_OF_FRAME_A
• usb1::ohci_control_status_partition::hc_interrupt_enable::UNRECOVERABLE_ERROR_A
• usb1::ohci_control_status_partition::hc_interrupt_enable::WRITEBACK_DONE_HEAD_A
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::NO_OVER_CURRENT_PROTECTION_A
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::NO_POWER_SWITHCING_A
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::OVER_CURRENT_PROTECTION_MODE_A
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::POWER_SWITCHING_MODE_A
• usb1::ohci_root_hub_partition::hc_rh_port_status::CONNECT_STATUS_CHANGE_A
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_ENABLE_STATUS_CHANGE_A
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_OVER_CURRENT_INDICATOR_CHANGE_A
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_RESET_STATUS_CHANGE_A
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_SUSPEND_STATUS_CHANGE_A

Traits

• generic::Readable
• generic::RegisterSpec
• generic::Resettable
• generic::Writable

Typedefs

• audio_codec::AC_ADC_CNT
• audio_codec::AC_ADC_DAP_CTR
• audio_codec::AC_ADC_DG
• audio_codec::AC_ADC_DRC_CTRL
• audio_codec::AC_ADC_DRC_EPSHC
• audio_codec::AC_ADC_DRC_EPSLC
• audio_codec::AC_ADC_DRC_HCT
• audio_codec::AC_ADC_DRC_HET
• audio_codec::AC_ADC_DRC_HHPFC
• audio_codec::AC_ADC_DRC_HKC
• audio_codec::AC_ADC_DRC_HKE
• audio_codec::AC_ADC_DRC_HKL
• audio_codec::AC_ADC_DRC_HKN
• audio_codec::AC_ADC_DRC_HLT
• audio_codec::AC_ADC_DRC_HOPC
• audio_codec::AC_ADC_DRC_HOPE
• audio_codec::AC_ADC_DRC_HOPL
• audio_codec::AC_ADC_DRC_HPFHGAIN
• audio_codec::AC_ADC_DRC_HPFLGAIN
• audio_codec::AC_ADC_DRC_LCT
• audio_codec::AC_ADC_DRC_LET
• audio_codec::AC_ADC_DRC_LHPFC
• audio_codec::AC_ADC_DRC_LKC
• audio_codec::AC_ADC_DRC_LKE
• audio_codec::AC_ADC_DRC_LKL
• audio_codec::AC_ADC_DRC_LKN
• audio_codec::AC_ADC_DRC_LLT
• audio_codec::AC_ADC_DRC_LOPC
• audio_codec::AC_ADC_DRC_LOPE
• audio_codec::AC_ADC_DRC_LOPL
• audio_codec::AC_ADC_DRC_LPFHAT
• audio_codec::AC_ADC_DRC_LPFHRT
• audio_codec::AC_ADC_DRC_LPFLAT
• audio_codec::AC_ADC_DRC_LPFLRT
• audio_codec::AC_ADC_DRC_LRMSHAT
• audio_codec::AC_ADC_DRC_LRMSLAT
• audio_codec::AC_ADC_DRC_MNGHS
• audio_codec::AC_ADC_DRC_MNGLS
• audio_codec::AC_ADC_DRC_MXGHS
• audio_codec::AC_ADC_DRC_MXGLS
• audio_codec::AC_ADC_DRC_RPFHAT
• audio_codec::AC_ADC_DRC_RPFHRT
• audio_codec::AC_ADC_DRC_RPFLAT
• audio_codec::AC_ADC_DRC_RPFLRT
• audio_codec::AC_ADC_DRC_RRMSHAT
• audio_codec::AC_ADC_DRC_RRMSLAT
• audio_codec::AC_ADC_DRC_SFHAT
• audio_codec::AC_ADC_DRC_SFHRT
• audio_codec::AC_ADC_DRC_SFLAT
• audio_codec::AC_ADC_DRC_SFLRT
• audio_codec::AC_ADC_FIFOC
• audio_codec::AC_ADC_FIFOS
• audio_codec::AC_ADC_RXDATA
• audio_codec::AC_DAC_CNT
• audio_codec::AC_DAC_DAP_CTRL
• audio_codec::AC_DAC_DG
• audio_codec::AC_DAC_DPC
• audio_codec::AC_DAC_DRC_CTRL
• audio_codec::AC_DAC_DRC_EPSHC
• audio_codec::AC_DAC_DRC_EPSLC
• audio_codec::AC_DAC_DRC_HCT
• audio_codec::AC_DAC_DRC_HET
• audio_codec::AC_DAC_DRC_HHPFC
• audio_codec::AC_DAC_DRC_HKC
• audio_codec::AC_DAC_DRC_HKE
• audio_codec::AC_DAC_DRC_HKL
• audio_codec::AC_DAC_DRC_HKN
• audio_codec::AC_DAC_DRC_HLT
• audio_codec::AC_DAC_DRC_HOPC
• audio_codec::AC_DAC_DRC_HOPE
• audio_codec::AC_DAC_DRC_HOPL
• audio_codec::AC_DAC_DRC_HPFHGAIN
• audio_codec::AC_DAC_DRC_HPFLGAIN
• audio_codec::AC_DAC_DRC_LCT
• audio_codec::AC_DAC_DRC_LET
• audio_codec::AC_DAC_DRC_LHPFC
• audio_codec::AC_DAC_DRC_LKC
• audio_codec::AC_DAC_DRC_LKE
• audio_codec::AC_DAC_DRC_LKL
• audio_codec::AC_DAC_DRC_LKN
• audio_codec::AC_DAC_DRC_LLT
• audio_codec::AC_DAC_DRC_LOPC
• audio_codec::AC_DAC_DRC_LOPE
• audio_codec::AC_DAC_DRC_LOPL
• audio_codec::AC_DAC_DRC_LPFHAT
• audio_codec::AC_DAC_DRC_LPFHRT
• audio_codec::AC_DAC_DRC_LPFLAT
• audio_codec::AC_DAC_DRC_LPFLRT
• audio_codec::AC_DAC_DRC_LRMSHAT
• audio_codec::AC_DAC_DRC_LRMSLAT
• audio_codec::AC_DAC_DRC_MNGHS
• audio_codec::AC_DAC_DRC_MNGLS
• audio_codec::AC_DAC_DRC_MXGHS
• audio_codec::AC_DAC_DRC_MXGLS
• audio_codec::AC_DAC_DRC_RPFHAT
• audio_codec::AC_DAC_DRC_RPFHRT
• audio_codec::AC_DAC_DRC_RPFLAT
• audio_codec::AC_DAC_DRC_RPFLRT
• audio_codec::AC_DAC_DRC_RRMSHAT
• audio_codec::AC_DAC_DRC_RRMSLAT
• audio_codec::AC_DAC_DRC_SFHAT
• audio_codec::AC_DAC_DRC_SFHRT
• audio_codec::AC_DAC_DRC_SFLAT
• audio_codec::AC_DAC_DRC_SFLRT
• audio_codec::AC_DAC_FIFOC
• audio_codec::AC_DAC_FIFOS
• audio_codec::AC_DAC_TXDATA
• audio_codec::ADC1_REG
• audio_codec::ADC2_REG
• audio_codec::ADC3_REG
• audio_codec::ADC5_REG
• audio_codec::ADC_DIG_CTRL
• audio_codec::ADC_VOL_CTRL1
• audio_codec::BIAS_REG
• audio_codec::DAC_REG
• audio_codec::DAC_VOL_CTRL
• audio_codec::MICBIAS_REG
• audio_codec::RAMP_REG
• audio_codec::VRA1SPEEDUP_DOWN_CTRL
• ccu::APB_CLK
• ccu::AUDIO_CODEC_ADC_CLK
• ccu::AUDIO_CODEC_BGR
• ccu::AUDIO_CODEC_DAC_CLK
• ccu::AVS_CLK
• ccu::CCU_FAN
• ccu::CCU_FAN_GATE
• ccu::CE_BGR
• ccu::CE_CLK
• ccu::CLK27M_FAN
• ccu::CPU_AXI_CFG
• ccu::CPU_GATING
• ccu::CSI_BGR
• ccu::CSI_CLK
• ccu::CSI_MASTER_CLK
• ccu::DBGSYS_BGR
• ccu::DE_BGR
• ccu::DE_CLK
• ccu::DI_BGR
• ccu::DI_CLK
• ccu::DMA_BGR
• ccu::DMIC_BGR
• ccu::DMIC_CLK
• ccu::DPSS_TOP_BGR
• ccu::DRAM_BGR
• ccu::DRAM_CLK
• ccu::DSI_BGR
• ccu::DSI_CLK
• ccu::DSP_BGR
• ccu::DSP_CLK
• ccu::EMAC_25M_CLK
• ccu::EMAC_BGR
• ccu::FRE_DET_CTRL
• ccu::FRE_DOWN_LIM
• ccu::FRE_UP_LIM
• ccu::G2D_BGR
• ccu::G2D_CLK
• ccu::GPADC_BGR
• ccu::HSTIMER_BGR
• ccu::I2S2_ASRC_CLK
• ccu::I2S_BGR
• ccu::I2S_CLK
• ccu::IOMMU_BGR
• ccu::IRTX_BGR
• ccu::IRTX_CLK
• ccu::LEDC_BGR
• ccu::LEDC_CLK
• ccu::LRADC_BGR
• ccu::LVDS_BGR
• ccu::MBUS_CLK
• ccu::MBUS_MAT_CLK_GATING
• ccu::MSGBOX_BGR
• ccu::OWA_BGR
• ccu::OWA_RX_CLK
• ccu::OWA_TX_CLK
• ccu::PCLK_FAN
• ccu::PLL_AUDIO0_BIAS
• ccu::PLL_AUDIO0_CTRL
• ccu::PLL_AUDIO0_PAT0_CTRL
• ccu::PLL_AUDIO0_PAT1_CTRL
• ccu::PLL_AUDIO1_BIAS
• ccu::PLL_AUDIO1_CTRL
• ccu::PLL_AUDIO1_PAT0_CTRL
• ccu::PLL_AUDIO1_PAT1_CTRL
• ccu::PLL_CPU_BIAS
• ccu::PLL_CPU_CTRL
• ccu::PLL_CPU_TUN
• ccu::PLL_DDR_BIAS
• ccu::PLL_DDR_CTRL
• ccu::PLL_DDR_PAT0_CTRL
• ccu::PLL_DDR_PAT1_CTRL
• ccu::PLL_LOCK_DBG_CTRL
• ccu::PLL_PERI_BIAS
• ccu::PLL_PERI_CTRL
• ccu::PLL_PERI_PAT0_CTRL
• ccu::PLL_PERI_PAT1_CTRL
• ccu::PLL_VE_BIAS
• ccu::PLL_VE_CTRL
• ccu::PLL_VE_PAT0_CTRL
• ccu::PLL_VE_PAT1_CTRL
• ccu::PLL_VIDEO0_BIAS
• ccu::PLL_VIDEO0_CTRL
• ccu::PLL_VIDEO0_PAT0_CTRL
• ccu::PLL_VIDEO0_PAT1_CTRL
• ccu::PLL_VIDEO1_BIAS
• ccu::PLL_VIDEO1_CTRL
• ccu::PLL_VIDEO1_PAT0_CTRL
• ccu::PLL_VIDEO1_PAT1_CTRL
• ccu::PSI_CLK
• ccu::PWM_BGR
• ccu::RISCV_CFG_BGR
• ccu::RISCV_CLK
• ccu::RISCV_GATING
• ccu::SMHC0_CLK
• ccu::SMHC1_CLK
• ccu::SMHC2_CLK
• ccu::SMHC_BGR
• ccu::SPI0_CLK
• ccu::SPI1_CLK
• ccu::SPINLOCK_BGR
• ccu::SPI_BGR
• ccu::TCONLCD_BGR
• ccu::TCONLCD_CLK
• ccu::TCONTV_BGR
• ccu::TCONTV_CLK
• ccu::THS_BGR
• ccu::TPADC_BGR
• ccu::TPADC_CLK
• ccu::TVD_BGR
• ccu::TVD_CLK
• ccu::TVE_BGR
• ccu::TVE_CLK
• ccu::TWI_BGR
• ccu::UART_BGR
• ccu::USB0_CLK
• ccu::USB1_CLK
• ccu::USB_BGR
• ccu::VE_BGR
• ccu::VE_CLK
• ccu::apb_clk::CLK_SRC_SEL_R
• ccu::apb_clk::CLK_SRC_SEL_W
• ccu::apb_clk::FACTOR_M_R
• ccu::apb_clk::FACTOR_M_W
• ccu::apb_clk::FACTOR_N_R
• ccu::apb_clk::FACTOR_N_W
• ccu::audio_codec_adc_clk::CLK_GATING_R
• ccu::audio_codec_adc_clk::CLK_GATING_W
• ccu::audio_codec_adc_clk::CLK_SRC_SEL_R
• ccu::audio_codec_adc_clk::CLK_SRC_SEL_W
• ccu::audio_codec_adc_clk::FACTOR_M_R
• ccu::audio_codec_adc_clk::FACTOR_M_W
• ccu::audio_codec_adc_clk::FACTOR_N_R
• ccu::audio_codec_adc_clk::FACTOR_N_W
• ccu::audio_codec_bgr::GATING_R
• ccu::audio_codec_bgr::GATING_W
• ccu::audio_codec_bgr::RST_R
• ccu::audio_codec_bgr::RST_W
• ccu::audio_codec_dac_clk::CLK_GATING_R
• ccu::audio_codec_dac_clk::CLK_GATING_W
• ccu::audio_codec_dac_clk::CLK_SRC_SEL_R
• ccu::audio_codec_dac_clk::CLK_SRC_SEL_W
• ccu::audio_codec_dac_clk::FACTOR_M_R
• ccu::audio_codec_dac_clk::FACTOR_M_W
• ccu::audio_codec_dac_clk::FACTOR_N_R
• ccu::audio_codec_dac_clk::FACTOR_N_W
• ccu::avs_clk::CLK_GATING_R
• ccu::avs_clk::CLK_GATING_W
• ccu::ccu_fan::CLK_FANOUT_EN_R
• ccu::ccu_fan::CLK_FANOUT_EN_W
• ccu::ccu_fan::CLK_FANOUT_SEL_R
• ccu::ccu_fan::CLK_FANOUT_SEL_W
• ccu::ccu_fan_gate::CLK12M_EN_R
• ccu::ccu_fan_gate::CLK12M_EN_W
• ccu::ccu_fan_gate::CLK16M_EN_R
• ccu::ccu_fan_gate::CLK16M_EN_W
• ccu::ccu_fan_gate::CLK24M_EN_R
• ccu::ccu_fan_gate::CLK24M_EN_W
• ccu::ccu_fan_gate::CLK25M_EN_R
• ccu::ccu_fan_gate::CLK25M_EN_W
• ccu::ccu_fan_gate::CLK32K_EN_R
• ccu::ccu_fan_gate::CLK32K_EN_W
• ccu::ce_bgr::GATING_R
• ccu::ce_bgr::GATING_W
• ccu::ce_bgr::RST_R
• ccu::ce_bgr::RST_W
• ccu::ce_clk::CLK_GATING_R
• ccu::ce_clk::CLK_GATING_W
• ccu::ce_clk::CLK_SRC_SEL_R
• ccu::ce_clk::CLK_SRC_SEL_W
• ccu::ce_clk::FACTOR_M_R
• ccu::ce_clk::FACTOR_M_W
• ccu::ce_clk::FACTOR_N_R
• ccu::ce_clk::FACTOR_N_W
• ccu::clk27m_fan::CLK_SRC_SEL_R
• ccu::clk27m_fan::CLK_SRC_SEL_W
• ccu::clk27m_fan::DIV0_R
• ccu::clk27m_fan::DIV0_W
• ccu::clk27m_fan::DIV1_R
• ccu::clk27m_fan::DIV1_W
• ccu::clk27m_fan::GATING_R
• ccu::clk27m_fan::GATING_W
• ccu::cpu_axi_cfg::CPU_CLK_SEL_R
• ccu::cpu_axi_cfg::CPU_CLK_SEL_W
• ccu::cpu_axi_cfg::CPU_DIV1_R
• ccu::cpu_axi_cfg::CPU_DIV1_W
• ccu::cpu_axi_cfg::CPU_DIV2_R
• ccu::cpu_axi_cfg::CPU_DIV2_W
• ccu::cpu_axi_cfg::PLL_CPU_OUT_EXT_DIVP_R
• ccu::cpu_axi_cfg::PLL_CPU_OUT_EXT_DIVP_W
• ccu::cpu_gating::CPU_GATING_FIELD_R
• ccu::cpu_gating::CPU_GATING_FIELD_W
• ccu::cpu_gating::CPU_GATING_R
• ccu::cpu_gating::CPU_GATING_W
• ccu::csi_bgr::GATING_R
• ccu::csi_bgr::GATING_W
• ccu::csi_bgr::RST_R
• ccu::csi_bgr::RST_W
• ccu::csi_clk::CLK_GATING_R
• ccu::csi_clk::CLK_GATING_W
• ccu::csi_clk::CLK_SRC_SEL_R
• ccu::csi_clk::CLK_SRC_SEL_W
• ccu::csi_clk::FACTOR_M_R
• ccu::csi_clk::FACTOR_M_W
• ccu::csi_master_clk::CLK_GATING_R
• ccu::csi_master_clk::CLK_GATING_W
• ccu::csi_master_clk::CLK_SRC_SEL_R
• ccu::csi_master_clk::CLK_SRC_SEL_W
• ccu::csi_master_clk::FACTOR_M_R
• ccu::csi_master_clk::FACTOR_M_W
• ccu::dbgsys_bgr::GATING_R
• ccu::dbgsys_bgr::GATING_W
• ccu::dbgsys_bgr::RST_R
• ccu::dbgsys_bgr::RST_W
• ccu::de_bgr::GATING_R
• ccu::de_bgr::GATING_W
• ccu::de_bgr::RST_R
• ccu::de_bgr::RST_W
• ccu::de_clk::CLK_GATING_R
• ccu::de_clk::CLK_GATING_W
• ccu::de_clk::CLK_SRC_SEL_R
• ccu::de_clk::CLK_SRC_SEL_W
• ccu::de_clk::FACTOR_M_R
• ccu::de_clk::FACTOR_M_W
• ccu::di_bgr::GATING_R
• ccu::di_bgr::GATING_W
• ccu::di_bgr::RST_R
• ccu::di_bgr::RST_W
• ccu::di_clk::CLK_GATING_R
• ccu::di_clk::CLK_GATING_W
• ccu::di_clk::CLK_SRC_SEL_R
• ccu::di_clk::CLK_SRC_SEL_W
• ccu::di_clk::FACTOR_M_R
• ccu::di_clk::FACTOR_M_W
• ccu::dma_bgr::GATING_R
• ccu::dma_bgr::GATING_W
• ccu::dma_bgr::RST_R
• ccu::dma_bgr::RST_W
• ccu::dmic_bgr::GATING_R
• ccu::dmic_bgr::GATING_W
• ccu::dmic_bgr::RST_R
• ccu::dmic_bgr::RST_W
• ccu::dmic_clk::CLK_GATING_R
• ccu::dmic_clk::CLK_GATING_W
• ccu::dmic_clk::CLK_SRC_SEL_R
• ccu::dmic_clk::CLK_SRC_SEL_W
• ccu::dmic_clk::FACTOR_M_R
• ccu::dmic_clk::FACTOR_M_W
• ccu::dmic_clk::FACTOR_N_R
• ccu::dmic_clk::FACTOR_N_W
• ccu::dpss_top_bgr::GATING_R
• ccu::dpss_top_bgr::GATING_W
• ccu::dpss_top_bgr::RST_R
• ccu::dpss_top_bgr::RST_W
• ccu::dram_bgr::GATING_R
• ccu::dram_bgr::GATING_W
• ccu::dram_bgr::RST_R
• ccu::dram_bgr::RST_W
• ccu::dram_clk::CLK_GATING_R
• ccu::dram_clk::CLK_GATING_W
• ccu::dram_clk::CLK_SRC_SEL_R
• ccu::dram_clk::CLK_SRC_SEL_W
• ccu::dram_clk::DRAM_DIV1_R
• ccu::dram_clk::DRAM_DIV1_W
• ccu::dram_clk::DRAM_DIV2_R
• ccu::dram_clk::DRAM_DIV2_W
• ccu::dram_clk::SDRCLK_UPD_R
• ccu::dram_clk::SDRCLK_UPD_W
• ccu::dsi_bgr::GATING_R
• ccu::dsi_bgr::GATING_W
• ccu::dsi_bgr::RST_R
• ccu::dsi_bgr::RST_W
• ccu::dsi_clk::CLK_GATING_R
• ccu::dsi_clk::CLK_GATING_W
• ccu::dsi_clk::CLK_SRC_SEL_R
• ccu::dsi_clk::CLK_SRC_SEL_W
• ccu::dsi_clk::FACTOR_M_R
• ccu::dsi_clk::FACTOR_M_W
• ccu::dsp_bgr::CFG_GATING_R
• ccu::dsp_bgr::CFG_GATING_W
• ccu::dsp_bgr::CFG_RST_R
• ccu::dsp_bgr::CFG_RST_W
• ccu::dsp_bgr::DBG_RST_R
• ccu::dsp_bgr::DBG_RST_W
• ccu::dsp_bgr::RST_R
• ccu::dsp_bgr::RST_W
• ccu::dsp_clk::CLK_GATING_R
• ccu::dsp_clk::CLK_GATING_W
• ccu::dsp_clk::CLK_SRC_SEL_R
• ccu::dsp_clk::CLK_SRC_SEL_W
• ccu::dsp_clk::FACTOR_M_R
• ccu::dsp_clk::FACTOR_M_W
• ccu::emac_25m_clk::CLK_GATING_R
• ccu::emac_25m_clk::CLK_GATING_W
• ccu::emac_25m_clk::CLK_SRC_GATING_R
• ccu::emac_25m_clk::CLK_SRC_GATING_W
• ccu::emac_bgr::GATING_R
• ccu::emac_bgr::GATING_W
• ccu::emac_bgr::RST_R
• ccu::emac_bgr::RST_W
• ccu::fre_det_ctrl::DET_TIME_R
• ccu::fre_det_ctrl::DET_TIME_W
• ccu::fre_det_ctrl::ERROR_FLAG_R
• ccu::fre_det_ctrl::ERROR_FLAG_W
• ccu::fre_det_ctrl::FRE_DET_FUN_EN_R
• ccu::fre_det_ctrl::FRE_DET_FUN_EN_W
• ccu::fre_det_ctrl::FRE_DET_IRQ_EN_R
• ccu::fre_det_ctrl::FRE_DET_IRQ_EN_W
• ccu::g2d_bgr::GATING_R
• ccu::g2d_bgr::GATING_W
• ccu::g2d_bgr::RST_R
• ccu::g2d_bgr::RST_W
• ccu::g2d_clk::CLK_GATING_R
• ccu::g2d_clk::CLK_GATING_W
• ccu::g2d_clk::CLK_SRC_SEL_R
• ccu::g2d_clk::CLK_SRC_SEL_W
• ccu::g2d_clk::FACTOR_M_R
• ccu::g2d_clk::FACTOR_M_W
• ccu::gpadc_bgr::GATING_R
• ccu::gpadc_bgr::GATING_W
• ccu::gpadc_bgr::RST_R
• ccu::gpadc_bgr::RST_W
• ccu::hstimer_bgr::GATING_R
• ccu::hstimer_bgr::GATING_W
• ccu::hstimer_bgr::RST_R
• ccu::hstimer_bgr::RST_W
• ccu::i2s2_asrc_clk::CLK_GATING_R
• ccu::i2s2_asrc_clk::CLK_GATING_W
• ccu::i2s2_asrc_clk::CLK_SRC_SEL_R
• ccu::i2s2_asrc_clk::CLK_SRC_SEL_W
• ccu::i2s2_asrc_clk::FACTOR_M_R
• ccu::i2s2_asrc_clk::FACTOR_M_W
• ccu::i2s2_asrc_clk::FACTOR_N_R
• ccu::i2s2_asrc_clk::FACTOR_N_W
• ccu::i2s_bgr::I2S_GATING_R
• ccu::i2s_bgr::I2S_GATING_W
• ccu::i2s_bgr::I2S_RST_R
• ccu::i2s_bgr::I2S_RST_W
• ccu::i2s_clk::CLK_GATING_R
• ccu::i2s_clk::CLK_GATING_W
• ccu::i2s_clk::CLK_SRC_SEL_R
• ccu::i2s_clk::CLK_SRC_SEL_W
• ccu::i2s_clk::FACTOR_M_R
• ccu::i2s_clk::FACTOR_M_W
• ccu::i2s_clk::FACTOR_N_R
• ccu::i2s_clk::FACTOR_N_W
• ccu::iommu_bgr::GATING_R
• ccu::iommu_bgr::GATING_W
• ccu::irtx_bgr::GATING_R
• ccu::irtx_bgr::GATING_W
• ccu::irtx_bgr::RST_R
• ccu::irtx_bgr::RST_W
• ccu::irtx_clk::CLK_GATING_R
• ccu::irtx_clk::CLK_GATING_W
• ccu::irtx_clk::CLK_SRC_SEL_R
• ccu::irtx_clk::CLK_SRC_SEL_W
• ccu::irtx_clk::FACTOR_M_R
• ccu::irtx_clk::FACTOR_M_W
• ccu::irtx_clk::FACTOR_N_R
• ccu::irtx_clk::FACTOR_N_W
• ccu::ledc_bgr::GATING_R
• ccu::ledc_bgr::GATING_W
• ccu::ledc_bgr::RST_R
• ccu::ledc_bgr::RST_W
• ccu::ledc_clk::CLK_GATING_R
• ccu::ledc_clk::CLK_GATING_W
• ccu::ledc_clk::CLK_SRC_SEL_R
• ccu::ledc_clk::CLK_SRC_SEL_W
• ccu::ledc_clk::FACTOR_M_R
• ccu::ledc_clk::FACTOR_M_W
• ccu::ledc_clk::FACTOR_N_R
• ccu::ledc_clk::FACTOR_N_W
• ccu::lradc_bgr::GATING_R
• ccu::lradc_bgr::GATING_W
• ccu::lradc_bgr::RST_R
• ccu::lradc_bgr::RST_W
• ccu::lvds_bgr::RST_R
• ccu::lvds_bgr::RST_W
• ccu::mbus_clk::MBUS_RST_R
• ccu::mbus_clk::MBUS_RST_W
• ccu::mbus_mat_clk_gating::CE_MCLK_EN_R
• ccu::mbus_mat_clk_gating::CE_MCLK_EN_W
• ccu::mbus_mat_clk_gating::CSI_MCLK_EN_R
• ccu::mbus_mat_clk_gating::CSI_MCLK_EN_W
• ccu::mbus_mat_clk_gating::DMA_MCLK_EN_R
• ccu::mbus_mat_clk_gating::DMA_MCLK_EN_W
• ccu::mbus_mat_clk_gating::G2D_MCLK_EN_R
• ccu::mbus_mat_clk_gating::G2D_MCLK_EN_W
• ccu::mbus_mat_clk_gating::RISCV_MCLK_EN_R
• ccu::mbus_mat_clk_gating::RISCV_MCLK_EN_W
• ccu::mbus_mat_clk_gating::TVIN_MCLK_EN_R
• ccu::mbus_mat_clk_gating::TVIN_MCLK_EN_W
• ccu::mbus_mat_clk_gating::VE_MCLK_EN_R
• ccu::mbus_mat_clk_gating::VE_MCLK_EN_W
• ccu::msgbox_bgr::MSGBOX_GATING_R
• ccu::msgbox_bgr::MSGBOX_GATING_W
• ccu::msgbox_bgr::MSGBOX_RST_R
• ccu::msgbox_bgr::MSGBOX_RST_W
• ccu::owa_bgr::GATING_R
• ccu::owa_bgr::GATING_W
• ccu::owa_bgr::RST_R
• ccu::owa_bgr::RST_W
• ccu::owa_rx_clk::CLK_GATING_R
• ccu::owa_rx_clk::CLK_GATING_W
• ccu::owa_rx_clk::CLK_SRC_SEL_R
• ccu::owa_rx_clk::CLK_SRC_SEL_W
• ccu::owa_rx_clk::FACTOR_M_R
• ccu::owa_rx_clk::FACTOR_M_W
• ccu::owa_rx_clk::FACTOR_N_R
• ccu::owa_rx_clk::FACTOR_N_W
• ccu::owa_tx_clk::CLK_GATING_R
• ccu::owa_tx_clk::CLK_GATING_W
• ccu::owa_tx_clk::CLK_SRC_SEL_R
• ccu::owa_tx_clk::CLK_SRC_SEL_W
• ccu::owa_tx_clk::FACTOR_M_R
• ccu::owa_tx_clk::FACTOR_M_W
• ccu::owa_tx_clk::FACTOR_N_R
• ccu::owa_tx_clk::FACTOR_N_W
• ccu::pclk_fan::DIV_R
• ccu::pclk_fan::DIV_W
• ccu::pclk_fan::GATING_R
• ccu::pclk_fan::GATING_W
• ccu::pll_audio0_bias::PLL_CP_R
• ccu::pll_audio0_bias::PLL_CP_W
• ccu::pll_audio0_ctrl::LOCK_ENABLE_R
• ccu::pll_audio0_ctrl::LOCK_ENABLE_W
• ccu::pll_audio0_ctrl::LOCK_R
• ccu::pll_audio0_ctrl::PLL_EN_R
• ccu::pll_audio0_ctrl::PLL_EN_W
• ccu::pll_audio0_ctrl::PLL_INPUT_DIV2_R
• ccu::pll_audio0_ctrl::PLL_INPUT_DIV2_W
• ccu::pll_audio0_ctrl::PLL_LDO_EN_R
• ccu::pll_audio0_ctrl::PLL_LDO_EN_W
• ccu::pll_audio0_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_audio0_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_audio0_ctrl::PLL_N_R
• ccu::pll_audio0_ctrl::PLL_N_W
• ccu::pll_audio0_ctrl::PLL_OUTPUT_DIV2_R
• ccu::pll_audio0_ctrl::PLL_OUTPUT_DIV2_W
• ccu::pll_audio0_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_audio0_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_audio0_ctrl::PLL_P_R
• ccu::pll_audio0_ctrl::PLL_P_W
• ccu::pll_audio0_ctrl::PLL_SDM_EN_R
• ccu::pll_audio0_ctrl::PLL_SDM_EN_W
• ccu::pll_audio0_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_audio0_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_audio0_pat0_ctrl::FREQ_R
• ccu::pll_audio0_pat0_ctrl::FREQ_W
• ccu::pll_audio0_pat0_ctrl::SDM_CLK_SEL_R
• ccu::pll_audio0_pat0_ctrl::SDM_CLK_SEL_W
• ccu::pll_audio0_pat0_ctrl::SIG_DELT_PAT_EN_R
• ccu::pll_audio0_pat0_ctrl::SIG_DELT_PAT_EN_W
• ccu::pll_audio0_pat0_ctrl::SPR_FREQ_MODE_R
• ccu::pll_audio0_pat0_ctrl::SPR_FREQ_MODE_W
• ccu::pll_audio0_pat0_ctrl::WAVE_BOT_R
• ccu::pll_audio0_pat0_ctrl::WAVE_BOT_W
• ccu::pll_audio0_pat0_ctrl::WAVE_STEP_R
• ccu::pll_audio0_pat0_ctrl::WAVE_STEP_W
• ccu::pll_audio0_pat1_ctrl::DITHER_EN_R
• ccu::pll_audio0_pat1_ctrl::DITHER_EN_W
• ccu::pll_audio0_pat1_ctrl::FRAC_EN_R
• ccu::pll_audio0_pat1_ctrl::FRAC_EN_W
• ccu::pll_audio0_pat1_ctrl::FRAC_IN_R
• ccu::pll_audio0_pat1_ctrl::FRAC_IN_W
• ccu::pll_audio1_bias::PLL_CP_R
• ccu::pll_audio1_bias::PLL_CP_W
• ccu::pll_audio1_ctrl::LOCK_ENABLE_R
• ccu::pll_audio1_ctrl::LOCK_ENABLE_W
• ccu::pll_audio1_ctrl::LOCK_R
• ccu::pll_audio1_ctrl::PLL_EN_R
• ccu::pll_audio1_ctrl::PLL_EN_W
• ccu::pll_audio1_ctrl::PLL_INPUT_DIV2_R
• ccu::pll_audio1_ctrl::PLL_INPUT_DIV2_W
• ccu::pll_audio1_ctrl::PLL_LDO_EN_R
• ccu::pll_audio1_ctrl::PLL_LDO_EN_W
• ccu::pll_audio1_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_audio1_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_audio1_ctrl::PLL_N_R
• ccu::pll_audio1_ctrl::PLL_N_W
• ccu::pll_audio1_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_audio1_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_audio1_ctrl::PLL_P0_R
• ccu::pll_audio1_ctrl::PLL_P0_W
• ccu::pll_audio1_ctrl::PLL_P1_R
• ccu::pll_audio1_ctrl::PLL_P1_W
• ccu::pll_audio1_ctrl::PLL_SDM_EN_R
• ccu::pll_audio1_ctrl::PLL_SDM_EN_W
• ccu::pll_audio1_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_audio1_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_audio1_pat0_ctrl::FREQ_R
• ccu::pll_audio1_pat0_ctrl::FREQ_W
• ccu::pll_audio1_pat0_ctrl::SDM_CLK_SEL_R
• ccu::pll_audio1_pat0_ctrl::SDM_CLK_SEL_W
• ccu::pll_audio1_pat0_ctrl::SIG_DELT_PAT_EN_R
• ccu::pll_audio1_pat0_ctrl::SIG_DELT_PAT_EN_W
• ccu::pll_audio1_pat0_ctrl::SPR_FREQ_MODE_R
• ccu::pll_audio1_pat0_ctrl::SPR_FREQ_MODE_W
• ccu::pll_audio1_pat0_ctrl::WAVE_BOT_R
• ccu::pll_audio1_pat0_ctrl::WAVE_BOT_W
• ccu::pll_audio1_pat0_ctrl::WAVE_STEP_R
• ccu::pll_audio1_pat0_ctrl::WAVE_STEP_W
• ccu::pll_audio1_pat1_ctrl::DITHER_EN_R
• ccu::pll_audio1_pat1_ctrl::DITHER_EN_W
• ccu::pll_audio1_pat1_ctrl::FRAC_EN_R
• ccu::pll_audio1_pat1_ctrl::FRAC_EN_W
• ccu::pll_audio1_pat1_ctrl::FRAC_IN_R
• ccu::pll_audio1_pat1_ctrl::FRAC_IN_W
• ccu::pll_cpu_bias::PLL_CP_R
• ccu::pll_cpu_bias::PLL_CP_W
• ccu::pll_cpu_bias::PLL_VCO_RST_IN_R
• ccu::pll_cpu_bias::PLL_VCO_RST_IN_W
• ccu::pll_cpu_ctrl::LOCK_ENABLE_R
• ccu::pll_cpu_ctrl::LOCK_ENABLE_W
• ccu::pll_cpu_ctrl::LOCK_R
• ccu::pll_cpu_ctrl::PLL_EN_R
• ccu::pll_cpu_ctrl::PLL_EN_W
• ccu::pll_cpu_ctrl::PLL_LDO_EN_R
• ccu::pll_cpu_ctrl::PLL_LDO_EN_W
• ccu::pll_cpu_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_cpu_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_cpu_ctrl::PLL_LOCK_TIME_R
• ccu::pll_cpu_ctrl::PLL_LOCK_TIME_W
• ccu::pll_cpu_ctrl::PLL_M_R
• ccu::pll_cpu_ctrl::PLL_M_W
• ccu::pll_cpu_ctrl::PLL_N_R
• ccu::pll_cpu_ctrl::PLL_N_W
• ccu::pll_cpu_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_cpu_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_cpu_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_cpu_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_cpu_tun::PLL_B_IN_R
• ccu::pll_cpu_tun::PLL_B_IN_W
• ccu::pll_cpu_tun::PLL_B_OUT_R
• ccu::pll_cpu_tun::PLL_CNT_INT_R
• ccu::pll_cpu_tun::PLL_CNT_INT_W
• ccu::pll_cpu_tun::PLL_REG_OD1_R
• ccu::pll_cpu_tun::PLL_REG_OD1_W
• ccu::pll_cpu_tun::PLL_REG_OD_R
• ccu::pll_cpu_tun::PLL_REG_OD_W
• ccu::pll_cpu_tun::PLL_VCO_GAIN_R
• ccu::pll_cpu_tun::PLL_VCO_GAIN_W
• ccu::pll_cpu_tun::PLL_VCO_R
• ccu::pll_cpu_tun::PLL_VCO_W
• ccu::pll_ddr_bias::PLL_CP_R
• ccu::pll_ddr_bias::PLL_CP_W
• ccu::pll_ddr_ctrl::LOCK_ENABLE_R
• ccu::pll_ddr_ctrl::LOCK_ENABLE_W
• ccu::pll_ddr_ctrl::LOCK_R
• ccu::pll_ddr_ctrl::PLL_EN_R
• ccu::pll_ddr_ctrl::PLL_EN_W
• ccu::pll_ddr_ctrl::PLL_INPUT_DIV2_R
• ccu::pll_ddr_ctrl::PLL_INPUT_DIV2_W
• ccu::pll_ddr_ctrl::PLL_LDO_EN_R
• ccu::pll_ddr_ctrl::PLL_LDO_EN_W
• ccu::pll_ddr_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_ddr_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_ddr_ctrl::PLL_N_R
• ccu::pll_ddr_ctrl::PLL_N_W
• ccu::pll_ddr_ctrl::PLL_OUTPUT_DIV2_R
• ccu::pll_ddr_ctrl::PLL_OUTPUT_DIV2_W
• ccu::pll_ddr_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_ddr_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_ddr_ctrl::PLL_SDM_EN_R
• ccu::pll_ddr_ctrl::PLL_SDM_EN_W
• ccu::pll_ddr_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_ddr_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_ddr_pat0_ctrl::FREQ_R
• ccu::pll_ddr_pat0_ctrl::FREQ_W
• ccu::pll_ddr_pat0_ctrl::SDM_CLK_SEL_R
• ccu::pll_ddr_pat0_ctrl::SDM_CLK_SEL_W
• ccu::pll_ddr_pat0_ctrl::SIG_DELT_PAT_EN_R
• ccu::pll_ddr_pat0_ctrl::SIG_DELT_PAT_EN_W
• ccu::pll_ddr_pat0_ctrl::SPR_FREQ_MODE_R
• ccu::pll_ddr_pat0_ctrl::SPR_FREQ_MODE_W
• ccu::pll_ddr_pat0_ctrl::WAVE_BOT_R
• ccu::pll_ddr_pat0_ctrl::WAVE_BOT_W
• ccu::pll_ddr_pat0_ctrl::WAVE_STEP_R
• ccu::pll_ddr_pat0_ctrl::WAVE_STEP_W
• ccu::pll_ddr_pat1_ctrl::DITHER_EN_R
• ccu::pll_ddr_pat1_ctrl::DITHER_EN_W
• ccu::pll_ddr_pat1_ctrl::FRAC_EN_R
• ccu::pll_ddr_pat1_ctrl::FRAC_EN_W
• ccu::pll_ddr_pat1_ctrl::FRAC_IN_R
• ccu::pll_ddr_pat1_ctrl::FRAC_IN_W
• ccu::pll_lock_dbg_ctrl::CLK_SRC_SEL_R
• ccu::pll_lock_dbg_ctrl::CLK_SRC_SEL_W
• ccu::pll_lock_dbg_ctrl::PLL_LOCK_FLAG_EN_R
• ccu::pll_lock_dbg_ctrl::PLL_LOCK_FLAG_EN_W
• ccu::pll_peri_bias::PLL_CP_R
• ccu::pll_peri_bias::PLL_CP_W
• ccu::pll_peri_ctrl::LOCK_ENABLE_R
• ccu::pll_peri_ctrl::LOCK_ENABLE_W
• ccu::pll_peri_ctrl::LOCK_R
• ccu::pll_peri_ctrl::PLL_EN_R
• ccu::pll_peri_ctrl::PLL_EN_W
• ccu::pll_peri_ctrl::PLL_INPUT_DIV2_R
• ccu::pll_peri_ctrl::PLL_INPUT_DIV2_W
• ccu::pll_peri_ctrl::PLL_LDO_EN_R
• ccu::pll_peri_ctrl::PLL_LDO_EN_W
• ccu::pll_peri_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_peri_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_peri_ctrl::PLL_N_R
• ccu::pll_peri_ctrl::PLL_N_W
• ccu::pll_peri_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_peri_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_peri_ctrl::PLL_P0_R
• ccu::pll_peri_ctrl::PLL_P0_W
• ccu::pll_peri_ctrl::PLL_P1_R
• ccu::pll_peri_ctrl::PLL_P1_W
• ccu::pll_peri_ctrl::PLL_SDM_EN_R
• ccu::pll_peri_ctrl::PLL_SDM_EN_W
• ccu::pll_peri_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_peri_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_peri_pat0_ctrl::FREQ_R
• ccu::pll_peri_pat0_ctrl::FREQ_W
• ccu::pll_peri_pat0_ctrl::SDM_CLK_SEL_R
• ccu::pll_peri_pat0_ctrl::SDM_CLK_SEL_W
• ccu::pll_peri_pat0_ctrl::SIG_DELT_PAT_EN_R
• ccu::pll_peri_pat0_ctrl::SIG_DELT_PAT_EN_W
• ccu::pll_peri_pat0_ctrl::SPR_FREQ_MODE_R
• ccu::pll_peri_pat0_ctrl::SPR_FREQ_MODE_W
• ccu::pll_peri_pat0_ctrl::WAVE_BOT_R
• ccu::pll_peri_pat0_ctrl::WAVE_BOT_W
• ccu::pll_peri_pat0_ctrl::WAVE_STEP_R
• ccu::pll_peri_pat0_ctrl::WAVE_STEP_W
• ccu::pll_peri_pat1_ctrl::DITHER_EN_R
• ccu::pll_peri_pat1_ctrl::DITHER_EN_W
• ccu::pll_peri_pat1_ctrl::FRAC_EN_R
• ccu::pll_peri_pat1_ctrl::FRAC_EN_W
• ccu::pll_peri_pat1_ctrl::FRAC_IN_R
• ccu::pll_peri_pat1_ctrl::FRAC_IN_W
• ccu::pll_ve_bias::PLL_CP_R
• ccu::pll_ve_bias::PLL_CP_W
• ccu::pll_ve_ctrl::LOCK_ENABLE_R
• ccu::pll_ve_ctrl::LOCK_ENABLE_W
• ccu::pll_ve_ctrl::LOCK_R
• ccu::pll_ve_ctrl::PLL_EN_R
• ccu::pll_ve_ctrl::PLL_EN_W
• ccu::pll_ve_ctrl::PLL_INPUT_DIV2_R
• ccu::pll_ve_ctrl::PLL_INPUT_DIV2_W
• ccu::pll_ve_ctrl::PLL_LDO_EN_R
• ccu::pll_ve_ctrl::PLL_LDO_EN_W
• ccu::pll_ve_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_ve_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_ve_ctrl::PLL_N_R
• ccu::pll_ve_ctrl::PLL_N_W
• ccu::pll_ve_ctrl::PLL_OUTPUT_DIV2_R
• ccu::pll_ve_ctrl::PLL_OUTPUT_DIV2_W
• ccu::pll_ve_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_ve_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_ve_ctrl::PLL_SDM_EN_R
• ccu::pll_ve_ctrl::PLL_SDM_EN_W
• ccu::pll_ve_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_ve_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_ve_pat0_ctrl::FREQ_R
• ccu::pll_ve_pat0_ctrl::FREQ_W
• ccu::pll_ve_pat0_ctrl::SDM_CLK_SEL_R
• ccu::pll_ve_pat0_ctrl::SDM_CLK_SEL_W
• ccu::pll_ve_pat0_ctrl::SIG_DELT_PAT_EN_R
• ccu::pll_ve_pat0_ctrl::SIG_DELT_PAT_EN_W
• ccu::pll_ve_pat0_ctrl::SPR_FREQ_MODE_R
• ccu::pll_ve_pat0_ctrl::SPR_FREQ_MODE_W
• ccu::pll_ve_pat0_ctrl::WAVE_BOT_R
• ccu::pll_ve_pat0_ctrl::WAVE_BOT_W
• ccu::pll_ve_pat0_ctrl::WAVE_STEP_R
• ccu::pll_ve_pat0_ctrl::WAVE_STEP_W
• ccu::pll_ve_pat1_ctrl::DITHER_EN_R
• ccu::pll_ve_pat1_ctrl::DITHER_EN_W
• ccu::pll_ve_pat1_ctrl::FRAC_EN_R
• ccu::pll_ve_pat1_ctrl::FRAC_EN_W
• ccu::pll_ve_pat1_ctrl::FRAC_IN_R
• ccu::pll_ve_pat1_ctrl::FRAC_IN_W
• ccu::pll_video0_bias::PLL_CP_R
• ccu::pll_video0_bias::PLL_CP_W
• ccu::pll_video0_ctrl::LOCK_ENABLE_R
• ccu::pll_video0_ctrl::LOCK_ENABLE_W
• ccu::pll_video0_ctrl::LOCK_R
• ccu::pll_video0_ctrl::PLL_EN_R
• ccu::pll_video0_ctrl::PLL_EN_W
• ccu::pll_video0_ctrl::PLL_INPUT_DIV2_R
• ccu::pll_video0_ctrl::PLL_INPUT_DIV2_W
• ccu::pll_video0_ctrl::PLL_LDO_EN_R
• ccu::pll_video0_ctrl::PLL_LDO_EN_W
• ccu::pll_video0_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_video0_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_video0_ctrl::PLL_N_R
• ccu::pll_video0_ctrl::PLL_N_W
• ccu::pll_video0_ctrl::PLL_OUTPUT_DIV2_R
• ccu::pll_video0_ctrl::PLL_OUTPUT_DIV2_W
• ccu::pll_video0_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_video0_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_video0_ctrl::PLL_SDM_EN_R
• ccu::pll_video0_ctrl::PLL_SDM_EN_W
• ccu::pll_video0_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_video0_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_video0_pat0_ctrl::FREQ_R
• ccu::pll_video0_pat0_ctrl::FREQ_W
• ccu::pll_video0_pat0_ctrl::SDM_CLK_SEL_R
• ccu::pll_video0_pat0_ctrl::SDM_CLK_SEL_W
• ccu::pll_video0_pat0_ctrl::SIG_DELT_PAT_EN_R
• ccu::pll_video0_pat0_ctrl::SIG_DELT_PAT_EN_W
• ccu::pll_video0_pat0_ctrl::SPR_FREQ_MODE_R
• ccu::pll_video0_pat0_ctrl::SPR_FREQ_MODE_W
• ccu::pll_video0_pat0_ctrl::WAVE_BOT_R
• ccu::pll_video0_pat0_ctrl::WAVE_BOT_W
• ccu::pll_video0_pat0_ctrl::WAVE_STEP_R
• ccu::pll_video0_pat0_ctrl::WAVE_STEP_W
• ccu::pll_video0_pat1_ctrl::DITHER_EN_R
• ccu::pll_video0_pat1_ctrl::DITHER_EN_W
• ccu::pll_video0_pat1_ctrl::FRAC_EN_R
• ccu::pll_video0_pat1_ctrl::FRAC_EN_W
• ccu::pll_video0_pat1_ctrl::FRAC_IN_R
• ccu::pll_video0_pat1_ctrl::FRAC_IN_W
• ccu::pll_video1_bias::PLL_CP_R
• ccu::pll_video1_bias::PLL_CP_W
• ccu::pll_video1_ctrl::LOCK_ENABLE_R
• ccu::pll_video1_ctrl::LOCK_ENABLE_W
• ccu::pll_video1_ctrl::LOCK_R
• ccu::pll_video1_ctrl::PLL_EN_R
• ccu::pll_video1_ctrl::PLL_EN_W
• ccu::pll_video1_ctrl::PLL_INPUT_DIV2_R
• ccu::pll_video1_ctrl::PLL_INPUT_DIV2_W
• ccu::pll_video1_ctrl::PLL_LDO_EN_R
• ccu::pll_video1_ctrl::PLL_LDO_EN_W
• ccu::pll_video1_ctrl::PLL_LOCK_MDSEL_R
• ccu::pll_video1_ctrl::PLL_LOCK_MDSEL_W
• ccu::pll_video1_ctrl::PLL_N_R
• ccu::pll_video1_ctrl::PLL_N_W
• ccu::pll_video1_ctrl::PLL_OUTPUT_DIV2_R
• ccu::pll_video1_ctrl::PLL_OUTPUT_DIV2_W
• ccu::pll_video1_ctrl::PLL_OUTPUT_GATE_R
• ccu::pll_video1_ctrl::PLL_OUTPUT_GATE_W
• ccu::pll_video1_ctrl::PLL_SDM_EN_R
• ccu::pll_video1_ctrl::PLL_SDM_EN_W
• ccu::pll_video1_ctrl::PLL_UNLOCK_MDSEL_R
• ccu::pll_video1_ctrl::PLL_UNLOCK_MDSEL_W
• ccu::pll_video1_pat0_ctrl::FREQ_R
• ccu::pll_video1_pat0_ctrl::FREQ_W
• ccu::pll_video1_pat0_ctrl::SDM_CLK_SEL_R
• ccu::pll_video1_pat0_ctrl::SDM_CLK_SEL_W
• ccu::pll_video1_pat0_ctrl::SIG_DELT_PAT_EN_R
• ccu::pll_video1_pat0_ctrl::SIG_DELT_PAT_EN_W
• ccu::pll_video1_pat0_ctrl::SPR_FREQ_MODE_R
• ccu::pll_video1_pat0_ctrl::SPR_FREQ_MODE_W
• ccu::pll_video1_pat0_ctrl::WAVE_BOT_R
• ccu::pll_video1_pat0_ctrl::WAVE_BOT_W
• ccu::pll_video1_pat0_ctrl::WAVE_STEP_R
• ccu::pll_video1_pat0_ctrl::WAVE_STEP_W
• ccu::pll_video1_pat1_ctrl::DITHER_EN_R
• ccu::pll_video1_pat1_ctrl::DITHER_EN_W
• ccu::pll_video1_pat1_ctrl::FRAC_EN_R
• ccu::pll_video1_pat1_ctrl::FRAC_EN_W
• ccu::pll_video1_pat1_ctrl::FRAC_IN_R
• ccu::pll_video1_pat1_ctrl::FRAC_IN_W
• ccu::psi_clk::CLK_SRC_SEL_R
• ccu::psi_clk::CLK_SRC_SEL_W
• ccu::psi_clk::FACTOR_M_R
• ccu::psi_clk::FACTOR_M_W
• ccu::psi_clk::FACTOR_N_R
• ccu::psi_clk::FACTOR_N_W
• ccu::pwm_bgr::GATING_R
• ccu::pwm_bgr::GATING_W
• ccu::pwm_bgr::RST_R
• ccu::pwm_bgr::RST_W
• ccu::riscv_cfg_bgr::GATING_R
• ccu::riscv_cfg_bgr::GATING_W
• ccu::riscv_cfg_bgr::RST_R
• ccu::riscv_cfg_bgr::RST_W
• ccu::riscv_clk::AXI_DIV_CFG_R
• ccu::riscv_clk::AXI_DIV_CFG_W
• ccu::riscv_clk::CLK_SRC_SEL_R
• ccu::riscv_clk::CLK_SRC_SEL_W
• ccu::riscv_clk::DIV_CFG_R
• ccu::riscv_clk::DIV_CFG_W
• ccu::riscv_gating::GATING_FIELD_R
• ccu::riscv_gating::GATING_FIELD_W
• ccu::riscv_gating::GATING_R
• ccu::riscv_gating::GATING_W
• ccu::smhc0_clk::CLK_GATING_R
• ccu::smhc0_clk::CLK_GATING_W
• ccu::smhc0_clk::CLK_SRC_SEL_R
• ccu::smhc0_clk::CLK_SRC_SEL_W
• ccu::smhc0_clk::FACTOR_M_R
• ccu::smhc0_clk::FACTOR_M_W
• ccu::smhc0_clk::FACTOR_N_R
• ccu::smhc0_clk::FACTOR_N_W
• ccu::smhc1_clk::CLK_GATING_R
• ccu::smhc1_clk::CLK_GATING_W
• ccu::smhc1_clk::CLK_SRC_SEL_R
• ccu::smhc1_clk::CLK_SRC_SEL_W
• ccu::smhc1_clk::FACTOR_M_R
• ccu::smhc1_clk::FACTOR_M_W
• ccu::smhc1_clk::FACTOR_N_R
• ccu::smhc1_clk::FACTOR_N_W
• ccu::smhc2_clk::CLK_GATING_R
• ccu::smhc2_clk::CLK_GATING_W
• ccu::smhc2_clk::CLK_SRC_SEL_R
• ccu::smhc2_clk::CLK_SRC_SEL_W
• ccu::smhc2_clk::FACTOR_M_R
• ccu::smhc2_clk::FACTOR_M_W
• ccu::smhc2_clk::FACTOR_N_R
• ccu::smhc2_clk::FACTOR_N_W
• ccu::smhc_bgr::SMHC_GATING_R
• ccu::smhc_bgr::SMHC_GATING_W
• ccu::smhc_bgr::SMHC_RST_R
• ccu::smhc_bgr::SMHC_RST_W
• ccu::spi0_clk::CLK_GATING_R
• ccu::spi0_clk::CLK_GATING_W
• ccu::spi0_clk::CLK_SRC_SEL_R
• ccu::spi0_clk::CLK_SRC_SEL_W
• ccu::spi0_clk::FACTOR_M_R
• ccu::spi0_clk::FACTOR_M_W
• ccu::spi0_clk::FACTOR_N_R
• ccu::spi0_clk::FACTOR_N_W
• ccu::spi1_clk::CLK_GATING_R
• ccu::spi1_clk::CLK_GATING_W
• ccu::spi1_clk::CLK_SRC_SEL_R
• ccu::spi1_clk::CLK_SRC_SEL_W
• ccu::spi1_clk::FACTOR_M_R
• ccu::spi1_clk::FACTOR_M_W
• ccu::spi1_clk::FACTOR_N_R
• ccu::spi1_clk::FACTOR_N_W
• ccu::spi_bgr::SPI_GATING_R
• ccu::spi_bgr::SPI_GATING_W
• ccu::spi_bgr::SPI_RST_R
• ccu::spi_bgr::SPI_RST_W
• ccu::spinlock_bgr::GATING_R
• ccu::spinlock_bgr::GATING_W
• ccu::spinlock_bgr::RST_R
• ccu::spinlock_bgr::RST_W
• ccu::tconlcd_bgr::GATING_R
• ccu::tconlcd_bgr::GATING_W
• ccu::tconlcd_bgr::RST_R
• ccu::tconlcd_bgr::RST_W
• ccu::tconlcd_clk::CLK_GATING_R
• ccu::tconlcd_clk::CLK_GATING_W
• ccu::tconlcd_clk::CLK_SRC_SEL_R
• ccu::tconlcd_clk::CLK_SRC_SEL_W
• ccu::tconlcd_clk::FACTOR_M_R
• ccu::tconlcd_clk::FACTOR_M_W
• ccu::tconlcd_clk::FACTOR_N_R
• ccu::tconlcd_clk::FACTOR_N_W
• ccu::tcontv_bgr::GATING_R
• ccu::tcontv_bgr::GATING_W
• ccu::tcontv_bgr::RST_R
• ccu::tcontv_bgr::RST_W
• ccu::tcontv_clk::CLK_GATING_R
• ccu::tcontv_clk::CLK_GATING_W
• ccu::tcontv_clk::CLK_SRC_SEL_R
• ccu::tcontv_clk::CLK_SRC_SEL_W
• ccu::tcontv_clk::FACTOR_M_R
• ccu::tcontv_clk::FACTOR_M_W
• ccu::tcontv_clk::FACTOR_N_R
• ccu::tcontv_clk::FACTOR_N_W
• ccu::ths_bgr::GATING_R
• ccu::ths_bgr::GATING_W
• ccu::ths_bgr::RST_R
• ccu::ths_bgr::RST_W
• ccu::tpadc_bgr::GATING_R
• ccu::tpadc_bgr::GATING_W
• ccu::tpadc_bgr::RST_R
• ccu::tpadc_bgr::RST_W
• ccu::tpadc_clk::CLK_GATING_R
• ccu::tpadc_clk::CLK_GATING_W
• ccu::tpadc_clk::CLK_SRC_SEL_R
• ccu::tpadc_clk::CLK_SRC_SEL_W
• ccu::tvd_bgr::GATING_R
• ccu::tvd_bgr::GATING_W
• ccu::tvd_bgr::RST_R
• ccu::tvd_bgr::RST_W
• ccu::tvd_bgr::TOP_GATING_R
• ccu::tvd_bgr::TOP_GATING_W
• ccu::tvd_bgr::TOP_RST_R
• ccu::tvd_bgr::TOP_RST_W
• ccu::tvd_clk::CLK_GATING_R
• ccu::tvd_clk::CLK_GATING_W
• ccu::tvd_clk::CLK_SRC_SEL_R
• ccu::tvd_clk::CLK_SRC_SEL_W
• ccu::tvd_clk::FACTOR_M_R
• ccu::tvd_clk::FACTOR_M_W
• ccu::tve_bgr::GATING_R
• ccu::tve_bgr::GATING_W
• ccu::tve_bgr::RST_R
• ccu::tve_bgr::RST_W
• ccu::tve_bgr::TOP_GATING_R
• ccu::tve_bgr::TOP_GATING_W
• ccu::tve_bgr::TOP_RST_R
• ccu::tve_bgr::TOP_RST_W
• ccu::tve_clk::CLK_GATING_R
• ccu::tve_clk::CLK_GATING_W
• ccu::tve_clk::CLK_SRC_SEL_R
• ccu::tve_clk::CLK_SRC_SEL_W
• ccu::tve_clk::FACTOR_M_R
• ccu::tve_clk::FACTOR_M_W
• ccu::tve_clk::FACTOR_N_R
• ccu::tve_clk::FACTOR_N_W
• ccu::twi_bgr::TWI_GATING_R
• ccu::twi_bgr::TWI_GATING_W
• ccu::twi_bgr::TWI_RST_R
• ccu::twi_bgr::TWI_RST_W
• ccu::uart_bgr::UART_GATING_R
• ccu::uart_bgr::UART_GATING_W
• ccu::uart_bgr::UART_RST_R
• ccu::uart_bgr::UART_RST_W
• ccu::usb0_clk::CLK12M_SEL_R
• ccu::usb0_clk::CLK12M_SEL_W
• ccu::usb0_clk::CLKEN_R
• ccu::usb0_clk::CLKEN_W
• ccu::usb0_clk::RSTN_R
• ccu::usb0_clk::RSTN_W
• ccu::usb1_clk::CLK12M_SEL_R
• ccu::usb1_clk::CLK12M_SEL_W
• ccu::usb1_clk::CLKEN_R
• ccu::usb1_clk::CLKEN_W
• ccu::usb1_clk::RSTN_R
• ccu::usb1_clk::RSTN_W
• ccu::usb_bgr::USBEHCI_GATING_R
• ccu::usb_bgr::USBEHCI_GATING_W
• ccu::usb_bgr::USBEHCI_RST_R
• ccu::usb_bgr::USBEHCI_RST_W
• ccu::usb_bgr::USBOHCI_GATING_R
• ccu::usb_bgr::USBOHCI_GATING_W
• ccu::usb_bgr::USBOHCI_RST_R
• ccu::usb_bgr::USBOHCI_RST_W
• ccu::usb_bgr::USBOTG0_GATING_R
• ccu::usb_bgr::USBOTG0_GATING_W
• ccu::usb_bgr::USBOTG0_RST_R
• ccu::usb_bgr::USBOTG0_RST_W
• ccu::ve_bgr::GATING_R
• ccu::ve_bgr::GATING_W
• ccu::ve_bgr::RST_R
• ccu::ve_bgr::RST_W
• ccu::ve_clk::CLK_GATING_R
• ccu::ve_clk::CLK_GATING_W
• ccu::ve_clk::CLK_SRC_SEL_R
• ccu::ve_clk::CLK_SRC_SEL_W
• ccu::ve_clk::FACTOR_M_R
• ccu::ve_clk::FACTOR_M_W
• ce_ns::CE_CDA
• ce_ns::CE_CSA
• ce_ns::CE_ESR
• ce_ns::CE_ICR
• ce_ns::CE_ISR
• ce_ns::CE_TDA
• ce_ns::CE_TLR
• ce_ns::CE_TPR
• ce_ns::CE_TSR
• ce_ns::ce_cda::CUR_DST_ADDR_R
• ce_ns::ce_csa::CUR_SRC_ADDR_R
• ce_ns::ce_esr::TASK_CHANNEL_ERROR_TYPE_R
• ce_ns::ce_esr::TASK_CHANNEL_ERROR_TYPE_W
• ce_ns::ce_icr::TASK_IRQ_EN_R
• ce_ns::ce_icr::TASK_IRQ_EN_W
• ce_ns::ce_isr::TASK_PENDING_R
• ce_ns::ce_isr::TASK_PENDING_W
• ce_ns::ce_tda::TASK_R
• ce_ns::ce_tda::TASK_W
• ce_ns::ce_tlr::TASK_LOAD_R
• ce_ns::ce_tlr::TASK_LOAD_W
• ce_ns::ce_tpr::TP_NUM_R
• ce_ns::ce_tpr::TP_NUM_W
• ce_ns::ce_tsr::RUNNING_CHANNEL_NUMBER_R
• cir_rx::CIR_CTL
• cir_rx::CIR_RXCFG
• cir_rx::CIR_RXFIFO
• cir_rx::CIR_RXINT
• cir_rx::CIR_RXPCFG
• cir_rx::CIR_RXSTA
• cir_rx::cir_ctl::APAM_R
• cir_rx::cir_ctl::APAM_W
• cir_rx::cir_ctl::CIREN_R
• cir_rx::cir_ctl::CIREN_W
• cir_rx::cir_ctl::GEN_R
• cir_rx::cir_ctl::GEN_W
• cir_rx::cir_ctl::RXEN_R
• cir_rx::cir_ctl::RXEN_W
• cir_rx::cir_rxcfg::ATHC_R
• cir_rx::cir_rxcfg::ATHC_W
• cir_rx::cir_rxcfg::ATHR_R
• cir_rx::cir_rxcfg::ATHR_W
• cir_rx::cir_rxcfg::ITHR_R
• cir_rx::cir_rxcfg::ITHR_W
• cir_rx::cir_rxcfg::NTHR_R
• cir_rx::cir_rxcfg::NTHR_W
• cir_rx::cir_rxcfg::SCS2_R
• cir_rx::cir_rxcfg::SCS2_W
• cir_rx::cir_rxcfg::SCS_R
• cir_rx::cir_rxcfg::SCS_W
• cir_rx::cir_rxfifo::RBF_R
• cir_rx::cir_rxint::DRQ_EN_R
• cir_rx::cir_rxint::DRQ_EN_W
• cir_rx::cir_rxint::RAI_EN_R
• cir_rx::cir_rxint::RAI_EN_W
• cir_rx::cir_rxint::RAL_R
• cir_rx::cir_rxint::RAL_W
• cir_rx::cir_rxint::ROI_EN_R
• cir_rx::cir_rxint::ROI_EN_W
• cir_rx::cir_rxint::RPEI_EN_R
• cir_rx::cir_rxint::RPEI_EN_W
• cir_rx::cir_rxpcfg::RPPI_R
• cir_rx::cir_rxpcfg::RPPI_W
• cir_rx::cir_rxsta::RAC_R
• cir_rx::cir_rxsta::RA_R
• cir_rx::cir_rxsta::RA_W
• cir_rx::cir_rxsta::ROI_R
• cir_rx::cir_rxsta::ROI_W
• cir_rx::cir_rxsta::RPE_R
• cir_rx::cir_rxsta::RPE_W
• cir_rx::cir_rxsta::STAT_R
• cir_tx::CIR_DMA_CTL
• cir_tx::CIR_IDC_H
• cir_tx::CIR_IDC_L
• cir_tx::CIR_TAC
• cir_tx::CIR_TCR
• cir_tx::CIR_TEL
• cir_tx::CIR_TGLR
• cir_tx::CIR_TICR_H
• cir_tx::CIR_TICR_L
• cir_tx::CIR_TMCR
• cir_tx::CIR_TXFIFO
• cir_tx::CIR_TXINT
• cir_tx::CIR_TXSTA
• cir_tx::CIR_TXT
• cir_tx::cir_dma_ctl::DMA_R
• cir_tx::cir_dma_ctl::DMA_W
• cir_tx::cir_idc_h::IDC_H_R
• cir_tx::cir_idc_h::IDC_H_W
• cir_tx::cir_idc_l::IDC_L_R
• cir_tx::cir_idc_l::IDC_L_W
• cir_tx::cir_tac::TAC_R
• cir_tx::cir_tcr::CSS_R
• cir_tx::cir_tcr::CSS_W
• cir_tx::cir_tcr::RCS_R
• cir_tx::cir_tcr::RCS_W
• cir_tx::cir_tcr::TTS_R
• cir_tx::cir_tcr::TTS_W
• cir_tx::cir_tel::TEL_R
• cir_tx::cir_tel::TEL_W
• cir_tx::cir_tglr::DRMC_R
• cir_tx::cir_tglr::DRMC_W
• cir_tx::cir_tglr::IMS_R
• cir_tx::cir_tglr::IMS_W
• cir_tx::cir_tglr::TPPI_R
• cir_tx::cir_tglr::TPPI_W
• cir_tx::cir_tglr::TR_R
• cir_tx::cir_tglr::TR_W
• cir_tx::cir_tglr::TXEN_R
• cir_tx::cir_tglr::TXEN_W
• cir_tx::cir_ticr_h::TIC_H_R
• cir_tx::cir_ticr_l::TIC_L_R
• cir_tx::cir_tmcr::RFMC_R
• cir_tx::cir_tmcr::RFMC_W
• cir_tx::cir_txfifo::TBF_W
• cir_tx::cir_txint::DRQ_EN_R
• cir_tx::cir_txint::DRQ_EN_W
• cir_tx::cir_txint::TAI_EN_R
• cir_tx::cir_txint::TAI_EN_W
• cir_tx::cir_txint::TPEI_TUI_EN_R
• cir_tx::cir_txint::TPEI_TUI_EN_W
• cir_tx::cir_txsta::DRQ_R
• cir_tx::cir_txsta::STCT_R
• cir_tx::cir_txsta::TAI_R
• cir_tx::cir_txsta::TAI_W
• cir_tx::cir_txsta::TPE_TUR_R
• cir_tx::cir_txsta::TPE_TUR_W
• cir_tx::cir_txt::NCTT_R
• cir_tx::cir_txt::NCTT_W
• csic::csic_ccu::CCU_CLK_MODE_REG
• csic::csic_ccu::CCU_PARSER_CLK_EN_REG
• csic::csic_ccu::CCU_POST0_CLK_EN_REG
• csic::csic_dma::CSIC_DMA_ACC_ITNL_CLK_CNT_REG
• csic::csic_dma::CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG
• csic::csic_dma::CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG
• csic::csic_dma::CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG
• csic::csic_dma::CSIC_DMA_BUF_ADDR_FIFO_CON_REG
• csic::csic_dma::CSIC_DMA_BUF_LEN_REG
• csic::csic_dma::CSIC_DMA_BUF_TH_REG
• csic::csic_dma::CSIC_DMA_CAP_STA_REG
• csic::csic_dma::CSIC_DMA_CFG_REG
• csic::csic_dma::CSIC_DMA_EN_REG
• csic::csic_dma::CSIC_DMA_F0_BUFA_REG
• csic::csic_dma::CSIC_DMA_F0_BUFA_RESULT_REG
• csic::csic_dma::CSIC_DMA_F1_BUFA_REG
• csic::csic_dma::CSIC_DMA_F1_BUFA_RESULT_REG
• csic::csic_dma::CSIC_DMA_F2_BUFA_REG
• csic::csic_dma::CSIC_DMA_F2_BUFA_RESULT_REG
• csic::csic_dma::CSIC_DMA_FIFO_STAT_REG
• csic::csic_dma::CSIC_DMA_FIFO_THRS_REG
• csic::csic_dma::CSIC_DMA_FLIP_SIZE_REG
• csic::csic_dma::CSIC_DMA_FRM_CLK_CNT_REG
• csic::csic_dma::CSIC_DMA_FRM_CNT_REG
• csic::csic_dma::CSIC_DMA_HSIZE_REG
• csic::csic_dma::CSIC_DMA_INT_EN_REG
• csic::csic_dma::CSIC_DMA_INT_STA_REG
• csic::csic_dma::CSIC_DMA_LINE_CNT_REG
• csic::csic_dma::CSIC_DMA_PCLK_STAT_REG
• csic::csic_dma::CSIC_DMA_STORED_FRM_CNT_REG
• csic::csic_dma::CSIC_DMA_VI_TO_CNT_VAL_REG
• csic::csic_dma::CSIC_DMA_VI_TO_TH0_REG
• csic::csic_dma::CSIC_DMA_VI_TO_TH1_REG
• csic::csic_dma::CSIC_DMA_VSIZE_REG
• csic::csic_dma::CSIC_FEATURE_REG
• csic::csic_parser0::CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG
• csic::csic_parser0::CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG
• csic::csic_parser0::CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG
• csic::csic_parser0::CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG
• csic::csic_parser0::CSIC_PRS_SIGNAL_STA_REG
• csic::csic_parser0::PRS_C0_INFMT_REG
• csic::csic_parser0::PRS_C0_INPUT_PARA0_REG
• csic::csic_parser0::PRS_C0_INPUT_PARA1_REG
• csic::csic_parser0::PRS_C0_INPUT_PARA2_REG
• csic::csic_parser0::PRS_C0_INPUT_PARA3_REG
• csic::csic_parser0::PRS_C0_INT_EN_REG
• csic::csic_parser0::PRS_C0_INT_STA_REG
• csic::csic_parser0::PRS_C0_OUTPUT_HSIZE_REG
• csic::csic_parser0::PRS_C0_OUTPUT_VSIZE_REG
• csic::csic_parser0::PRS_C1_INFMT_REG
• csic::csic_parser0::PRS_C1_INPUT_PARA0_REG
• csic::csic_parser0::PRS_C1_INPUT_PARA1_REG
• csic::csic_parser0::PRS_C1_INPUT_PARA2_REG
• csic::csic_parser0::PRS_C1_INPUT_PARA3_REG
• csic::csic_parser0::PRS_C1_INT_EN_REG
• csic::csic_parser0::PRS_C1_INT_STA_REG
• csic::csic_parser0::PRS_C1_OUTPUT_HSIZE_REG
• csic::csic_parser0::PRS_C1_OUTPUT_VSIZE_REG
• csic::csic_parser0::PRS_C2_INFMT_REG
• csic::csic_parser0::PRS_C2_INPUT_PARA0_REG
• csic::csic_parser0::PRS_C2_INPUT_PARA1_REG
• csic::csic_parser0::PRS_C2_INPUT_PARA2_REG
• csic::csic_parser0::PRS_C2_INPUT_PARA3_REG
• csic::csic_parser0::PRS_C2_INT_EN_REG
• csic::csic_parser0::PRS_C2_INT_STA_REG
• csic::csic_parser0::PRS_C2_OUTPUT_HSIZE_REG
• csic::csic_parser0::PRS_C2_OUTPUT_VSIZE_REG
• csic::csic_parser0::PRS_C3_INFMT_REG
• csic::csic_parser0::PRS_C3_INPUT_PARA0_REG
• csic::csic_parser0::PRS_C3_INPUT_PARA1_REG
• csic::csic_parser0::PRS_C3_INPUT_PARA2_REG
• csic::csic_parser0::PRS_C3_INPUT_PARA3_REG
• csic::csic_parser0::PRS_C3_INT_EN_REG
• csic::csic_parser0::PRS_C3_INT_STA_REG
• csic::csic_parser0::PRS_C3_OUTPUT_HSIZE_REG
• csic::csic_parser0::PRS_C3_OUTPUT_VSIZE_REG
• csic::csic_parser0::PRS_CAP_REG
• csic::csic_parser0::PRS_CH0_LINE_TIME_REG
• csic::csic_parser0::PRS_CH1_LINE_TIME_REG
• csic::csic_parser0::PRS_CH2_LINE_TIME_REG
• csic::csic_parser0::PRS_CH3_LINE_TIME_REG
• csic::csic_parser0::PRS_EN_REG
• csic::csic_parser0::PRS_NCSIC_IF_CFG_REG
• csic::csic_top::CSIC_BIST_CONTROL_REG
• csic::csic_top::CSIC_BIST_CS_REG
• csic::csic_top::CSIC_BIST_DATA_MASK_REG
• csic::csic_top::CSIC_BIST_END_REG
• csic::csic_top::CSIC_BIST_START_REG
• csic::csic_top::CSIC_DMA0_INPUT_SEL_REG
• csic::csic_top::CSIC_DMA1_INPUT_SEL_REG
• csic::csic_top::CSIC_MBUS_REQ_MAX_REG
• csic::csic_top::CSIC_MULF_INT_REG
• csic::csic_top::CSIC_MULF_MOD_REG
• csic::csic_top::CSIC_PTN_ADDR_REG
• csic::csic_top::CSIC_PTN_CTRL_REG
• csic::csic_top::CSIC_PTN_GEN_EN_REG
• csic::csic_top::CSIC_PTN_ISP_SIZE_REG
• csic::csic_top::CSIC_PTN_LEN_REG
• csic::csic_top::CSIC_TOP_EN_REG
• dmac::DMAC_AUTO_GATE_REG
• dmac::DMAC_BCNT_LEFT_REG
• dmac::DMAC_CFG_REG
• dmac::DMAC_CUR_DEST_REG
• dmac::DMAC_CUR_SRC_REG
• dmac::DMAC_DESC_ADDR_REG
• dmac::DMAC_EN_REG
• dmac::DMAC_FDESC_ADDR_REG
• dmac::DMAC_IRQ_EN_REG0
• dmac::DMAC_IRQ_EN_REG1
• dmac::DMAC_IRQ_PEND_REG0
• dmac::DMAC_IRQ_PEND_REG1
• dmac::DMAC_MODE_REG
• dmac::DMAC_PARA_REG
• dmac::DMAC_PAU_REG
• dmac::DMAC_PKG_NUM_REG
• dmac::DMAC_STA_REG
• dmac::dmac_auto_gate_reg::DMA_CHAN_CIRCUIT_R
• dmac::dmac_auto_gate_reg::DMA_CHAN_CIRCUIT_W
• dmac::dmac_auto_gate_reg::DMA_COMMON_CIRCUIT_R
• dmac::dmac_auto_gate_reg::DMA_COMMON_CIRCUIT_W
• dmac::dmac_auto_gate_reg::DMA_MCLK_CIRCUIT_R
• dmac::dmac_auto_gate_reg::DMA_MCLK_CIRCUIT_W
• dmac::dmac_bcnt_left_reg::DMA_BCNT_LEFT_R
• dmac::dmac_cfg_reg::BMODE_SEL_R
• dmac::dmac_cfg_reg::DMA_ADDR_MODE_R
• dmac::dmac_cfg_reg::DMA_DEST_BLOCK_SIZE_R
• dmac::dmac_cfg_reg::DMA_DEST_DATA_WIDTH_R
• dmac::dmac_cfg_reg::DMA_DEST_DRQ_TYPE_R
• dmac::dmac_cfg_reg::DMA_SRC_ADDR_MODE_R
• dmac::dmac_cfg_reg::DMA_SRC_BLOCK_SIZE_R
• dmac::dmac_cfg_reg::DMA_SRC_DATA_WIDTH_R
• dmac::dmac_cfg_reg::DMA_SRC_DRQ_TYPE_R
• dmac::dmac_desc_addr_reg::DMA_DESC_ADDR_R
• dmac::dmac_desc_addr_reg::DMA_DESC_ADDR_W
• dmac::dmac_desc_addr_reg::DMA_DESC_HIGH_ADDR_R
• dmac::dmac_desc_addr_reg::DMA_DESC_HIGH_ADDR_W
• dmac::dmac_en_reg::DMA_EN_R
• dmac::dmac_en_reg::DMA_EN_W
• dmac::dmac_irq_en_reg0::DMA_HLAF_IRQ_EN_R
• dmac::dmac_irq_en_reg0::DMA_HLAF_IRQ_EN_W
• dmac::dmac_irq_en_reg0::DMA_PKG_IRQ_EN_R
• dmac::dmac_irq_en_reg0::DMA_PKG_IRQ_EN_W
• dmac::dmac_irq_en_reg0::DMA_QUEUE_IRQ_EN_R
• dmac::dmac_irq_en_reg0::DMA_QUEUE_IRQ_EN_W
• dmac::dmac_irq_en_reg1::DMA_HLAF_IRQ_EN_R
• dmac::dmac_irq_en_reg1::DMA_HLAF_IRQ_EN_W
• dmac::dmac_irq_en_reg1::DMA_PKG_IRQ_EN_R
• dmac::dmac_irq_en_reg1::DMA_PKG_IRQ_EN_W
• dmac::dmac_irq_en_reg1::DMA_QUEUE_IRQ_EN_R
• dmac::dmac_irq_en_reg1::DMA_QUEUE_IRQ_EN_W
• dmac::dmac_irq_pend_reg0::DMA_HLAF_IRQ_PEND_R
• dmac::dmac_irq_pend_reg0::DMA_HLAF_IRQ_PEND_W
• dmac::dmac_irq_pend_reg0::DMA_PKG_IRQ_PEND_R
• dmac::dmac_irq_pend_reg0::DMA_PKG_IRQ_PEND_W
• dmac::dmac_irq_pend_reg0::DMA_QUEUE_IRQ_PEND_R
• dmac::dmac_irq_pend_reg0::DMA_QUEUE_IRQ_PEND_W
• dmac::dmac_irq_pend_reg1::DMA_HLAF_IRQ_PEND_R
• dmac::dmac_irq_pend_reg1::DMA_HLAF_IRQ_PEND_W
• dmac::dmac_irq_pend_reg1::DMA_PKG_IRQ_PEND_R
• dmac::dmac_irq_pend_reg1::DMA_PKG_IRQ_PEND_W
• dmac::dmac_irq_pend_reg1::DMA_QUEUE_IRQ_PEND_R
• dmac::dmac_irq_pend_reg1::DMA_QUEUE_IRQ_PEND_W
• dmac::dmac_mode_reg::DMA_DST_MODE_R
• dmac::dmac_mode_reg::DMA_DST_MODE_W
• dmac::dmac_mode_reg::DMA_SRC_MODE_R
• dmac::dmac_mode_reg::DMA_SRC_MODE_W
• dmac::dmac_para_reg::WAIT_CYC_R
• dmac::dmac_pau_reg::DMA_PAUSE_R
• dmac::dmac_pau_reg::DMA_PAUSE_W
• dmac::dmac_sta_reg::DMA_STATUS_R
• dmac::dmac_sta_reg::MBUS_FIFO_STATUS_R
• dmic::DATA0_DATA1_VOL_CTR
• dmic::DATA2_DATA3_VOL_CTR
• dmic::DMIC_CH_MAP
• dmic::DMIC_CH_NUM
• dmic::DMIC_CNT
• dmic::DMIC_CTR
• dmic::DMIC_DATA
• dmic::DMIC_EN
• dmic::DMIC_INTC
• dmic::DMIC_INTS
• dmic::DMIC_RXFIFO_CTR
• dmic::DMIC_RXFIFO_STA
• dmic::DMIC_SR
• dmic::HPF_COEF_REG
• dmic::HPF_EN_CTR
• dmic::HPF_GAIN_REG
• dsp_msgbox::msgbox::MSGBOX_DEBUG_REG
• dsp_msgbox::msgbox::MSGBOX_FIFO_STATUS_REG
• dsp_msgbox::msgbox::MSGBOX_MSG_REG
• dsp_msgbox::msgbox::MSGBOX_MSG_STATUS_REG
• dsp_msgbox::msgbox::MSGBOX_RD_IRQ_EN_REG
• dsp_msgbox::msgbox::MSGBOX_RD_IRQ_STATUS_REG
• dsp_msgbox::msgbox::MSGBOX_WR_INT_THRESHOLD_REG
• dsp_msgbox::msgbox::MSGBOX_WR_IRQ_EN_REG
• dsp_msgbox::msgbox::MSGBOX_WR_IRQ_STATUS_REG
• dsp_msgbox::msgbox::msgbox_fifo_status_reg::FIFO_NOT_AVA_FLAG_R
• dsp_msgbox::msgbox::msgbox_msg_reg::MSG_QUE_R
• dsp_msgbox::msgbox::msgbox_msg_reg::MSG_QUE_W
• dsp_msgbox::msgbox::msgbox_msg_status_reg::MSG_NUM_R
• dsp_msgbox::msgbox::msgbox_rd_irq_en_reg::RECEPTION_MQ_IRQ_EN_R
• dsp_msgbox::msgbox::msgbox_rd_irq_en_reg::RECEPTION_MQ_IRQ_EN_W
• dsp_msgbox::msgbox::msgbox_rd_irq_status_reg::RECEPTION_MQ_IRQ_PEND_R
• dsp_msgbox::msgbox::msgbox_rd_irq_status_reg::RECEPTION_MQ_IRQ_PEND_W
• dsp_msgbox::msgbox::msgbox_wr_int_threshold_reg::MSG_WR_INT_THRESHOLD_CFG_R
• dsp_msgbox::msgbox::msgbox_wr_int_threshold_reg::MSG_WR_INT_THRESHOLD_CFG_W
• dsp_msgbox::msgbox::msgbox_wr_irq_en_reg::TRANSMIT_MQ_IRQ_EN_R
• dsp_msgbox::msgbox::msgbox_wr_irq_en_reg::TRANSMIT_MQ_IRQ_EN_W
• dsp_msgbox::msgbox::msgbox_wr_irq_status_reg::TRANSMIT_MQ_IRQ_PEND_R
• dsp_msgbox::msgbox::msgbox_wr_irq_status_reg::TRANSMIT_MQ_IRQ_PEND_W
• emac::EMAC_ADDR_HIGH
• emac::EMAC_ADDR_HIGH0
• emac::EMAC_ADDR_LOW
• emac::EMAC_BASIC_CTL0
• emac::EMAC_BASIC_CTL1
• emac::EMAC_INT_EN
• emac::EMAC_INT_STA
• emac::EMAC_MII_CMD
• emac::EMAC_MII_DATA
• emac::EMAC_RGMII_STA
• emac::EMAC_RX_CTL0
• emac::EMAC_RX_CTL1
• emac::EMAC_RX_CUR_BUF
• emac::EMAC_RX_CUR_DESC
• emac::EMAC_RX_DMA_DESC_LIST
• emac::EMAC_RX_DMA_STA
• emac::EMAC_RX_FRM_FLT
• emac::EMAC_RX_HASH0
• emac::EMAC_RX_HASH1
• emac::EMAC_TX_CTL0
• emac::EMAC_TX_CTL1
• emac::EMAC_TX_CUR_BUF
• emac::EMAC_TX_CUR_DESC
• emac::EMAC_TX_DMA_DESC_LIST
• emac::EMAC_TX_DMA_STA
• emac::EMAC_TX_FLOW_CTL
• emac::emac_addr_high0::MAC_ADDR_HIGH0_R
• emac::emac_addr_high0::MAC_ADDR_HIGH0_W
• emac::emac_addr_high::MAC_ADDR_BYTE_CTL_R
• emac::emac_addr_high::MAC_ADDR_BYTE_CTL_W
• emac::emac_addr_high::MAC_ADDR_CTL_R
• emac::emac_addr_high::MAC_ADDR_CTL_W
• emac::emac_addr_high::MAC_ADDR_HIGH_R
• emac::emac_addr_high::MAC_ADDR_HIGH_W
• emac::emac_addr_high::MAC_ADDR_TYPE_R
• emac::emac_addr_high::MAC_ADDR_TYPE_W
• emac::emac_basic_ctl0::DUPLEX_R
• emac::emac_basic_ctl0::DUPLEX_W
• emac::emac_basic_ctl0::LOOPBACK_R
• emac::emac_basic_ctl0::LOOPBACK_W
• emac::emac_basic_ctl0::SPEED_R
• emac::emac_basic_ctl0::SPEED_W
• emac::emac_basic_ctl1::BURST_LEN_R
• emac::emac_basic_ctl1::BURST_LEN_W
• emac::emac_basic_ctl1::RX_TX_PRI_R
• emac::emac_basic_ctl1::RX_TX_PRI_W
• emac::emac_basic_ctl1::SOFT_RST_R
• emac::emac_basic_ctl1::SOFT_RST_W
• emac::emac_int_en::RX_BUF_UA_INT_EN_R
• emac::emac_int_en::RX_BUF_UA_INT_EN_W
• emac::emac_int_en::RX_DMA_STOPPED_INT_EN_R
• emac::emac_int_en::RX_DMA_STOPPED_INT_EN_W
• emac::emac_int_en::RX_EARLY_INT_EN_R
• emac::emac_int_en::RX_EARLY_INT_EN_W
• emac::emac_int_en::RX_INT_EN_R
• emac::emac_int_en::RX_INT_EN_W
• emac::emac_int_en::RX_OVERFLOW_INT_EN_R
• emac::emac_int_en::RX_OVERFLOW_INT_EN_W
• emac::emac_int_en::RX_TIMEOUT_INT_EN_R
• emac::emac_int_en::RX_TIMEOUT_INT_EN_W
• emac::emac_int_en::TX_BUF_UA_INT_EN_R
• emac::emac_int_en::TX_BUF_UA_INT_EN_W
• emac::emac_int_en::TX_DMA_STOPPED_INT_EN_R
• emac::emac_int_en::TX_DMA_STOPPED_INT_EN_W
• emac::emac_int_en::TX_EARLY_INT_EN_R
• emac::emac_int_en::TX_EARLY_INT_EN_W
• emac::emac_int_en::TX_INT_EN_R
• emac::emac_int_en::TX_INT_EN_W
• emac::emac_int_en::TX_TIMEOUT_INT_EN_R
• emac::emac_int_en::TX_TIMEOUT_INT_EN_W
• emac::emac_int_en::TX_UNDERFLOW_INT_EN_R
• emac::emac_int_en::TX_UNDERFLOW_INT_EN_W
• emac::emac_int_sta::RGMII_LINK_STA_P_R
• emac::emac_int_sta::RGMII_LINK_STA_P_W
• emac::emac_int_sta::RX_BUF_UA_P_R
• emac::emac_int_sta::RX_BUF_UA_P_W
• emac::emac_int_sta::RX_DMA_STOPPED_P_R
• emac::emac_int_sta::RX_DMA_STOPPED_P_W
• emac::emac_int_sta::RX_EARLY_P_R
• emac::emac_int_sta::RX_EARLY_P_W
• emac::emac_int_sta::RX_OVERFLOW_P_R
• emac::emac_int_sta::RX_OVERFLOW_P_W
• emac::emac_int_sta::RX_P_R
• emac::emac_int_sta::RX_P_W
• emac::emac_int_sta::RX_TIMEOUT_P_R
• emac::emac_int_sta::RX_TIMEOUT_P_W
• emac::emac_int_sta::TX_BUF_UA_P_R
• emac::emac_int_sta::TX_BUF_UA_P_W
• emac::emac_int_sta::TX_DMA_STOPPED_P_R
• emac::emac_int_sta::TX_DMA_STOPPED_P_W
• emac::emac_int_sta::TX_EARLY_P_R
• emac::emac_int_sta::TX_EARLY_P_W
• emac::emac_int_sta::TX_P_R
• emac::emac_int_sta::TX_P_W
• emac::emac_int_sta::TX_TIMEOUT_P_R
• emac::emac_int_sta::TX_TIMEOUT_P_W
• emac::emac_int_sta::TX_UNDERFLOW_P_R
• emac::emac_int_sta::TX_UNDERFLOW_P_W
• emac::emac_mii_cmd::MDC_DIV_RATIO_M_R
• emac::emac_mii_cmd::MDC_DIV_RATIO_M_W
• emac::emac_mii_cmd::MII_BUSY_R
• emac::emac_mii_cmd::MII_BUSY_W
• emac::emac_mii_cmd::MII_WR_R
• emac::emac_mii_cmd::MII_WR_W
• emac::emac_mii_cmd::PHY_ADDR_R
• emac::emac_mii_cmd::PHY_ADDR_W
• emac::emac_mii_cmd::PHY_REG_ADDR_R
• emac::emac_mii_cmd::PHY_REG_ADDR_W
• emac::emac_mii_data::MII_DATA_R
• emac::emac_mii_data::MII_DATA_W
• emac::emac_rgmii_sta::RGMII_LINK_MD_R
• emac::emac_rgmii_sta::RGMII_LINK_MD_W
• emac::emac_rgmii_sta::RGMII_LINK_R
• emac::emac_rgmii_sta::RGMII_LINK_SPD_R
• emac::emac_rgmii_sta::RGMII_LINK_SPD_W
• emac::emac_rgmii_sta::RGMII_LINK_W
• emac::emac_rx_ctl0::CHECK_CRC_R
• emac::emac_rx_ctl0::CHECK_CRC_W
• emac::emac_rx_ctl0::JUMBO_FRM_EN_R
• emac::emac_rx_ctl0::JUMBO_FRM_EN_W
• emac::emac_rx_ctl0::RX_EN_R
• emac::emac_rx_ctl0::RX_EN_W
• emac::emac_rx_ctl0::RX_FLOW_CTL_EN_R
• emac::emac_rx_ctl0::RX_FLOW_CTL_EN_W
• emac::emac_rx_ctl0::RX_FRM_LEN_CTL_R
• emac::emac_rx_ctl0::RX_FRM_LEN_CTL_W
• emac::emac_rx_ctl0::RX_PAUSE_FRM_MD_R
• emac::emac_rx_ctl0::RX_PAUSE_FRM_MD_W
• emac::emac_rx_ctl0::STRIP_FCS_R
• emac::emac_rx_ctl0::STRIP_FCS_W
• emac::emac_rx_ctl1::FLUSH_RX_FRM_R
• emac::emac_rx_ctl1::FLUSH_RX_FRM_W
• emac::emac_rx_ctl1::RX_DMA_START_R
• emac::emac_rx_ctl1::RX_DMA_START_W
• emac::emac_rx_ctl1::RX_EMA_EN_R
• emac::emac_rx_ctl1::RX_EMA_EN_W
• emac::emac_rx_ctl1::RX_ERR_FRM_R
• emac::emac_rx_ctl1::RX_ERR_FRM_W
• emac::emac_rx_ctl1::RX_FIFO_FLOW_CTL_R
• emac::emac_rx_ctl1::RX_FIFO_FLOW_CTL_W
• emac::emac_rx_ctl1::RX_FLOW_CTL_TH_ACT_R
• emac::emac_rx_ctl1::RX_FLOW_CTL_TH_ACT_W
• emac::emac_rx_ctl1::RX_FLOW_CTL_TH_DEACT_R
• emac::emac_rx_ctl1::RX_FLOW_CTL_TH_DEACT_W
• emac::emac_rx_ctl1::RX_MD_R
• emac::emac_rx_ctl1::RX_MD_W
• emac::emac_rx_ctl1::RX_RUNT_FRM_R
• emac::emac_rx_ctl1::RX_RUNT_FRM_W
• emac::emac_rx_ctl1::RX_TH_R
• emac::emac_rx_ctl1::RX_TH_W
• emac::emac_rx_dma_sta::RX_DMA_STA_R
• emac::emac_rx_frm_flt::CTL_FRM_FILTER_R
• emac::emac_rx_frm_flt::CTL_FRM_FILTER_W
• emac::emac_rx_frm_flt::DA_INV_FILTER_R
• emac::emac_rx_frm_flt::DA_INV_FILTER_W
• emac::emac_rx_frm_flt::DIS_ADDR_FILTER_R
• emac::emac_rx_frm_flt::DIS_ADDR_FILTER_W
• emac::emac_rx_frm_flt::DIS_BROADCAST_R
• emac::emac_rx_frm_flt::DIS_BROADCAST_W
• emac::emac_rx_frm_flt::FLT_MD_R
• emac::emac_rx_frm_flt::FLT_MD_W
• emac::emac_rx_frm_flt::HASH_MULTICAST_R
• emac::emac_rx_frm_flt::HASH_MULTICAST_W
• emac::emac_rx_frm_flt::HASH_UNICAST_R
• emac::emac_rx_frm_flt::HASH_UNICAST_W
• emac::emac_rx_frm_flt::RX_ALL_MULTICAST_R
• emac::emac_rx_frm_flt::RX_ALL_MULTICAST_W
• emac::emac_rx_frm_flt::RX_ALL_R
• emac::emac_rx_frm_flt::RX_ALL_W
• emac::emac_rx_frm_flt::SA_FILTER_EN_R
• emac::emac_rx_frm_flt::SA_FILTER_EN_W
• emac::emac_rx_frm_flt::SA_INV_FILTER_R
• emac::emac_rx_frm_flt::SA_INV_FILTER_W
• emac::emac_tx_ctl0::TX_EN_R
• emac::emac_tx_ctl0::TX_EN_W
• emac::emac_tx_ctl0::TX_FRM_LEN_CTL_R
• emac::emac_tx_ctl0::TX_FRM_LEN_CTL_W
• emac::emac_tx_ctl1::FLUSH_TX_FIFO_R
• emac::emac_tx_ctl1::FLUSH_TX_FIFO_W
• emac::emac_tx_ctl1::TX_DMA_EN_R
• emac::emac_tx_ctl1::TX_DMA_EN_W
• emac::emac_tx_ctl1::TX_DMA_START_R
• emac::emac_tx_ctl1::TX_DMA_START_W
• emac::emac_tx_ctl1::TX_MD_R
• emac::emac_tx_ctl1::TX_MD_W
• emac::emac_tx_ctl1::TX_TH_R
• emac::emac_tx_ctl1::TX_TH_W
• emac::emac_tx_dma_sta::TX_DMA_STA_R
• emac::emac_tx_flow_ctl::PAUSE_TIME_R
• emac::emac_tx_flow_ctl::PAUSE_TIME_W
• emac::emac_tx_flow_ctl::TX_FLOW_CTL_EN_R
• emac::emac_tx_flow_ctl::TX_FLOW_CTL_EN_W
• emac::emac_tx_flow_ctl::TX_FLOW_CTL_STA_R
• emac::emac_tx_flow_ctl::TX_FLOW_CTL_STA_W
• emac::emac_tx_flow_ctl::TX_PAUSE_FRM_SLOT_R
• emac::emac_tx_flow_ctl::TX_PAUSE_FRM_SLOT_W
• emac::emac_tx_flow_ctl::ZQP_FRM_EN_R
• emac::emac_tx_flow_ctl::ZQP_FRM_EN_W
• generic::BitReader
• generic::BitWriter
• generic::BitWriter0C
• generic::BitWriter0S
• generic::BitWriter0T
• generic::BitWriter1C
• generic::BitWriter1S
• generic::BitWriter1T
• generic::FieldReader
• generic::FieldWriter
• generic::FieldWriterSafe
• gpadc::GP_CDATA
• gpadc::GP_CH0_CMP_DATA
• gpadc::GP_CH0_DATA
• gpadc::GP_CH1_CMP_DATA
• gpadc::GP_CH1_DATA
• gpadc::GP_CS_EN
• gpadc::GP_CTRL
• gpadc::GP_DATAH_INTC
• gpadc::GP_DATAH_INTS
• gpadc::GP_DATAL_INTC
• gpadc::GP_DATAL_INTS
• gpadc::GP_DATA_INTC
• gpadc::GP_DATA_INTS
• gpadc::GP_FIFO_DATA
• gpadc::GP_FIFO_INTC
• gpadc::GP_FIFO_INTS
• gpadc::GP_SR_CON
• gpadc::gp_cdata::GP_CDATA_R
• gpadc::gp_cdata::GP_CDATA_W
• gpadc::gp_ch0_cmp_data::CH0_CMP_HIG_DATA_R
• gpadc::gp_ch0_cmp_data::CH0_CMP_HIG_DATA_W
• gpadc::gp_ch0_cmp_data::CH0_CMP_LOW_DATA_R
• gpadc::gp_ch0_cmp_data::CH0_CMP_LOW_DATA_W
• gpadc::gp_ch0_data::GP_CH0_DATA_R
• gpadc::gp_ch1_cmp_data::CH1_CMP_HIG_DATA_R
• gpadc::gp_ch1_cmp_data::CH1_CMP_HIG_DATA_W
• gpadc::gp_ch1_cmp_data::CH1_CMP_LOW_DATA_R
• gpadc::gp_ch1_cmp_data::CH1_CMP_LOW_DATA_W
• gpadc::gp_ch1_data::GP_CH1_DATA_R
• gpadc::gp_cs_en::ADC_CH_CMP_EN_R
• gpadc::gp_cs_en::ADC_CH_CMP_EN_W
• gpadc::gp_cs_en::ADC_CH_SELECT_R
• gpadc::gp_cs_en::ADC_CH_SELECT_W
• gpadc::gp_ctrl::ADC_AUTOCALI_EN_R
• gpadc::gp_ctrl::ADC_AUTOCALI_EN_W
• gpadc::gp_ctrl::ADC_CALI_EN_R
• gpadc::gp_ctrl::ADC_CALI_EN_W
• gpadc::gp_ctrl::ADC_EN_R
• gpadc::gp_ctrl::ADC_EN_W
• gpadc::gp_ctrl::ADC_FIRST_DLY_R
• gpadc::gp_ctrl::ADC_FIRST_DLY_W
• gpadc::gp_ctrl::ADC_OP_BIAS_R
• gpadc::gp_ctrl::ADC_OP_BIAS_W
• gpadc::gp_ctrl::GPADC_WORK_MODE_R
• gpadc::gp_ctrl::GPADC_WORK_MODE_W
• gpadc::gp_data_intc::CH_DATA_IRQ_EN_R
• gpadc::gp_data_intc::CH_DATA_IRQ_EN_W
• gpadc::gp_data_ints::CH_DATA_PENGDING_R
• gpadc::gp_data_ints::CH_DATA_PENGDING_W
• gpadc::gp_datah_intc::CH_HIG_IRQ_EN_R
• gpadc::gp_datah_intc::CH_HIG_IRQ_EN_W
• gpadc::gp_datah_ints::CH_HIG_PENGDING_R
• gpadc::gp_datah_ints::CH_HIG_PENGDING_W
• gpadc::gp_datal_intc::CH_LOW_IRQ_EN_R
• gpadc::gp_datal_intc::CH_LOW_IRQ_EN_W
• gpadc::gp_datal_ints::CH_LOW_PENGDING_R
• gpadc::gp_datal_ints::CH_LOW_PENGDING_W
• gpadc::gp_fifo_data::GP_FIFO_DATA_R
• gpadc::gp_fifo_intc::FIFO_DATA_DRQ_EN_R
• gpadc::gp_fifo_intc::FIFO_DATA_DRQ_EN_W
• gpadc::gp_fifo_intc::FIFO_DATA_IRQ_EN_R
• gpadc::gp_fifo_intc::FIFO_DATA_IRQ_EN_W
• gpadc::gp_fifo_intc::FIFO_FLUSH_R
• gpadc::gp_fifo_intc::FIFO_FLUSH_W
• gpadc::gp_fifo_intc::FIFO_OVERRUN_IRQ_EN_R
• gpadc::gp_fifo_intc::FIFO_OVERRUN_IRQ_EN_W
• gpadc::gp_fifo_intc::FIFO_TRIG_LEVEL_R
• gpadc::gp_fifo_intc::FIFO_TRIG_LEVEL_W
• gpadc::gp_fifo_ints::FIFO_DATA_PENDING_R
• gpadc::gp_fifo_ints::FIFO_DATA_PENDING_W
• gpadc::gp_fifo_ints::FIFO_OVERRUN_PENDING_R
• gpadc::gp_fifo_ints::FIFO_OVERRUN_PENDING_W
• gpadc::gp_fifo_ints::RXA_CNT_R
• gpadc::gp_sr_con::FS_DIV_R
• gpadc::gp_sr_con::FS_DIV_W
• gpadc::gp_sr_con::TACQ_R
• gpadc::gp_sr_con::TACQ_W
• gpio::PB_CFG0
• gpio::PB_CFG1
• gpio::PB_DAT
• gpio::PB_DRV0
• gpio::PB_DRV1
• gpio::PB_EINT_CFG0
• gpio::PB_EINT_CFG1
• gpio::PB_EINT_CTL
• gpio::PB_EINT_DEB
• gpio::PB_EINT_STATUS
• gpio::PB_PULL0
• gpio::PC_CFG0
• gpio::PC_DAT
• gpio::PC_DRV0
• gpio::PC_EINT_CFG0
• gpio::PC_EINT_CTL
• gpio::PC_EINT_DEB
• gpio::PC_EINT_STATUS
• gpio::PC_PULL0
• gpio::PD_CFG0
• gpio::PD_CFG1
• gpio::PD_CFG2
• gpio::PD_DAT
• gpio::PD_DRV0
• gpio::PD_DRV1
• gpio::PD_DRV2
• gpio::PD_EINT_CFG0
• gpio::PD_EINT_CFG1
• gpio::PD_EINT_CFG2
• gpio::PD_EINT_CTL
• gpio::PD_EINT_DEB
• gpio::PD_EINT_STATUS
• gpio::PD_PULL0
• gpio::PD_PULL1
• gpio::PE_CFG0
• gpio::PE_CFG1
• gpio::PE_CFG2
• gpio::PE_DAT
• gpio::PE_DRV0
• gpio::PE_DRV1
• gpio::PE_DRV2
• gpio::PE_EINT_CFG0
• gpio::PE_EINT_CFG1
• gpio::PE_EINT_CFG2
• gpio::PE_EINT_CTL
• gpio::PE_EINT_DEB
• gpio::PE_EINT_STATUS
• gpio::PE_PULL0
• gpio::PE_PULL1
• gpio::PF_CFG0
• gpio::PF_DAT
• gpio::PF_DRV0
• gpio::PF_EINT_CFG0
• gpio::PF_EINT_CTL
• gpio::PF_EINT_DEB
• gpio::PF_EINT_STATUS
• gpio::PF_PULL0
• gpio::PG_CFG0
• gpio::PG_CFG1
• gpio::PG_CFG2
• gpio::PG_DAT
• gpio::PG_DRV0
• gpio::PG_DRV1
• gpio::PG_DRV2
• gpio::PG_EINT_CFG0
• gpio::PG_EINT_CFG1
• gpio::PG_EINT_CFG2
• gpio::PG_EINT_CTL
• gpio::PG_EINT_DEB
• gpio::PG_EINT_STATUS
• gpio::PG_PULL0
• gpio::PG_PULL1
• gpio::PIO_POW_MOD_SEL
• gpio::PIO_POW_MS_CTL
• gpio::PIO_POW_VAL
• gpio::PIO_POW_VOL_SEL_CTL
• gpio::pb_cfg0::PB0_SELECT_R
• gpio::pb_cfg0::PB0_SELECT_W
• gpio::pb_cfg0::PB1_SELECT_R
• gpio::pb_cfg0::PB1_SELECT_W
• gpio::pb_cfg0::PB2_SELECT_R
• gpio::pb_cfg0::PB2_SELECT_W
• gpio::pb_cfg0::PB3_SELECT_R
• gpio::pb_cfg0::PB3_SELECT_W
• gpio::pb_cfg0::PB4_SELECT_R
• gpio::pb_cfg0::PB4_SELECT_W
• gpio::pb_cfg0::PB5_SELECT_R
• gpio::pb_cfg0::PB5_SELECT_W
• gpio::pb_cfg0::PB6_SELECT_R
• gpio::pb_cfg0::PB6_SELECT_W
• gpio::pb_cfg0::PB7_SELECT_R
• gpio::pb_cfg0::PB7_SELECT_W
• gpio::pb_cfg1::PB10_SELECT_R
• gpio::pb_cfg1::PB10_SELECT_W
• gpio::pb_cfg1::PB11_SELECT_R
• gpio::pb_cfg1::PB11_SELECT_W
• gpio::pb_cfg1::PB12_SELECT_R
• gpio::pb_cfg1::PB12_SELECT_W
• gpio::pb_cfg1::PB8_SELECT_R
• gpio::pb_cfg1::PB8_SELECT_W
• gpio::pb_cfg1::PB9_SELECT_R
• gpio::pb_cfg1::PB9_SELECT_W
• gpio::pb_dat::PB_DAT_R
• gpio::pb_dat::PB_DAT_W
• gpio::pb_drv0::PB_DRV_R
• gpio::pb_drv0::PB_DRV_W
• gpio::pb_drv1::PB_DRV_R
• gpio::pb_drv1::PB_DRV_W
• gpio::pb_eint_cfg0::EINT_CFG_R
• gpio::pb_eint_cfg0::EINT_CFG_W
• gpio::pb_eint_cfg1::EINT_CFG_R
• gpio::pb_eint_cfg1::EINT_CFG_W
• gpio::pb_eint_ctl::EINT_CTL_R
• gpio::pb_eint_ctl::EINT_CTL_W
• gpio::pb_eint_deb::DEB_CLK_PRE_SCALE_R
• gpio::pb_eint_deb::DEB_CLK_PRE_SCALE_W
• gpio::pb_eint_deb::PIO_INT_CLK_SELECT_R
• gpio::pb_eint_deb::PIO_INT_CLK_SELECT_W
• gpio::pb_eint_status::EINT_STATUS_R
• gpio::pb_eint_status::EINT_STATUS_W
• gpio::pb_pull0::PC_PULL_R
• gpio::pb_pull0::PC_PULL_W
• gpio::pc_cfg0::PC0_SELECT_R
• gpio::pc_cfg0::PC0_SELECT_W
• gpio::pc_cfg0::PC1_SELECT_R
• gpio::pc_cfg0::PC1_SELECT_W
• gpio::pc_cfg0::PC2_SELECT_R
• gpio::pc_cfg0::PC2_SELECT_W
• gpio::pc_cfg0::PC3_SELECT_R
• gpio::pc_cfg0::PC3_SELECT_W
• gpio::pc_cfg0::PC4_SELECT_R
• gpio::pc_cfg0::PC4_SELECT_W
• gpio::pc_cfg0::PC5_SELECT_R
• gpio::pc_cfg0::PC5_SELECT_W
• gpio::pc_cfg0::PC6_SELECT_R
• gpio::pc_cfg0::PC6_SELECT_W
• gpio::pc_cfg0::PC7_SELECT_R
• gpio::pc_cfg0::PC7_SELECT_W
• gpio::pc_dat::PC_DAT_R
• gpio::pc_dat::PC_DAT_W
• gpio::pc_drv0::PC_DRV_R
• gpio::pc_drv0::PC_DRV_W
• gpio::pc_eint_cfg0::EINT_CFG_R
• gpio::pc_eint_cfg0::EINT_CFG_W
• gpio::pc_eint_ctl::EINT_CTL_R
• gpio::pc_eint_ctl::EINT_CTL_W
• gpio::pc_eint_deb::DEB_CLK_PRE_SCALE_R
• gpio::pc_eint_deb::DEB_CLK_PRE_SCALE_W
• gpio::pc_eint_deb::PIO_INT_CLK_SELECT_R
• gpio::pc_eint_deb::PIO_INT_CLK_SELECT_W
• gpio::pc_eint_status::EINT_STATUS_R
• gpio::pc_eint_status::EINT_STATUS_W
• gpio::pc_pull0::PC_PULL_R
• gpio::pc_pull0::PC_PULL_W
• gpio::pd_cfg0::PD0_SELECT_R
• gpio::pd_cfg0::PD0_SELECT_W
• gpio::pd_cfg0::PD1_SELECT_R
• gpio::pd_cfg0::PD1_SELECT_W
• gpio::pd_cfg0::PD2_SELECT_R
• gpio::pd_cfg0::PD2_SELECT_W
• gpio::pd_cfg0::PD3_SELECT_R
• gpio::pd_cfg0::PD3_SELECT_W
• gpio::pd_cfg0::PD4_SELECT_R
• gpio::pd_cfg0::PD4_SELECT_W
• gpio::pd_cfg0::PD5_SELECT_R
• gpio::pd_cfg0::PD5_SELECT_W
• gpio::pd_cfg0::PD6_SELECT_R
• gpio::pd_cfg0::PD6_SELECT_W
• gpio::pd_cfg0::PD7_SELECT_R
• gpio::pd_cfg0::PD7_SELECT_W
• gpio::pd_cfg1::PD10_SELECT_R
• gpio::pd_cfg1::PD10_SELECT_W
• gpio::pd_cfg1::PD11_SELECT_R
• gpio::pd_cfg1::PD11_SELECT_W
• gpio::pd_cfg1::PD12_SELECT_R
• gpio::pd_cfg1::PD12_SELECT_W
• gpio::pd_cfg1::PD13_SELECT_R
• gpio::pd_cfg1::PD13_SELECT_W
• gpio::pd_cfg1::PD14_SELECT_R
• gpio::pd_cfg1::PD14_SELECT_W
• gpio::pd_cfg1::PD15_SELECT_R
• gpio::pd_cfg1::PD15_SELECT_W
• gpio::pd_cfg1::PD8_SELECT_R
• gpio::pd_cfg1::PD8_SELECT_W
• gpio::pd_cfg1::PD9_SELECT_R
• gpio::pd_cfg1::PD9_SELECT_W
• gpio::pd_cfg2::PD16_SELECT_R
• gpio::pd_cfg2::PD16_SELECT_W
• gpio::pd_cfg2::PD17_SELECT_R
• gpio::pd_cfg2::PD17_SELECT_W
• gpio::pd_cfg2::PD18_SELECT_R
• gpio::pd_cfg2::PD18_SELECT_W
• gpio::pd_cfg2::PD19_SELECT_R
• gpio::pd_cfg2::PD19_SELECT_W
• gpio::pd_cfg2::PD20_SELECT_R
• gpio::pd_cfg2::PD20_SELECT_W
• gpio::pd_cfg2::PD21_SELECT_R
• gpio::pd_cfg2::PD21_SELECT_W
• gpio::pd_cfg2::PD22_SELECT_R
• gpio::pd_cfg2::PD22_SELECT_W
• gpio::pd_dat::PD_DAT_R
• gpio::pd_dat::PD_DAT_W
• gpio::pd_drv0::PD_DRV_R
• gpio::pd_drv0::PD_DRV_W
• gpio::pd_drv1::PD_DRV_R
• gpio::pd_drv1::PD_DRV_W
• gpio::pd_drv2::PD_DRV_R
• gpio::pd_drv2::PD_DRV_W
• gpio::pd_eint_cfg0::EINT_CFG_R
• gpio::pd_eint_cfg0::EINT_CFG_W
• gpio::pd_eint_cfg1::EINT_CFG_R
• gpio::pd_eint_cfg1::EINT_CFG_W
• gpio::pd_eint_cfg2::EINT_CFG_R
• gpio::pd_eint_cfg2::EINT_CFG_W
• gpio::pd_eint_ctl::EINT_CTL_R
• gpio::pd_eint_ctl::EINT_CTL_W
• gpio::pd_eint_deb::DEB_CLK_PRE_SCALE_R
• gpio::pd_eint_deb::DEB_CLK_PRE_SCALE_W
• gpio::pd_eint_deb::PIO_INT_CLK_SELECT_R
• gpio::pd_eint_deb::PIO_INT_CLK_SELECT_W
• gpio::pd_eint_status::EINT_STATUS_R
• gpio::pd_eint_status::EINT_STATUS_W
• gpio::pd_pull0::PD_PULL_R
• gpio::pd_pull0::PD_PULL_W
• gpio::pd_pull1::PD_PULL_R
• gpio::pd_pull1::PD_PULL_W
• gpio::pe_cfg0::PE0_SELECT_R
• gpio::pe_cfg0::PE0_SELECT_W
• gpio::pe_cfg0::PE1_SELECT_R
• gpio::pe_cfg0::PE1_SELECT_W
• gpio::pe_cfg0::PE2_SELECT_R
• gpio::pe_cfg0::PE2_SELECT_W
• gpio::pe_cfg0::PE3_SELECT_R
• gpio::pe_cfg0::PE3_SELECT_W
• gpio::pe_cfg0::PE4_SELECT_R
• gpio::pe_cfg0::PE4_SELECT_W
• gpio::pe_cfg0::PE5_SELECT_R
• gpio::pe_cfg0::PE5_SELECT_W
• gpio::pe_cfg0::PE6_SELECT_R
• gpio::pe_cfg0::PE6_SELECT_W
• gpio::pe_cfg0::PE7_SELECT_R
• gpio::pe_cfg0::PE7_SELECT_W
• gpio::pe_cfg1::PE10_SELECT_R
• gpio::pe_cfg1::PE10_SELECT_W
• gpio::pe_cfg1::PE11_SELECT_R
• gpio::pe_cfg1::PE11_SELECT_W
• gpio::pe_cfg1::PE12_SELECT_R
• gpio::pe_cfg1::PE12_SELECT_W
• gpio::pe_cfg1::PE13_SELECT_R
• gpio::pe_cfg1::PE13_SELECT_W
• gpio::pe_cfg1::PE14_SELECT_R
• gpio::pe_cfg1::PE14_SELECT_W
• gpio::pe_cfg1::PE15_SELECT_R
• gpio::pe_cfg1::PE15_SELECT_W
• gpio::pe_cfg1::PE8_SELECT_R
• gpio::pe_cfg1::PE8_SELECT_W
• gpio::pe_cfg1::PE9_SELECT_R
• gpio::pe_cfg1::PE9_SELECT_W
• gpio::pe_cfg2::PE16_SELECT_R
• gpio::pe_cfg2::PE16_SELECT_W
• gpio::pe_cfg2::PE17_SELECT_R
• gpio::pe_cfg2::PE17_SELECT_W
• gpio::pe_dat::PE_DAT_R
• gpio::pe_dat::PE_DAT_W
• gpio::pe_drv0::PE_DRV_R
• gpio::pe_drv0::PE_DRV_W
• gpio::pe_drv1::PE_DRV_R
• gpio::pe_drv1::PE_DRV_W
• gpio::pe_drv2::PE_DRV_R
• gpio::pe_drv2::PE_DRV_W
• gpio::pe_eint_cfg0::EINT_CFG_R
• gpio::pe_eint_cfg0::EINT_CFG_W
• gpio::pe_eint_cfg1::EINT_CFG_R
• gpio::pe_eint_cfg1::EINT_CFG_W
• gpio::pe_eint_cfg2::EINT_CFG_R
• gpio::pe_eint_cfg2::EINT_CFG_W
• gpio::pe_eint_ctl::EINT_CTL_R
• gpio::pe_eint_ctl::EINT_CTL_W
• gpio::pe_eint_deb::DEB_CLK_PRE_SCALE_R
• gpio::pe_eint_deb::DEB_CLK_PRE_SCALE_W
• gpio::pe_eint_deb::PIO_INT_CLK_SELECT_R
• gpio::pe_eint_deb::PIO_INT_CLK_SELECT_W
• gpio::pe_eint_status::EINT_STATUS_R
• gpio::pe_eint_status::EINT_STATUS_W
• gpio::pe_pull0::PE_PULL_R
• gpio::pe_pull0::PE_PULL_W
• gpio::pe_pull1::PE_PULL_R
• gpio::pe_pull1::PE_PULL_W
• gpio::pf_cfg0::PF0_SELECT_R
• gpio::pf_cfg0::PF0_SELECT_W
• gpio::pf_cfg0::PF1_SELECT_R
• gpio::pf_cfg0::PF1_SELECT_W
• gpio::pf_cfg0::PF2_SELECT_R
• gpio::pf_cfg0::PF2_SELECT_W
• gpio::pf_cfg0::PF3_SELECT_R
• gpio::pf_cfg0::PF3_SELECT_W
• gpio::pf_cfg0::PF4_SELECT_R
• gpio::pf_cfg0::PF4_SELECT_W
• gpio::pf_cfg0::PF5_SELECT_R
• gpio::pf_cfg0::PF5_SELECT_W
• gpio::pf_cfg0::PF6_SELECT_R
• gpio::pf_cfg0::PF6_SELECT_W
• gpio::pf_dat::PF_DAT_R
• gpio::pf_dat::PF_DAT_W
• gpio::pf_drv0::PF_DRV_R
• gpio::pf_drv0::PF_DRV_W
• gpio::pf_eint_cfg0::EINT_CFG_R
• gpio::pf_eint_cfg0::EINT_CFG_W
• gpio::pf_eint_ctl::EINT_CTL_R
• gpio::pf_eint_ctl::EINT_CTL_W
• gpio::pf_eint_deb::DEB_CLK_PRE_SCALE_R
• gpio::pf_eint_deb::DEB_CLK_PRE_SCALE_W
• gpio::pf_eint_deb::PIO_INT_CLK_SELECT_R
• gpio::pf_eint_deb::PIO_INT_CLK_SELECT_W
• gpio::pf_eint_status::EINT_STATUS_R
• gpio::pf_eint_status::EINT_STATUS_W
• gpio::pf_pull0::PF_PULL_R
• gpio::pf_pull0::PF_PULL_W
• gpio::pg_cfg0::PG0_SELECT_R
• gpio::pg_cfg0::PG0_SELECT_W
• gpio::pg_cfg0::PG1_SELECT_R
• gpio::pg_cfg0::PG1_SELECT_W
• gpio::pg_cfg0::PG2_SELECT_R
• gpio::pg_cfg0::PG2_SELECT_W
• gpio::pg_cfg0::PG3_SELECT_R
• gpio::pg_cfg0::PG3_SELECT_W
• gpio::pg_cfg0::PG4_SELECT_R
• gpio::pg_cfg0::PG4_SELECT_W
• gpio::pg_cfg0::PG5_SELECT_R
• gpio::pg_cfg0::PG5_SELECT_W
• gpio::pg_cfg0::PG6_SELECT_R
• gpio::pg_cfg0::PG6_SELECT_W
• gpio::pg_cfg0::PG7_SELECT_R
• gpio::pg_cfg0::PG7_SELECT_W
• gpio::pg_cfg1::PG10_SELECT_R
• gpio::pg_cfg1::PG10_SELECT_W
• gpio::pg_cfg1::PG11_SELECT_R
• gpio::pg_cfg1::PG11_SELECT_W
• gpio::pg_cfg1::PG12_SELECT_R
• gpio::pg_cfg1::PG12_SELECT_W
• gpio::pg_cfg1::PG13_SELECT_R
• gpio::pg_cfg1::PG13_SELECT_W
• gpio::pg_cfg1::PG14_SELECT_R
• gpio::pg_cfg1::PG14_SELECT_W
• gpio::pg_cfg1::PG15_SELECT_R
• gpio::pg_cfg1::PG15_SELECT_W
• gpio::pg_cfg1::PG8_SELECT_R
• gpio::pg_cfg1::PG8_SELECT_W
• gpio::pg_cfg1::PG9_SELECT_R
• gpio::pg_cfg1::PG9_SELECT_W
• gpio::pg_cfg2::PG16_SELECT_R
• gpio::pg_cfg2::PG16_SELECT_W
• gpio::pg_cfg2::PG17_SELECT_R
• gpio::pg_cfg2::PG17_SELECT_W
• gpio::pg_cfg2::PG18_SELECT_R
• gpio::pg_cfg2::PG18_SELECT_W
• gpio::pg_dat::PG_DAT_R
• gpio::pg_dat::PG_DAT_W
• gpio::pg_drv0::PG_DRV_R
• gpio::pg_drv0::PG_DRV_W
• gpio::pg_drv1::PG_DRV_R
• gpio::pg_drv1::PG_DRV_W
• gpio::pg_drv2::PG_DRV_R
• gpio::pg_drv2::PG_DRV_W
• gpio::pg_eint_cfg0::EINT_CFG_R
• gpio::pg_eint_cfg0::EINT_CFG_W
• gpio::pg_eint_cfg1::EINT_CFG_R
• gpio::pg_eint_cfg1::EINT_CFG_W
• gpio::pg_eint_cfg2::EINT_CFG_R
• gpio::pg_eint_cfg2::EINT_CFG_W
• gpio::pg_eint_ctl::EINT_CTL_R
• gpio::pg_eint_ctl::EINT_CTL_W
• gpio::pg_eint_deb::DEB_CLK_PRE_SCALE_R
• gpio::pg_eint_deb::DEB_CLK_PRE_SCALE_W
• gpio::pg_eint_deb::PIO_INT_CLK_SELECT_R
• gpio::pg_eint_deb::PIO_INT_CLK_SELECT_W
• gpio::pg_eint_status::EINT_STATUS_R
• gpio::pg_eint_status::EINT_STATUS_W
• gpio::pg_pull0::PG_PULL_R
• gpio::pg_pull0::PG_PULL_W
• gpio::pg_pull1::PG_PULL_R
• gpio::pg_pull1::PG_PULL_W
• gpio::pio_pow_mod_sel::P_PWR_MOD_SEL_R
• gpio::pio_pow_mod_sel::P_PWR_MOD_SEL_W
• gpio::pio_pow_mod_sel::VCC_IO_PWR_MOD_SEL_R
• gpio::pio_pow_mod_sel::VCC_IO_PWR_MOD_SEL_W
• gpio::pio_pow_ms_ctl::VCCIO_WS_VOL_MOD_SEL_R
• gpio::pio_pow_ms_ctl::VCCIO_WS_VOL_MOD_SEL_W
• gpio::pio_pow_ms_ctl::VCC_P_WS_VOL_MOD_SEL_R
• gpio::pio_pow_ms_ctl::VCC_P_WS_VOL_MOD_SEL_W
• gpio::pio_pow_val::P_PWR_VAL_R
• gpio::pio_pow_val::VCCIO_PWS_VAL_R
• gpio::pio_pow_vol_sel_ctl::VCC_PF_PWR_VOL_SEL_R
• gpio::pio_pow_vol_sel_ctl::VCC_PF_PWR_VOL_SEL_W
• hstimer::HS_TMR_CTRL
• hstimer::HS_TMR_CURNT_HI
• hstimer::HS_TMR_CURNT_LO
• hstimer::HS_TMR_INTV_HI
• hstimer::HS_TMR_INTV_LO
• hstimer::HS_TMR_IRQ_EN
• hstimer::HS_TMR_IRQ_STAS
• hstimer::hs_tmr_ctrl::HS_TMR_CLK_R
• hstimer::hs_tmr_ctrl::HS_TMR_CLK_W
• hstimer::hs_tmr_ctrl::HS_TMR_EN_R
• hstimer::hs_tmr_ctrl::HS_TMR_EN_W
• hstimer::hs_tmr_ctrl::HS_TMR_MODE_R
• hstimer::hs_tmr_ctrl::HS_TMR_MODE_W
• hstimer::hs_tmr_ctrl::HS_TMR_RELOAD_R
• hstimer::hs_tmr_ctrl::HS_TMR_RELOAD_W
• hstimer::hs_tmr_ctrl::HS_TMR_TEST_R
• hstimer::hs_tmr_ctrl::HS_TMR_TEST_W
• hstimer::hs_tmr_curnt_hi::HS_TMR_CUR_VALUE_HI_R
• hstimer::hs_tmr_curnt_hi::HS_TMR_CUR_VALUE_HI_W
• hstimer::hs_tmr_intv_hi::HS_TMR_INTV_VALUE_HI_R
• hstimer::hs_tmr_intv_hi::HS_TMR_INTV_VALUE_HI_W
• hstimer::hs_tmr_irq_en::HS_TMR_INT_EN_R
• hstimer::hs_tmr_irq_en::HS_TMR_INT_EN_W
• hstimer::hs_tmr_irq_stas::HS_TMR_IRQ_PEND_R
• hstimer::hs_tmr_irq_stas::HS_TMR_IRQ_PEND_W
• i2s_pcm::ASRCCFG
• i2s_pcm::ASRCFIFOSTAT
• i2s_pcm::ASRCMANCFG
• i2s_pcm::ASRCMBISTCFG
• i2s_pcm::ASRCMBISTSTAT
• i2s_pcm::ASRCRATIOSTAT
• i2s_pcm::FSINEXTCFG
• i2s_pcm::FSOUTCFG
• i2s_pcm::I2S_PCM_CHCFG
• i2s_pcm::I2S_PCM_CLKD
• i2s_pcm::I2S_PCM_CTL
• i2s_pcm::I2S_PCM_FCTL
• i2s_pcm::I2S_PCM_FMT0
• i2s_pcm::I2S_PCM_FMT1
• i2s_pcm::I2S_PCM_FSTA
• i2s_pcm::I2S_PCM_INT
• i2s_pcm::I2S_PCM_ISTA
• i2s_pcm::I2S_PCM_RXCHMAP0
• i2s_pcm::I2S_PCM_RXCHMAP1
• i2s_pcm::I2S_PCM_RXCHMAP2
• i2s_pcm::I2S_PCM_RXCHMAP3
• i2s_pcm::I2S_PCM_RXCHSEL
• i2s_pcm::I2S_PCM_RXCNT
• i2s_pcm::I2S_PCM_RXFIFO
• i2s_pcm::I2S_PCM_TX0CHMAP0
• i2s_pcm::I2S_PCM_TX0CHMAP1
• i2s_pcm::I2S_PCM_TX0CHSEL
• i2s_pcm::I2S_PCM_TX1CHMAP0
• i2s_pcm::I2S_PCM_TX1CHMAP1
• i2s_pcm::I2S_PCM_TX1CHSEL
• i2s_pcm::I2S_PCM_TX2CHMAP0
• i2s_pcm::I2S_PCM_TX2CHMAP1
• i2s_pcm::I2S_PCM_TX2CHSEL
• i2s_pcm::I2S_PCM_TX3CHMAP0
• i2s_pcm::I2S_PCM_TX3CHMAP1
• i2s_pcm::I2S_PCM_TX3CHSEL
• i2s_pcm::I2S_PCM_TXCNT
• i2s_pcm::I2S_PCM_TXFIFO
• i2s_pcm::MCLKCFG
• iommu::IOMMU_4KB_BDY_PRT_CTRL_REG
• iommu::IOMMU_AUTO_GATING_REG
• iommu::IOMMU_BYPASS_REG
• iommu::IOMMU_DM_AUT_CTRL0_REG
• iommu::IOMMU_DM_AUT_CTRL1_REG
• iommu::IOMMU_DM_AUT_CTRL2_REG
• iommu::IOMMU_DM_AUT_CTRL3_REG
• iommu::IOMMU_DM_AUT_CTRL4_REG
• iommu::IOMMU_DM_AUT_CTRL5_REG
• iommu::IOMMU_DM_AUT_CTRL6_REG
• iommu::IOMMU_DM_AUT_CTRL7_REG
• iommu::IOMMU_DM_AUT_OVWT_REG
• iommu::IOMMU_ENABLE_REG
• iommu::IOMMU_INT_CLR_REG
• iommu::IOMMU_INT_ENABLE_REG
• iommu::IOMMU_INT_ERR_ADDR0_REG
• iommu::IOMMU_INT_ERR_ADDR1_REG
• iommu::IOMMU_INT_ERR_ADDR2_REG
• iommu::IOMMU_INT_ERR_ADDR3_REG
• iommu::IOMMU_INT_ERR_ADDR4_REG
• iommu::IOMMU_INT_ERR_ADDR5_REG
• iommu::IOMMU_INT_ERR_ADDR6_REG
• iommu::IOMMU_INT_ERR_ADDR7_REG
• iommu::IOMMU_INT_ERR_ADDR8_REG
• iommu::IOMMU_INT_ERR_DATA0_REG
• iommu::IOMMU_INT_ERR_DATA1_REG
• iommu::IOMMU_INT_ERR_DATA2_REG
• iommu::IOMMU_INT_ERR_DATA3_REG
• iommu::IOMMU_INT_ERR_DATA4_REG
• iommu::IOMMU_INT_ERR_DATA5_REG
• iommu::IOMMU_INT_ERR_DATA6_REG
• iommu::IOMMU_INT_ERR_DATA7_REG
• iommu::IOMMU_INT_ERR_DATA8_REG
• iommu::IOMMU_INT_STA_REG
• iommu::IOMMU_L1PG_INT_REG
• iommu::IOMMU_L2PG_INT_REG
• iommu::IOMMU_OOO_CTRL_REG
• iommu::IOMMU_PC_IVLD_ADDR_REG
• iommu::IOMMU_PC_IVLD_ENABLE_REG
• iommu::IOMMU_PC_IVLD_END_ADDR_REG
• iommu::IOMMU_PC_IVLD_MODE_SEL_REG
• iommu::IOMMU_PC_IVLD_STA_ADDR_REG
• iommu::IOMMU_PMU_ACCESS_HIGH0_REG
• iommu::IOMMU_PMU_ACCESS_HIGH1_REG
• iommu::IOMMU_PMU_ACCESS_HIGH2_REG
• iommu::IOMMU_PMU_ACCESS_HIGH3_REG
• iommu::IOMMU_PMU_ACCESS_HIGH4_REG
• iommu::IOMMU_PMU_ACCESS_HIGH5_REG
• iommu::IOMMU_PMU_ACCESS_HIGH6_REG
• iommu::IOMMU_PMU_ACCESS_HIGH7_REG
• iommu::IOMMU_PMU_ACCESS_HIGH8_REG
• iommu::IOMMU_PMU_ACCESS_LOW0_REG
• iommu::IOMMU_PMU_ACCESS_LOW1_REG
• iommu::IOMMU_PMU_ACCESS_LOW2_REG
• iommu::IOMMU_PMU_ACCESS_LOW3_REG
• iommu::IOMMU_PMU_ACCESS_LOW4_REG
• iommu::IOMMU_PMU_ACCESS_LOW5_REG
• iommu::IOMMU_PMU_ACCESS_LOW6_REG
• iommu::IOMMU_PMU_ACCESS_LOW7_REG
• iommu::IOMMU_PMU_ACCESS_LOW8_REG
• iommu::IOMMU_PMU_CLR_REG
• iommu::IOMMU_PMU_ENABLE_REG
• iommu::IOMMU_PMU_HIT_HIGH0_REG
• iommu::IOMMU_PMU_HIT_HIGH1_REG
• iommu::IOMMU_PMU_HIT_HIGH2_REG
• iommu::IOMMU_PMU_HIT_HIGH3_REG
• iommu::IOMMU_PMU_HIT_HIGH4_REG
• iommu::IOMMU_PMU_HIT_HIGH5_REG
• iommu::IOMMU_PMU_HIT_HIGH6_REG
• iommu::IOMMU_PMU_HIT_HIGH7_REG
• iommu::IOMMU_PMU_HIT_HIGH8_REG
• iommu::IOMMU_PMU_HIT_LOW0_REG
• iommu::IOMMU_PMU_HIT_LOW1_REG
• iommu::IOMMU_PMU_HIT_LOW2_REG
• iommu::IOMMU_PMU_HIT_LOW3_REG
• iommu::IOMMU_PMU_HIT_LOW4_REG
• iommu::IOMMU_PMU_HIT_LOW5_REG
• iommu::IOMMU_PMU_HIT_LOW6_REG
• iommu::IOMMU_PMU_HIT_LOW7_REG
• iommu::IOMMU_PMU_HIT_LOW8_REG
• iommu::IOMMU_PMU_ML0_REG
• iommu::IOMMU_PMU_ML1_REG
• iommu::IOMMU_PMU_ML2_REG
• iommu::IOMMU_PMU_ML3_REG
• iommu::IOMMU_PMU_ML4_REG
• iommu::IOMMU_PMU_ML5_REG
• iommu::IOMMU_PMU_ML6_REG
• iommu::IOMMU_PMU_TL_HIGH0_REG
• iommu::IOMMU_PMU_TL_HIGH1_REG
• iommu::IOMMU_PMU_TL_HIGH2_REG
• iommu::IOMMU_PMU_TL_HIGH3_REG
• iommu::IOMMU_PMU_TL_HIGH4_REG
• iommu::IOMMU_PMU_TL_HIGH5_REG
• iommu::IOMMU_PMU_TL_HIGH6_REG
• iommu::IOMMU_PMU_TL_LOW0_REG
• iommu::IOMMU_PMU_TL_LOW1_REG
• iommu::IOMMU_PMU_TL_LOW2_REG
• iommu::IOMMU_PMU_TL_LOW3_REG
• iommu::IOMMU_PMU_TL_LOW4_REG
• iommu::IOMMU_PMU_TL_LOW5_REG
• iommu::IOMMU_PMU_TL_LOW6_REG
• iommu::IOMMU_RESET_REG
• iommu::IOMMU_TLB_ENABLE_REG
• iommu::IOMMU_TLB_FLUSH_ENABLE_REG
• iommu::IOMMU_TLB_IVLD_ADDR_MASK_REG
• iommu::IOMMU_TLB_IVLD_ADDR_REG
• iommu::IOMMU_TLB_IVLD_ENABLE_REG
• iommu::IOMMU_TLB_IVLD_END_ADDR_REG
• iommu::IOMMU_TLB_IVLD_MODE_SEL_REG
• iommu::IOMMU_TLB_IVLD_STA_ADDR_REG
• iommu::IOMMU_TLB_PREFETCH_REG
• iommu::IOMMU_TTB_REG
• iommu::IOMMU_VA_CONFIG_REG
• iommu::IOMMU_VA_DATA_REG
• iommu::IOMMU_VA_REG
• iommu::IOMMU_WBUF_CTRL_REG
• ledc::LEDC_CTRL
• ledc::LEDC_DATA
• ledc::LEDC_DATA_FINISH_CNT
• ledc::LEDC_DMA_CTRL
• ledc::LEDC_FIFO_DATA
• ledc::LEDC_INT_CTRL
• ledc::LEDC_INT_STS
• ledc::LEDC_WAIT_TIME0_CTRL
• ledc::LEDC_WAIT_TIME1_CTRL
• ledc::LED_RESET_TIMING_CTRL
• ledc::LED_T01_TIMING_CTRL
• ledc::led_reset_timing_ctrl::LED_NUM_R
• ledc::led_reset_timing_ctrl::LED_NUM_W
• ledc::led_reset_timing_ctrl::TR_TIME_R
• ledc::led_reset_timing_ctrl::TR_TIME_W
• ledc::led_t01_timing_ctrl::T0H_TIME_R
• ledc::led_t01_timing_ctrl::T0H_TIME_W
• ledc::led_t01_timing_ctrl::T0L_TIME_R
• ledc::led_t01_timing_ctrl::T0L_TIME_W
• ledc::led_t01_timing_ctrl::T1H_TIME_R
• ledc::led_t01_timing_ctrl::T1H_TIME_W
• ledc::led_t01_timing_ctrl::T1L_TIME_R
• ledc::led_t01_timing_ctrl::T1L_TIME_W
• ledc::ledc_ctrl::LEDC_EN_R
• ledc::ledc_ctrl::LEDC_EN_W
• ledc::ledc_ctrl::LEDC_SOFT_RESET_R
• ledc::ledc_ctrl::LEDC_SOFT_RESET_W
• ledc::ledc_ctrl::LED_MSB__R
• ledc::ledc_ctrl::LED_MSB__W
• ledc::ledc_ctrl::LED_RGB_MODE_R
• ledc::ledc_ctrl::LED_RGB_MODE_W
• ledc::ledc_ctrl::RESET_LED_EN_R
• ledc::ledc_ctrl::RESET_LED_EN_W
• ledc::ledc_ctrl::TOTAL_DATA_LENGTH_R
• ledc::ledc_ctrl::TOTAL_DATA_LENGTH_W
• ledc::ledc_data_finish_cnt::LED_DATA_FINISH_CNT_R
• ledc::ledc_data_finish_cnt::LED_WAIT_DATA_TIME_R
• ledc::ledc_data_finish_cnt::LED_WAIT_DATA_TIME_W
• ledc::ledc_dma_ctrl::LEDC_DMA_EN_R
• ledc::ledc_dma_ctrl::LEDC_DMA_EN_W
• ledc::ledc_dma_ctrl::LEDC_FIFO_TRIG_LEVEL_R
• ledc::ledc_dma_ctrl::LEDC_FIFO_TRIG_LEVEL_W
• ledc::ledc_int_ctrl::FIFO_CPUREQ_INT_EN_R
• ledc::ledc_int_ctrl::FIFO_CPUREQ_INT_EN_W
• ledc::ledc_int_ctrl::FIFO_OVERFLOW_INT_EN_R
• ledc::ledc_int_ctrl::FIFO_OVERFLOW_INT_EN_W
• ledc::ledc_int_ctrl::GLOBAL_INT_EN_R
• ledc::ledc_int_ctrl::GLOBAL_INT_EN_W
• ledc::ledc_int_ctrl::LED_TRANS_FINISH_INT_EN_R
• ledc::ledc_int_ctrl::LED_TRANS_FINISH_INT_EN_W
• ledc::ledc_int_ctrl::WAITDATA_TIMEOUT_INT_EN_R
• ledc::ledc_int_ctrl::WAITDATA_TIMEOUT_INT_EN_W
• ledc::ledc_int_sts::FIFO_CPUREQ_INT_R
• ledc::ledc_int_sts::FIFO_CPUREQ_INT_W
• ledc::ledc_int_sts::FIFO_EMPTY_R
• ledc::ledc_int_sts::FIFO_FULL_R
• ledc::ledc_int_sts::FIFO_OVERFLOW_INT_R
• ledc::ledc_int_sts::FIFO_OVERFLOW_INT_W
• ledc::ledc_int_sts::FIFO_WLW_R
• ledc::ledc_int_sts::LEC_TRANS_FINISH_INT_R
• ledc::ledc_int_sts::LEC_TRANS_FINISH_INT_W
• ledc::ledc_int_sts::WAITDATA_TIMEOUT_INT_R
• ledc::ledc_int_sts::WAITDATA_TIMEOUT_INT_W
• ledc::ledc_wait_time0_ctrl::TOTAL_WAIT_TIME0_R
• ledc::ledc_wait_time0_ctrl::TOTAL_WAIT_TIME0_W
• ledc::ledc_wait_time0_ctrl::WAIT_TIM0_EN_R
• ledc::ledc_wait_time0_ctrl::WAIT_TIM0_EN_W
• ledc::ledc_wait_time1_ctrl::TOTAL_WAIT_TIME1_R
• ledc::ledc_wait_time1_ctrl::TOTAL_WAIT_TIME1_W
• ledc::ledc_wait_time1_ctrl::WAIT_TIM1_EN_R
• ledc::ledc_wait_time1_ctrl::WAIT_TIM1_EN_W
• lradc::LRADC_CTRL
• lradc::LRADC_DATA
• lradc::LRADC_INTC
• lradc::LRADC_INTS
• lradc::lradc_ctrl::CONTINUE_TIME_SELECT_R
• lradc::lradc_ctrl::CONTINUE_TIME_SELECT_W
• lradc::lradc_ctrl::FIRST_CONVERT_DLY_R
• lradc::lradc_ctrl::FIRST_CONVERT_DLY_W
• lradc::lradc_ctrl::KEY_MODE_SELECT_R
• lradc::lradc_ctrl::KEY_MODE_SELECT_W
• lradc::lradc_ctrl::LEVELA_B_CNT_R
• lradc::lradc_ctrl::LEVELA_B_CNT_W
• lradc::lradc_ctrl::LEVELB_VOL_R
• lradc::lradc_ctrl::LEVELB_VOL_W
• lradc::lradc_ctrl::LRADC_CHANNEL_EN_R
• lradc::lradc_ctrl::LRADC_CHANNEL_EN_W
• lradc::lradc_ctrl::LRADC_EN_R
• lradc::lradc_ctrl::LRADC_EN_W
• lradc::lradc_ctrl::LRADC_HOLD_KEY_EN_R
• lradc::lradc_ctrl::LRADC_HOLD_KEY_EN_W
• lradc::lradc_ctrl::LRADC_SAMPLE_RATE_R
• lradc::lradc_ctrl::LRADC_SAMPLE_RATE_W
• lradc::lradc_data::LRADC_DATA_R
• lradc::lradc_intc::ADC0_ALRDY_HOLD_IRQ_EN_R
• lradc::lradc_intc::ADC0_ALRDY_HOLD_IRQ_EN_W
• lradc::lradc_intc::ADC0_DATA_IRQ_EN_R
• lradc::lradc_intc::ADC0_DATA_IRQ_EN_W
• lradc::lradc_intc::ADC0_HOLD_IRQ_EN_R
• lradc::lradc_intc::ADC0_HOLD_IRQ_EN_W
• lradc::lradc_intc::ADC0_KEYDOWN_IRQ_EN_R
• lradc::lradc_intc::ADC0_KEYDOWN_IRQ_EN_W
• lradc::lradc_intc::ADC0_KEYUP_IRQ_EN_R
• lradc::lradc_intc::ADC0_KEYUP_IRQ_EN_W
• lradc::lradc_ints::ADC0_ALRDY_HOLD_PENDING_R
• lradc::lradc_ints::ADC0_ALRDY_HOLD_PENDING_W
• lradc::lradc_ints::ADC0_DATA_PENDING_R
• lradc::lradc_ints::ADC0_DATA_PENDING_W
• lradc::lradc_ints::ADC0_HOLD_PENDING_R
• lradc::lradc_ints::ADC0_HOLD_PENDING_W
• lradc::lradc_ints::ADC0_KEYDOWN_PENDING_R
• lradc::lradc_ints::ADC0_KEYDOWN_PENDING_W
• lradc::lradc_ints::ADC0_KEYUP_PENDING_R
• lradc::lradc_ints::ADC0_KEYUP_PENDING_W
• owa::OWA_EXP_CTL
• owa::OWA_EXP_DBG_0
• owa::OWA_EXP_DBG_1
• owa::OWA_EXP_INFO_0
• owa::OWA_EXP_INFO_1
• owa::OWA_EXP_ISTA
• owa::OWA_FCTL
• owa::OWA_FSTA
• owa::OWA_GEN_CTL
• owa::OWA_INT
• owa::OWA_ISTA
• owa::OWA_RXCHSTA0
• owa::OWA_RXCHSTA1
• owa::OWA_RXFIFO
• owa::OWA_RX_CFIG
• owa::OWA_RX_CNT
• owa::OWA_TX_CFIG
• owa::OWA_TX_CHSTA0
• owa::OWA_TX_CHSTA1
• owa::OWA_TX_CNT
• owa::OWA_TX_FIFO
• plic::CTRL
• plic::IP
• plic::MCLAIM
• plic::MIE
• plic::MTH
• plic::PRIO
• plic::SCLAIM
• plic::SIE
• plic::STH
• plic::ctrl::CTRL_R
• plic::ctrl::CTRL_W
• plic::mclaim::MCLAIM_R
• plic::mclaim::MCLAIM_W
• plic::mth::PRIORITY_R
• plic::mth::PRIORITY_W
• plic::prio::PRIORITY_R
• plic::prio::PRIORITY_W
• plic::sclaim::SCLAIM_R
• plic::sclaim::SCLAIM_W
• plic::sth::PRIORITY_R
• plic::sth::PRIORITY_W
• pwm::CCR
• pwm::CER
• pwm::CFLR
• pwm::CIER
• pwm::CISR
• pwm::CRLR
• pwm::PCCR01
• pwm::PCCR23
• pwm::PCCR45
• pwm::PCCR67
• pwm::PCGR
• pwm::PCNTR
• pwm::PCR
• pwm::PDZCR01
• pwm::PDZCR23
• pwm::PDZCR45
• pwm::PDZCR67
• pwm::PER
• pwm::PGR
• pwm::PIER
• pwm::PISR
• pwm::PPCNTR
• pwm::PPR
• pwm::ccr::CAPINV_R
• pwm::ccr::CAPINV_W
• pwm::ccr::CFLF_R
• pwm::ccr::CFLF_W
• pwm::ccr::CFTE_R
• pwm::ccr::CFTE_W
• pwm::ccr::CRLF_R
• pwm::ccr::CRLF_W
• pwm::ccr::CRTE_R
• pwm::ccr::CRTE_W
• pwm::cer::CAP_EN_R
• pwm::cer::CAP_EN_W
• pwm::cflr::CFLR_R
• pwm::cier::CFIE_R
• pwm::cier::CFIE_W
• pwm::cier::CRIE_R
• pwm::cier::CRIE_W
• pwm::cisr::CFIS_R
• pwm::cisr::CFIS_W
• pwm::cisr::CRIS_R
• pwm::cisr::CRIS_W
• pwm::crlr::CRLR_R
• pwm::pccr01::PWM01_CLK_DIV_M_R
• pwm::pccr01::PWM01_CLK_DIV_M_W
• pwm::pccr01::PWM01_CLK_SRC_R
• pwm::pccr01::PWM01_CLK_SRC_W
• pwm::pccr23::PWM23_CLK_DIV_M_R
• pwm::pccr23::PWM23_CLK_DIV_M_W
• pwm::pccr23::PWM23_CLK_SRC_SEL_R
• pwm::pccr23::PWM23_CLK_SRC_SEL_W
• pwm::pccr45::PWM45_CLK_DIV_M_R
• pwm::pccr45::PWM45_CLK_DIV_M_W
• pwm::pccr45::PWM45_CLK_SRC_SEL_R
• pwm::pccr45::PWM45_CLK_SRC_SEL_W
• pwm::pccr67::PWM67_CLK_DIV_M_R
• pwm::pccr67::PWM67_CLK_DIV_M_W
• pwm::pccr67::PWM67_CLK_SRC_SEL_R
• pwm::pccr67::PWM67_CLK_SRC_SEL_W
• pwm::pcgr::PWM_CLK_BYPASS_R
• pwm::pcgr::PWM_CLK_BYPASS_W
• pwm::pcgr::PWM_CLK_GATING_R
• pwm::pcgr::PWM_CLK_GATING_W
• pwm::pcntr::PWM_COUNTER_START_R
• pwm::pcntr::PWM_COUNTER_START_W
• pwm::pcntr::PWM_COUNTER_STATUS_R
• pwm::pcr::PWM_ACT_STA_R
• pwm::pcr::PWM_ACT_STA_W
• pwm::pcr::PWM_MODE_R
• pwm::pcr::PWM_MODE_W
• pwm::pcr::PWM_PERIOD_RDY_R
• pwm::pcr::PWM_PRESCAL_K_R
• pwm::pcr::PWM_PRESCAL_K_W
• pwm::pcr::PWM_PUL_NUM_R
• pwm::pcr::PWM_PUL_NUM_W
• pwm::pcr::PWM_PUL_START_R
• pwm::pcr::PWM_PUL_START_W
• pwm::pdzcr01::PWM01_DZ_EN_R
• pwm::pdzcr01::PWM01_DZ_EN_W
• pwm::pdzcr01::PWM01_DZ_INTV_R
• pwm::pdzcr01::PWM01_DZ_INTV_W
• pwm::pdzcr23::PWM23_DZ_EN_R
• pwm::pdzcr23::PWM23_DZ_EN_W
• pwm::pdzcr23::PWM23_DZ_INTV_R
• pwm::pdzcr23::PWM23_DZ_INTV_W
• pwm::pdzcr45::PWM45_DZ_EN_R
• pwm::pdzcr45::PWM45_DZ_EN_W
• pwm::pdzcr45::PWM45_DZ_INTV_R
• pwm::pdzcr45::PWM45_DZ_INTV_W
• pwm::pdzcr67::PWM67_DZ_EN_R
• pwm::pdzcr67::PWM67_DZ_EN_W
• pwm::pdzcr67::PWM67_DZ_INTV_R
• pwm::pdzcr67::PWM67_DZ_INTV_W
• pwm::per::PWM_EN_R
• pwm::per::PWM_EN_W
• pwm::pgr::CS_R
• pwm::pgr::CS_W
• pwm::pgr::EN_R
• pwm::pgr::EN_W
• pwm::pgr::START_R
• pwm::pgr::START_W
• pwm::pier::PCIE_R
• pwm::pier::PCIE_W
• pwm::pier::PGIE_R
• pwm::pier::PGIE_W
• pwm::pisr::PGIS_R
• pwm::pisr::PGIS_W
• pwm::pisr::PIS_R
• pwm::pisr::PIS_W
• pwm::ppcntr::PWM_PUL_COUNTER_STATUS_R
• pwm::ppr::PWM_ACT_CYCLE_R
• pwm::ppr::PWM_ACT_CYCLE_W
• pwm::ppr::PWM_ENTIRE_CYCLE_R
• pwm::ppr::PWM_ENTIRE_CYCLE_W
• rtc::ALARM0_CUR_VLU_REG
• rtc::ALARM0_DAY_SET_REG
• rtc::ALARM0_ENABLE_REG
• rtc::ALARM0_IRQ_EN
• rtc::ALARM0_IRQ_STA_REG
• rtc::ALARM_CONFIG_REG
• rtc::DCXO_CTRL_REG
• rtc::EFUSE_HV_PWRSWT_CTRL_REG
• rtc::FBOOT_INFO_REG0
• rtc::FBOOT_INFO_REG1
• rtc::GP_DATA_REG
• rtc::IC_CHARA_REG
• rtc::INTOSC_CLK_PRESCAL_REG
• rtc::LOSC_AUTO_SWT_STA_REG
• rtc::LOSC_CTRL_REG
• rtc::RTC_DAY_REG
• rtc::RTC_HH_MM_SS_REG
• rtc::RTC_SPI_CLK_CTRL_REG
• rtc::RTC_VIO_REG
• rtc::VDD_OFF_GATING_CTRL_REG
• rtc::_32K_FOUT_CTRL_GATING_REG
• smhc::EMMC_DDR_SBIT_DET
• smhc::SMHC_A12A
• smhc::SMHC_A23A
• smhc::SMHC_BLKSIZ
• smhc::SMHC_BYTCNT
• smhc::SMHC_CLKDIV
• smhc::SMHC_CMD
• smhc::SMHC_CMDARG
• smhc::SMHC_CSDC
• smhc::SMHC_CTRL
• smhc::SMHC_CTYPE
• smhc::SMHC_DBGC
• smhc::SMHC_DLBA
• smhc::SMHC_DRV_DL
• smhc::SMHC_DS_DL
• smhc::SMHC_EXT_CMD
• smhc::SMHC_EXT_RESP
• smhc::SMHC_FIFO
• smhc::SMHC_FIFOTH
• smhc::SMHC_FUNS
• smhc::SMHC_HS400_DL
• smhc::SMHC_HWRST
• smhc::SMHC_IDIE
• smhc::SMHC_IDMAC
• smhc::SMHC_IDST
• smhc::SMHC_INTMASK
• smhc::SMHC_MINTSTS
• smhc::SMHC_NTSR
• smhc::SMHC_RESP0
• smhc::SMHC_RESP1
• smhc::SMHC_RESP2
• smhc::SMHC_RESP3
• smhc::SMHC_RINTSTS
• smhc::SMHC_SFC
• smhc::SMHC_SMAP_DL
• smhc::SMHC_STATUS
• smhc::SMHC_TBC0
• smhc::SMHC_TBC1
• smhc::SMHC_THLD
• smhc::SMHC_TMOUT
• smhc::emmc_ddr_sbit_det::HALF_START_BIT_R
• smhc::emmc_ddr_sbit_det::HALF_START_BIT_W
• smhc::emmc_ddr_sbit_det::HS400_MD_EN_R
• smhc::emmc_ddr_sbit_det::HS400_MD_EN_W
• smhc::smhc_a12a::SD_A12A_R
• smhc::smhc_a12a::SD_A12A_W
• smhc::smhc_blksiz::BLK_SZ_R
• smhc::smhc_blksiz::BLK_SZ_W
• smhc::smhc_clkdiv::CCLK_CTRL_R
• smhc::smhc_clkdiv::CCLK_CTRL_W
• smhc::smhc_clkdiv::CCLK_DIV_R
• smhc::smhc_clkdiv::CCLK_DIV_W
• smhc::smhc_clkdiv::CCLK_ENB_R
• smhc::smhc_clkdiv::CCLK_ENB_W
• smhc::smhc_clkdiv::MASK_DATA0_R
• smhc::smhc_clkdiv::MASK_DATA0_W
• smhc::smhc_cmd::BOOT_ABT_R
• smhc::smhc_cmd::BOOT_ABT_W
• smhc::smhc_cmd::BOOT_MOD_R
• smhc::smhc_cmd::BOOT_MOD_W
• smhc::smhc_cmd::CHK_RESP_CRC_R
• smhc::smhc_cmd::CHK_RESP_CRC_W
• smhc::smhc_cmd::CMD_IDX_R
• smhc::smhc_cmd::CMD_IDX_W
• smhc::smhc_cmd::CMD_LOAD_R
• smhc::smhc_cmd::CMD_LOAD_W
• smhc::smhc_cmd::DATA_TRANS_R
• smhc::smhc_cmd::DATA_TRANS_W
• smhc::smhc_cmd::EXP_BOOT_ACK_R
• smhc::smhc_cmd::EXP_BOOT_ACK_W
• smhc::smhc_cmd::LONG_RESP_R
• smhc::smhc_cmd::LONG_RESP_W
• smhc::smhc_cmd::PRG_CLK_R
• smhc::smhc_cmd::PRG_CLK_W
• smhc::smhc_cmd::RESP_RCV_R
• smhc::smhc_cmd::RESP_RCV_W
• smhc::smhc_cmd::SEND_INIT_SEQ_R
• smhc::smhc_cmd::SEND_INIT_SEQ_W
• smhc::smhc_cmd::STOP_ABT_CMD_R
• smhc::smhc_cmd::STOP_ABT_CMD_W
• smhc::smhc_cmd::STOP_CMD_FLAG_R
• smhc::smhc_cmd::STOP_CMD_FLAG_W
• smhc::smhc_cmd::TRANS_DIR_R
• smhc::smhc_cmd::TRANS_DIR_W
• smhc::smhc_cmd::TRANS_MODE_R
• smhc::smhc_cmd::TRANS_MODE_W
• smhc::smhc_cmd::VOL_SW_R
• smhc::smhc_cmd::VOL_SW_W
• smhc::smhc_cmd::WAIT_PRE_OVER_R
• smhc::smhc_cmd::WAIT_PRE_OVER_W
• smhc::smhc_csdc::CRC_DET_PARA_R
• smhc::smhc_csdc::CRC_DET_PARA_W
• smhc::smhc_ctrl::CD_DBC_ENB_R
• smhc::smhc_ctrl::CD_DBC_ENB_W
• smhc::smhc_ctrl::DDR_MOD_SEL_R
• smhc::smhc_ctrl::DDR_MOD_SEL_W
• smhc::smhc_ctrl::DMA_ENB_R
• smhc::smhc_ctrl::DMA_ENB_W
• smhc::smhc_ctrl::DMA_RST_R
• smhc::smhc_ctrl::DMA_RST_W
• smhc::smhc_ctrl::FIFO_AC_MOD_R
• smhc::smhc_ctrl::FIFO_AC_MOD_W
• smhc::smhc_ctrl::FIFO_RST_R
• smhc::smhc_ctrl::FIFO_RST_W
• smhc::smhc_ctrl::INE_ENB_R
• smhc::smhc_ctrl::INE_ENB_W
• smhc::smhc_ctrl::SOFT_RST_R
• smhc::smhc_ctrl::SOFT_RST_W
• smhc::smhc_ctrl::TIME_UNIT_CMD_R
• smhc::smhc_ctrl::TIME_UNIT_CMD_W
• smhc::smhc_ctrl::TIME_UNIT_DAT_R
• smhc::smhc_ctrl::TIME_UNIT_DAT_W
• smhc::smhc_ctype::CARD_WID_R
• smhc::smhc_ctype::CARD_WID_W
• smhc::smhc_drv_dl::CMD_DRV_PH_SEL_R
• smhc::smhc_drv_dl::CMD_DRV_PH_SEL_W
• smhc::smhc_drv_dl::DAT_DRV_PH_SEL_R
• smhc::smhc_drv_dl::DAT_DRV_PH_SEL_W
• smhc::smhc_ds_dl::DS_DL_CAL_DONE_R
• smhc::smhc_ds_dl::DS_DL_CAL_START_R
• smhc::smhc_ds_dl::DS_DL_CAL_START_W
• smhc::smhc_ds_dl::DS_DL_R
• smhc::smhc_ds_dl::DS_DL_SW_EN_R
• smhc::smhc_ds_dl::DS_DL_SW_EN_W
• smhc::smhc_ds_dl::DS_DL_SW_R
• smhc::smhc_ds_dl::DS_DL_SW_W
• smhc::smhc_ext_cmd::AUTO_CMD23_EN_R
• smhc::smhc_ext_cmd::AUTO_CMD23_EN_W
• smhc::smhc_fifoth::BSIZE_OF_TRANS_R
• smhc::smhc_fifoth::BSIZE_OF_TRANS_W
• smhc::smhc_fifoth::RX_TL_R
• smhc::smhc_fifoth::RX_TL_W
• smhc::smhc_fifoth::TX_TL_R
• smhc::smhc_fifoth::TX_TL_W
• smhc::smhc_funs::ABT_RDATA_R
• smhc::smhc_funs::ABT_RDATA_W
• smhc::smhc_funs::HOST_SEND_MIMC_IRQRESQ_R
• smhc::smhc_funs::HOST_SEND_MIMC_IRQRESQ_W
• smhc::smhc_funs::READ_WAIT_R
• smhc::smhc_funs::READ_WAIT_W
• smhc::smhc_hs400_dl::HS400_DL_CAL_DONE_R
• smhc::smhc_hs400_dl::HS400_DL_CAL_START_R
• smhc::smhc_hs400_dl::HS400_DL_CAL_START_W
• smhc::smhc_hs400_dl::HS400_DL_R
• smhc::smhc_hs400_dl::HS400_DL_SW_EN_R
• smhc::smhc_hs400_dl::HS400_DL_SW_EN_W
• smhc::smhc_hs400_dl::HS400_DL_SW_R
• smhc::smhc_hs400_dl::HS400_DL_SW_W
• smhc::smhc_hwrst::HW_RST_R
• smhc::smhc_hwrst::HW_RST_W
• smhc::smhc_idie::DES_UNAVL_INT_ENB_R
• smhc::smhc_idie::DES_UNAVL_INT_ENB_W
• smhc::smhc_idie::ERR_SUM_INT_ENB_R
• smhc::smhc_idie::ERR_SUM_INT_ENB_W
• smhc::smhc_idie::FERR_INT_ENB_R
• smhc::smhc_idie::FERR_INT_ENB_W
• smhc::smhc_idie::RX_INT_ENB_R
• smhc::smhc_idie::RX_INT_ENB_W
• smhc::smhc_idie::TX_INT_ENB_R
• smhc::smhc_idie::TX_INT_ENB_W
• smhc::smhc_idmac::DES_LOAD_CTRL_W
• smhc::smhc_idmac::FIX_BUST_CTRL_R
• smhc::smhc_idmac::FIX_BUST_CTRL_W
• smhc::smhc_idmac::IDMAC_ENB_R
• smhc::smhc_idmac::IDMAC_ENB_W
• smhc::smhc_idmac::IDMAC_RST_R
• smhc::smhc_idmac::IDMAC_RST_W
• smhc::smhc_idst::ABN_INT_SUM_R
• smhc::smhc_idst::ABN_INT_SUM_W
• smhc::smhc_idst::DES_UNAVL_INT_R
• smhc::smhc_idst::DES_UNAVL_INT_W
• smhc::smhc_idst::ERR_FLAG_SUM_R
• smhc::smhc_idst::ERR_FLAG_SUM_W
• smhc::smhc_idst::FATAL_BERR_INT_R
• smhc::smhc_idst::FATAL_BERR_INT_W
• smhc::smhc_idst::IDMAC_ERR_STA_R
• smhc::smhc_idst::NOR_INT_SUM_R
• smhc::smhc_idst::NOR_INT_SUM_W
• smhc::smhc_idst::RX_INT_R
• smhc::smhc_idst::RX_INT_W
• smhc::smhc_idst::TX_INT_R
• smhc::smhc_idst::TX_INT_W
• smhc::smhc_intmask::ACD_INT_EN_R
• smhc::smhc_intmask::ACD_INT_EN_W
• smhc::smhc_intmask::CARD_INSERT_INT_EN_R
• smhc::smhc_intmask::CARD_INSERT_INT_EN_W
• smhc::smhc_intmask::CARD_REMOVAL_INT_EN_R
• smhc::smhc_intmask::CARD_REMOVAL_INT_EN_W
• smhc::smhc_intmask::CB_IW_INT_EN_R
• smhc::smhc_intmask::CB_IW_INT_EN_W
• smhc::smhc_intmask::CC_INT_EN_R
• smhc::smhc_intmask::CC_INT_EN_W
• smhc::smhc_intmask::DCE_INT_EN_R
• smhc::smhc_intmask::DCE_INT_EN_W
• smhc::smhc_intmask::DEE_INT_EN_R
• smhc::smhc_intmask::DEE_INT_EN_W
• smhc::smhc_intmask::DRR_INT_EN_R
• smhc::smhc_intmask::DRR_INT_EN_W
• smhc::smhc_intmask::DSE_BC_INT_EN_R
• smhc::smhc_intmask::DSE_BC_INT_EN_W
• smhc::smhc_intmask::DSTO_VSD_INT_EN_R
• smhc::smhc_intmask::DSTO_VSD_INT_EN_W
• smhc::smhc_intmask::DTC_INT_EN_R
• smhc::smhc_intmask::DTC_INT_EN_W
• smhc::smhc_intmask::DTO_BDS_INT_EN_R
• smhc::smhc_intmask::DTO_BDS_INT_EN_W
• smhc::smhc_intmask::DTR_INT_EN_R
• smhc::smhc_intmask::DTR_INT_EN_W
• smhc::smhc_intmask::FU_FO_INT_EN_R
• smhc::smhc_intmask::FU_FO_INT_EN_W
• smhc::smhc_intmask::RCE_INT_EN_R
• smhc::smhc_intmask::RCE_INT_EN_W
• smhc::smhc_intmask::RE_INT_EN_R
• smhc::smhc_intmask::RE_INT_EN_W
• smhc::smhc_intmask::RTO_BACK_INT_EN_R
• smhc::smhc_intmask::RTO_BACK_INT_EN_W
• smhc::smhc_intmask::SDIO_INT_EN_R
• smhc::smhc_intmask::SDIO_INT_EN_W
• smhc::smhc_mintsts::M_ACD_INT_R
• smhc::smhc_mintsts::M_CARD_INSERT_R
• smhc::smhc_mintsts::M_CARD_REMOVAL_INT_R
• smhc::smhc_mintsts::M_CB_IW_INT_R
• smhc::smhc_mintsts::M_CC_INT_R
• smhc::smhc_mintsts::M_DCE_INT_R
• smhc::smhc_mintsts::M_DEE_INT_R
• smhc::smhc_mintsts::M_DRR_INT_R
• smhc::smhc_mintsts::M_DSE_BC_INT_R
• smhc::smhc_mintsts::M_DSTO_VSD_INT_R
• smhc::smhc_mintsts::M_DTC_INT_R
• smhc::smhc_mintsts::M_DTO_BDS_INT_R
• smhc::smhc_mintsts::M_DTR_INT_R
• smhc::smhc_mintsts::M_FU_FO_INT_R
• smhc::smhc_mintsts::M_RCE_INT_R
• smhc::smhc_mintsts::M_RE_INT_R
• smhc::smhc_mintsts::M_RTO_BACK_INT_R
• smhc::smhc_mintsts::M_SDIO_INT_R
• smhc::smhc_ntsr::CMD_DAT_RX_PHASE_CLR_R
• smhc::smhc_ntsr::CMD_DAT_RX_PHASE_CLR_W
• smhc::smhc_ntsr::CMD_SAMPLE_TIMING_PHASE_R
• smhc::smhc_ntsr::CMD_SAMPLE_TIMING_PHASE_W
• smhc::smhc_ntsr::CMD_SEND_RX_PHASE_CLR_R
• smhc::smhc_ntsr::CMD_SEND_RX_PHASE_CLR_W
• smhc::smhc_ntsr::DAT_CRC_STATUS_RX_PHASE_CLR_R
• smhc::smhc_ntsr::DAT_CRC_STATUS_RX_PHASE_CLR_W
• smhc::smhc_ntsr::DAT_RECV_RX_PHASE_CLR_R
• smhc::smhc_ntsr::DAT_RECV_RX_PHASE_CLR_W
• smhc::smhc_ntsr::DAT_SAMPLE_TIMING_PHASE_R
• smhc::smhc_ntsr::DAT_SAMPLE_TIMING_PHASE_W
• smhc::smhc_ntsr::DAT_TRANS_RX_PHASE_CLR_R
• smhc::smhc_ntsr::DAT_TRANS_RX_PHASE_CLR_W
• smhc::smhc_ntsr::HS400_NEW_SAMPLE_EN_R
• smhc::smhc_ntsr::HS400_NEW_SAMPLE_EN_W
• smhc::smhc_ntsr::MODE_SELECT_R
• smhc::smhc_ntsr::MODE_SELECT_W
• smhc::smhc_rintsts::ACD_R
• smhc::smhc_rintsts::ACD_W
• smhc::smhc_rintsts::CARD_INSERT_R
• smhc::smhc_rintsts::CARD_INSERT_W
• smhc::smhc_rintsts::CARD_REMOVAL_R
• smhc::smhc_rintsts::CARD_REMOVAL_W
• smhc::smhc_rintsts::CB_IW_R
• smhc::smhc_rintsts::CB_IW_W
• smhc::smhc_rintsts::CC_R
• smhc::smhc_rintsts::CC_W
• smhc::smhc_rintsts::DCE_R
• smhc::smhc_rintsts::DCE_W
• smhc::smhc_rintsts::DEE_R
• smhc::smhc_rintsts::DEE_W
• smhc::smhc_rintsts::DRR_R
• smhc::smhc_rintsts::DRR_W
• smhc::smhc_rintsts::DSE_BC_R
• smhc::smhc_rintsts::DSE_BC_W
• smhc::smhc_rintsts::DSTO_VSD_R
• smhc::smhc_rintsts::DSTO_VSD_W
• smhc::smhc_rintsts::DTC_R
• smhc::smhc_rintsts::DTC_W
• smhc::smhc_rintsts::DTO_BDS_R
• smhc::smhc_rintsts::DTO_BDS_W
• smhc::smhc_rintsts::DTR_R
• smhc::smhc_rintsts::DTR_W
• smhc::smhc_rintsts::FU_FO_R
• smhc::smhc_rintsts::FU_FO_W
• smhc::smhc_rintsts::RCE_R
• smhc::smhc_rintsts::RCE_W
• smhc::smhc_rintsts::RE_R
• smhc::smhc_rintsts::RE_W
• smhc::smhc_rintsts::RTO_BACK_R
• smhc::smhc_rintsts::RTO_BACK_W
• smhc::smhc_rintsts::SDIOI_INT_R
• smhc::smhc_rintsts::SDIOI_INT_W
• smhc::smhc_sfc::BYPASS_EN_R
• smhc::smhc_sfc::BYPASS_EN_W
• smhc::smhc_sfc::STOP_CLK_CTRL_R
• smhc::smhc_sfc::STOP_CLK_CTRL_W
• smhc::smhc_smap_dl::SAMP_DL_CAL_DONE_R
• smhc::smhc_smap_dl::SAMP_DL_CAL_START_R
• smhc::smhc_smap_dl::SAMP_DL_CAL_START_W
• smhc::smhc_smap_dl::SAMP_DL_R
• smhc::smhc_smap_dl::SAMP_DL_SW_EN_R
• smhc::smhc_smap_dl::SAMP_DL_SW_EN_W
• smhc::smhc_smap_dl::SAMP_DL_SW_R
• smhc::smhc_smap_dl::SAMP_DL_SW_W
• smhc::smhc_status::CARD_BUSY_R
• smhc::smhc_status::CARD_PRESENT_R
• smhc::smhc_status::DMA_REQ_R
• smhc::smhc_status::FIFO_EMPTY_R
• smhc::smhc_status::FIFO_FULL_R
• smhc::smhc_status::FIFO_LEVEL_R
• smhc::smhc_status::FIFO_RX_LEVEL_R
• smhc::smhc_status::FIFO_TX_LEVEL_R
• smhc::smhc_status::FSM_BUSY_R
• smhc::smhc_status::FSM_STA_R
• smhc::smhc_status::RESP_IDX_R
• smhc::smhc_thld::BCIG_R
• smhc::smhc_thld::BCIG_W
• smhc::smhc_thld::CARD_RD_THLD_ENB_R
• smhc::smhc_thld::CARD_RD_THLD_ENB_W
• smhc::smhc_thld::CARD_WR_THLD_ENB_R
• smhc::smhc_thld::CARD_WR_THLD_ENB_W
• smhc::smhc_thld::CARD_WR_THLD_R
• smhc::smhc_thld::CARD_WR_THLD_W
• smhc::smhc_tmout::DTO_LMT_R
• smhc::smhc_tmout::DTO_LMT_W
• smhc::smhc_tmout::RTO_LMT_R
• smhc::smhc_tmout::RTO_LMT_W
• spi0::SPI_BATC
• spi0::SPI_BA_CCR
• spi0::SPI_BCC
• spi0::SPI_FCR
• spi0::SPI_FSR
• spi0::SPI_GCR
• spi0::SPI_IER
• spi0::SPI_ISR
• spi0::SPI_MBC
• spi0::SPI_MTC
• spi0::SPI_NDMA_MODE_CTL
• spi0::SPI_RBR
• spi0::SPI_RXD
• spi0::SPI_RXD_16
• spi0::SPI_RXD_8
• spi0::SPI_SAMP_DL
• spi0::SPI_TBR
• spi0::SPI_TCR
• spi0::SPI_TXD
• spi0::SPI_TXD_16
• spi0::SPI_TXD_8
• spi0::SPI_WCR
• spi0::spi_ba_ccr::CDR_N_R
• spi0::spi_ba_ccr::CDR_N_W
• spi0::spi_batc::MSMS_R
• spi0::spi_batc::MSMS_W
• spi0::spi_batc::RX_FRM_LEN_R
• spi0::spi_batc::RX_FRM_LEN_W
• spi0::spi_batc::SPOL_R
• spi0::spi_batc::SPOL_W
• spi0::spi_batc::SS_LEVEL_R
• spi0::spi_batc::SS_LEVEL_W
• spi0::spi_batc::SS_OWNER_R
• spi0::spi_batc::SS_OWNER_W
• spi0::spi_batc::SS_SEL_R
• spi0::spi_batc::SS_SEL_W
• spi0::spi_batc::TBC_INT_EN_R
• spi0::spi_batc::TBC_INT_EN_W
• spi0::spi_batc::TBC_R
• spi0::spi_batc::TBC_W
• spi0::spi_batc::TCE_R
• spi0::spi_batc::TCE_W
• spi0::spi_batc::TX_FRM_LEN_R
• spi0::spi_batc::TX_FRM_LEN_W
• spi0::spi_batc::WMS_R
• spi0::spi_batc::WMS_W
• spi0::spi_bcc::DBC_R
• spi0::spi_bcc::DBC_W
• spi0::spi_bcc::DRM_R
• spi0::spi_bcc::DRM_W
• spi0::spi_bcc::QUAD_EN_R
• spi0::spi_bcc::QUAD_EN_W
• spi0::spi_bcc::STC_R
• spi0::spi_bcc::STC_W
• spi0::spi_fcr::RF_DRQ_EN_R
• spi0::spi_fcr::RF_DRQ_EN_W
• spi0::spi_fcr::RF_RST_R
• spi0::spi_fcr::RF_RST_W
• spi0::spi_fcr::RF_TEST_EN_R
• spi0::spi_fcr::RF_TEST_EN_W
• spi0::spi_fcr::RF_TRIG_LEVEL_R
• spi0::spi_fcr::RF_TRIG_LEVEL_W
• spi0::spi_fcr::TF_DRQ_EN_R
• spi0::spi_fcr::TF_DRQ_EN_W
• spi0::spi_fcr::TF_RST_R
• spi0::spi_fcr::TF_RST_W
• spi0::spi_fcr::TF_TEST_EN_R
• spi0::spi_fcr::TF_TEST_EN_W
• spi0::spi_fcr::TF_TRIG_LEVEL_R
• spi0::spi_fcr::TF_TRIG_LEVEL_W
• spi0::spi_fsr::RB_CNT_R
• spi0::spi_fsr::RB_WR_R
• spi0::spi_fsr::RF_CNT_R
• spi0::spi_fsr::TB_CNT_R
• spi0::spi_fsr::TB_WR_R
• spi0::spi_fsr::TF_CNT_R
• spi0::spi_gcr::EN_R
• spi0::spi_gcr::EN_W
• spi0::spi_gcr::MODE_R
• spi0::spi_gcr::MODE_SELEC_R
• spi0::spi_gcr::MODE_SELEC_W
• spi0::spi_gcr::MODE_W
• spi0::spi_gcr::SRST_R
• spi0::spi_gcr::SRST_W
• spi0::spi_gcr::TP_EN_R
• spi0::spi_gcr::TP_EN_W
• spi0::spi_ier::RF_EMP_INT_EN_R
• spi0::spi_ier::RF_EMP_INT_EN_W
• spi0::spi_ier::RF_FULL_INT_EN_R
• spi0::spi_ier::RF_FULL_INT_EN_W
• spi0::spi_ier::RF_OVF_INT_EN_R
• spi0::spi_ier::RF_OVF_INT_EN_W
• spi0::spi_ier::RF_RDY_INT_EN_R
• spi0::spi_ier::RF_RDY_INT_EN_W
• spi0::spi_ier::RF_UDR_INT_EN_R
• spi0::spi_ier::RF_UDR_INT_EN_W
• spi0::spi_ier::SS_INT_EN_R
• spi0::spi_ier::SS_INT_EN_W
• spi0::spi_ier::TC_INT_EN_R
• spi0::spi_ier::TC_INT_EN_W
• spi0::spi_ier::TF_EMP_INT_EN_R
• spi0::spi_ier::TF_EMP_INT_EN_W
• spi0::spi_ier::TF_ERQ_INT_EN_R
• spi0::spi_ier::TF_ERQ_INT_EN_W
• spi0::spi_ier::TF_FULL_INT_EN_R
• spi0::spi_ier::TF_FULL_INT_EN_W
• spi0::spi_ier::TF_OVF_INT_EN_R
• spi0::spi_ier::TF_OVF_INT_EN_W
• spi0::spi_ier::TF_UDR_INT_EN_R
• spi0::spi_ier::TF_UDR_INT_EN_W
• spi0::spi_isr::RF_EMP_R
• spi0::spi_isr::RF_EMP_W
• spi0::spi_isr::RF_FULL_R
• spi0::spi_isr::RF_FULL_W
• spi0::spi_isr::RF_OVF_R
• spi0::spi_isr::RF_OVF_W
• spi0::spi_isr::RF_RDY_R
• spi0::spi_isr::RF_RDY_W
• spi0::spi_isr::RF_UDR_R
• spi0::spi_isr::RF_UDR_W
• spi0::spi_isr::SSI_R
• spi0::spi_isr::SSI_W
• spi0::spi_isr::TC_R
• spi0::spi_isr::TC_W
• spi0::spi_isr::TF_EMP_R
• spi0::spi_isr::TF_EMP_W
• spi0::spi_isr::TF_FULL_R
• spi0::spi_isr::TF_FULL_W
• spi0::spi_isr::TF_OVF_R
• spi0::spi_isr::TF_OVF_W
• spi0::spi_isr::TF_READY_R
• spi0::spi_isr::TF_READY_W
• spi0::spi_isr::TF_UDR_R
• spi0::spi_isr::TF_UDR_W
• spi0::spi_mbc::MBC_R
• spi0::spi_mbc::MBC_W
• spi0::spi_mtc::MWTC_R
• spi0::spi_mtc::MWTC_W
• spi0::spi_ndma_mode_ctl::SPI_ACK_M_R
• spi0::spi_ndma_mode_ctl::SPI_ACK_M_W
• spi0::spi_ndma_mode_ctl::SPI_ACT_M_R
• spi0::spi_ndma_mode_ctl::SPI_ACT_M_W
• spi0::spi_ndma_mode_ctl::SPI_DMA_WAIT_R
• spi0::spi_ndma_mode_ctl::SPI_DMA_WAIT_W
• spi0::spi_samp_dl::SAMP_DL_CAL_DONE_R
• spi0::spi_samp_dl::SAMP_DL_CAL_START_R
• spi0::spi_samp_dl::SAMP_DL_CAL_START_W
• spi0::spi_samp_dl::SAMP_DL_R
• spi0::spi_samp_dl::SAMP_DL_SW_EN_R
• spi0::spi_samp_dl::SAMP_DL_SW_EN_W
• spi0::spi_samp_dl::SAMP_DL_SW_R
• spi0::spi_samp_dl::SAMP_DL_SW_W
• spi0::spi_tcr::CPHA_R
• spi0::spi_tcr::CPHA_W
• spi0::spi_tcr::CPOL_R
• spi0::spi_tcr::CPOL_W
• spi0::spi_tcr::DDB_R
• spi0::spi_tcr::DDB_W
• spi0::spi_tcr::DHB_R
• spi0::spi_tcr::DHB_W
• spi0::spi_tcr::FBS_R
• spi0::spi_tcr::FBS_W
• spi0::spi_tcr::RPSM_R
• spi0::spi_tcr::RPSM_W
• spi0::spi_tcr::SDC1_R
• spi0::spi_tcr::SDC1_W
• spi0::spi_tcr::SDC_R
• spi0::spi_tcr::SDC_W
• spi0::spi_tcr::SDDM_R
• spi0::spi_tcr::SDDM_W
• spi0::spi_tcr::SDM_R
• spi0::spi_tcr::SDM_W
• spi0::spi_tcr::SPOL_R
• spi0::spi_tcr::SPOL_W
• spi0::spi_tcr::SSCTL_R
• spi0::spi_tcr::SSCTL_W
• spi0::spi_tcr::SS_LEVEL_R
• spi0::spi_tcr::SS_LEVEL_W
• spi0::spi_tcr::SS_OWNER_R
• spi0::spi_tcr::SS_OWNER_W
• spi0::spi_tcr::SS_SEL_R
• spi0::spi_tcr::SS_SEL_W
• spi0::spi_tcr::XCH_R
• spi0::spi_tcr::XCH_W
• spi0::spi_wcr::SWC_R
• spi0::spi_wcr::SWC_W
• spi0::spi_wcr::WWC_R
• spi0::spi_wcr::WWC_W
• spi_dbi::DBI_CTL_0
• spi_dbi::DBI_CTL_1
• spi_dbi::DBI_CTL_2
• spi_dbi::DBI_DEBUG_0
• spi_dbi::DBI_DEBUG_1
• spi_dbi::DBI_INT
• spi_dbi::DBI_TIMER
• spi_dbi::DBI_VIDEO_SZIE
• spi_dbi::SPI_BATC
• spi_dbi::SPI_BA_CCR
• spi_dbi::SPI_BCC
• spi_dbi::SPI_FCR
• spi_dbi::SPI_FSR
• spi_dbi::SPI_GCR
• spi_dbi::SPI_IER
• spi_dbi::SPI_ISR
• spi_dbi::SPI_MBC
• spi_dbi::SPI_MTC
• spi_dbi::SPI_NDMA_MODE_CTL
• spi_dbi::SPI_RBR
• spi_dbi::SPI_RXD
• spi_dbi::SPI_SAMP_DL
• spi_dbi::SPI_TBR
• spi_dbi::SPI_TCR
• spi_dbi::SPI_TXD
• spi_dbi::SPI_WCR
• spi_dbi::dbi_ctl_0::CMDT_R
• spi_dbi::dbi_ctl_0::CMDT_W
• spi_dbi::dbi_ctl_0::DAT_FMT_R
• spi_dbi::dbi_ctl_0::DAT_FMT_W
• spi_dbi::dbi_ctl_0::DAT_SEQ_R
• spi_dbi::dbi_ctl_0::DAT_SEQ_W
• spi_dbi::dbi_ctl_0::DBI_INTERFACE_R
• spi_dbi::dbi_ctl_0::DBI_INTERFACE_W
• spi_dbi::dbi_ctl_0::DUM_VAL_R
• spi_dbi::dbi_ctl_0::DUM_VAL_W
• spi_dbi::dbi_ctl_0::ELEMENT_A_POS_R
• spi_dbi::dbi_ctl_0::ELEMENT_A_POS_W
• spi_dbi::dbi_ctl_0::RGB_BO_R
• spi_dbi::dbi_ctl_0::RGB_BO_W
• spi_dbi::dbi_ctl_0::RGB_SEQ_R
• spi_dbi::dbi_ctl_0::RGB_SEQ_W
• spi_dbi::dbi_ctl_0::RGB_SRC_FMT_R
• spi_dbi::dbi_ctl_0::RGB_SRC_FMT_W
• spi_dbi::dbi_ctl_0::TRAN_MOD_R
• spi_dbi::dbi_ctl_0::TRAN_MOD_W
• spi_dbi::dbi_ctl_0::VI_SRC_TYPE_R
• spi_dbi::dbi_ctl_0::VI_SRC_TYPE_W
• spi_dbi::dbi_ctl_0::WCDC_R
• spi_dbi::dbi_ctl_0::WCDC_W
• spi_dbi::dbi_ctl_1::DBI_CLKO_INV_R
• spi_dbi::dbi_ctl_1::DBI_CLKO_INV_W
• spi_dbi::dbi_ctl_1::DBI_CLKO_MOD_R
• spi_dbi::dbi_ctl_1::DBI_CLKO_MOD_W
• spi_dbi::dbi_ctl_1::DBI_EN_MODE_SEL_R
• spi_dbi::dbi_ctl_1::DBI_EN_MODE_SEL_W
• spi_dbi::dbi_ctl_1::DBI_RXCLK_INV_R
• spi_dbi::dbi_ctl_1::DBI_RXCLK_INV_W
• spi_dbi::dbi_ctl_1::DBI_SOFT_TRG_R
• spi_dbi::dbi_ctl_1::DBI_SOFT_TRG_W
• spi_dbi::dbi_ctl_1::DCX_DATA_R
• spi_dbi::dbi_ctl_1::DCX_DATA_W
• spi_dbi::dbi_ctl_1::RCDC_R
• spi_dbi::dbi_ctl_1::RCDC_W
• spi_dbi::dbi_ctl_1::RDAT_LSB_R
• spi_dbi::dbi_ctl_1::RDAT_LSB_W
• spi_dbi::dbi_ctl_1::RDBN_R
• spi_dbi::dbi_ctl_1::RDBN_W
• spi_dbi::dbi_ctl_1::RGB16_DATA_SOURCE_SELECT_R
• spi_dbi::dbi_ctl_1::RGB16_DATA_SOURCE_SELECT_W
• spi_dbi::dbi_ctl_1::RGB666_FMT_R
• spi_dbi::dbi_ctl_1::RGB666_FMT_W
• spi_dbi::dbi_ctl_2::DBI_DCX_SEL_R
• spi_dbi::dbi_ctl_2::DBI_DCX_SEL_W
• spi_dbi::dbi_ctl_2::DBI_FIFO_DRQ_EN_R
• spi_dbi::dbi_ctl_2::DBI_FIFO_DRQ_EN_W
• spi_dbi::dbi_ctl_2::DBI_SDI_SEL_R
• spi_dbi::dbi_ctl_2::DBI_SDI_SEL_W
• spi_dbi::dbi_ctl_2::DBI_SDQ_OUT_SEL_R
• spi_dbi::dbi_ctl_2::DBI_SDQ_OUT_SEL_W
• spi_dbi::dbi_ctl_2::DBI_TRIG_LEVEL_R
• spi_dbi::dbi_ctl_2::DBI_TRIG_LEVEL_W
• spi_dbi::dbi_ctl_2::TE_DBC_SEL_R
• spi_dbi::dbi_ctl_2::TE_DBC_SEL_W
• spi_dbi::dbi_ctl_2::TE_EN_R
• spi_dbi::dbi_ctl_2::TE_EN_W
• spi_dbi::dbi_ctl_2::TE_TRIG_SEL_R
• spi_dbi::dbi_ctl_2::TE_TRIG_SEL_W
• spi_dbi::dbi_debug_0::DBI_FIFO_AVAIL_R
• spi_dbi::dbi_debug_0::DBI_RXCS_R
• spi_dbi::dbi_debug_0::DBI_TXCS_R
• spi_dbi::dbi_debug_0::MEM_CS_R
• spi_dbi::dbi_debug_0::SH_CS_R
• spi_dbi::dbi_debug_0::TE_VAL_R
• spi_dbi::dbi_debug_1::CCNT_R
• spi_dbi::dbi_debug_1::LCNT_R
• spi_dbi::dbi_int::DBI_FIFO_EMPTY_INT_EN_R
• spi_dbi::dbi_int::DBI_FIFO_EMPTY_INT_EN_W
• spi_dbi::dbi_int::DBI_FIFO_EMPTY_INT_R
• spi_dbi::dbi_int::DBI_FIFO_EMPTY_INT_W
• spi_dbi::dbi_int::DBI_FIFO_FULL_INT_EN_R
• spi_dbi::dbi_int::DBI_FIFO_FULL_INT_EN_W
• spi_dbi::dbi_int::DBI_FIFO_FULL_INT_R
• spi_dbi::dbi_int::DBI_FIFO_FULL_INT_W
• spi_dbi::dbi_int::FRAM_DONE_INT_EN_R
• spi_dbi::dbi_int::FRAM_DONE_INT_EN_W
• spi_dbi::dbi_int::FRAM_DONE_INT_R
• spi_dbi::dbi_int::FRAM_DONE_INT_W
• spi_dbi::dbi_int::LINE_DONE_INT_EN_R
• spi_dbi::dbi_int::LINE_DONE_INT_EN_W
• spi_dbi::dbi_int::LINE_DONE_INT_R
• spi_dbi::dbi_int::LINE_DONE_INT_W
• spi_dbi::dbi_int::RD_DONE_INT_EN_R
• spi_dbi::dbi_int::RD_DONE_INT_EN_W
• spi_dbi::dbi_int::RD_DONE_INT_R
• spi_dbi::dbi_int::RD_DONE_INT_W
• spi_dbi::dbi_int::TE_INT_EN_R
• spi_dbi::dbi_int::TE_INT_EN_W
• spi_dbi::dbi_int::TE_INT_R
• spi_dbi::dbi_int::TE_INT_W
• spi_dbi::dbi_int::TIMER_INT_EN_R
• spi_dbi::dbi_int::TIMER_INT_EN_W
• spi_dbi::dbi_int::TIMER_INT_R
• spi_dbi::dbi_int::TIMER_INT_W
• spi_dbi::dbi_timer::DBI_TIMER_VALUE_R
• spi_dbi::dbi_timer::DBI_TIMER_VALUE_W
• spi_dbi::dbi_timer::DBI_TM_EN_R
• spi_dbi::dbi_timer::DBI_TM_EN_W
• spi_dbi::dbi_video_szie::H_SIZE_R
• spi_dbi::dbi_video_szie::H_SIZE_W
• spi_dbi::dbi_video_szie::V_SIZE_R
• spi_dbi::dbi_video_szie::V_SIZE_W
• spi_dbi::spi_ba_ccr::CDR_N_R
• spi_dbi::spi_ba_ccr::CDR_N_W
• spi_dbi::spi_batc::MSMS_R
• spi_dbi::spi_batc::MSMS_W
• spi_dbi::spi_batc::RX_FRM_LEN_R
• spi_dbi::spi_batc::RX_FRM_LEN_W
• spi_dbi::spi_batc::SPOL_R
• spi_dbi::spi_batc::SPOL_W
• spi_dbi::spi_batc::SS_LEVEL_R
• spi_dbi::spi_batc::SS_LEVEL_W
• spi_dbi::spi_batc::SS_OWNER_R
• spi_dbi::spi_batc::SS_OWNER_W
• spi_dbi::spi_batc::SS_SEL_R
• spi_dbi::spi_batc::SS_SEL_W
• spi_dbi::spi_batc::TBC_INT_EN_R
• spi_dbi::spi_batc::TBC_INT_EN_W
• spi_dbi::spi_batc::TBC_R
• spi_dbi::spi_batc::TBC_W
• spi_dbi::spi_batc::TCE_R
• spi_dbi::spi_batc::TCE_W
• spi_dbi::spi_batc::TX_FRM_LEN_R
• spi_dbi::spi_batc::TX_FRM_LEN_W
• spi_dbi::spi_batc::WMS_R
• spi_dbi::spi_batc::WMS_W
• spi_dbi::spi_bcc::DBC_R
• spi_dbi::spi_bcc::DBC_W
• spi_dbi::spi_bcc::DRM_R
• spi_dbi::spi_bcc::DRM_W
• spi_dbi::spi_bcc::QUAD_EN_R
• spi_dbi::spi_bcc::QUAD_EN_W
• spi_dbi::spi_bcc::STC_R
• spi_dbi::spi_bcc::STC_W
• spi_dbi::spi_fcr::RF_DRQ_EN_R
• spi_dbi::spi_fcr::RF_DRQ_EN_W
• spi_dbi::spi_fcr::RF_RST_R
• spi_dbi::spi_fcr::RF_RST_W
• spi_dbi::spi_fcr::RF_TEST_EN_R
• spi_dbi::spi_fcr::RF_TEST_EN_W
• spi_dbi::spi_fcr::RF_TRIG_LEVEL_R
• spi_dbi::spi_fcr::RF_TRIG_LEVEL_W
• spi_dbi::spi_fcr::TF_DRQ_EN_R
• spi_dbi::spi_fcr::TF_DRQ_EN_W
• spi_dbi::spi_fcr::TF_RST_R
• spi_dbi::spi_fcr::TF_RST_W
• spi_dbi::spi_fcr::TF_TEST_EN_R
• spi_dbi::spi_fcr::TF_TEST_EN_W
• spi_dbi::spi_fcr::TF_TRIG_LEVEL_R
• spi_dbi::spi_fcr::TF_TRIG_LEVEL_W
• spi_dbi::spi_fsr::RB_CNT_R
• spi_dbi::spi_fsr::RB_WR_R
• spi_dbi::spi_fsr::RF_CNT_R
• spi_dbi::spi_fsr::TB_CNT_R
• spi_dbi::spi_fsr::TB_WR_R
• spi_dbi::spi_fsr::TF_CNT_R
• spi_dbi::spi_gcr::EN_R
• spi_dbi::spi_gcr::EN_W
• spi_dbi::spi_gcr::MODE_R
• spi_dbi::spi_gcr::MODE_SELEC_R
• spi_dbi::spi_gcr::MODE_SELEC_W
• spi_dbi::spi_gcr::MODE_W
• spi_dbi::spi_gcr::SRST_R
• spi_dbi::spi_gcr::SRST_W
• spi_dbi::spi_gcr::TP_EN_R
• spi_dbi::spi_gcr::TP_EN_W
• spi_dbi::spi_ier::RF_EMP_INT_EN_R
• spi_dbi::spi_ier::RF_EMP_INT_EN_W
• spi_dbi::spi_ier::RF_FULL_INT_EN_R
• spi_dbi::spi_ier::RF_FULL_INT_EN_W
• spi_dbi::spi_ier::RF_OVF_INT_EN_R
• spi_dbi::spi_ier::RF_OVF_INT_EN_W
• spi_dbi::spi_ier::RF_RDY_INT_EN_R
• spi_dbi::spi_ier::RF_RDY_INT_EN_W
• spi_dbi::spi_ier::RF_UDR_INT_EN_R
• spi_dbi::spi_ier::RF_UDR_INT_EN_W
• spi_dbi::spi_ier::SS_INT_EN_R
• spi_dbi::spi_ier::SS_INT_EN_W
• spi_dbi::spi_ier::TC_INT_EN_R
• spi_dbi::spi_ier::TC_INT_EN_W
• spi_dbi::spi_ier::TF_EMP_INT_EN_R
• spi_dbi::spi_ier::TF_EMP_INT_EN_W
• spi_dbi::spi_ier::TF_ERQ_INT_EN_R
• spi_dbi::spi_ier::TF_ERQ_INT_EN_W
• spi_dbi::spi_ier::TF_FULL_INT_EN_R
• spi_dbi::spi_ier::TF_FULL_INT_EN_W
• spi_dbi::spi_ier::TF_OVF_INT_EN_R
• spi_dbi::spi_ier::TF_OVF_INT_EN_W
• spi_dbi::spi_ier::TF_UDR_INT_EN_R
• spi_dbi::spi_ier::TF_UDR_INT_EN_W
• spi_dbi::spi_isr::RF_EMP_R
• spi_dbi::spi_isr::RF_EMP_W
• spi_dbi::spi_isr::RF_FULL_R
• spi_dbi::spi_isr::RF_FULL_W
• spi_dbi::spi_isr::RF_OVF_R
• spi_dbi::spi_isr::RF_OVF_W
• spi_dbi::spi_isr::RF_RDY_R
• spi_dbi::spi_isr::RF_RDY_W
• spi_dbi::spi_isr::RF_UDR_R
• spi_dbi::spi_isr::RF_UDR_W
• spi_dbi::spi_isr::SSI_R
• spi_dbi::spi_isr::SSI_W
• spi_dbi::spi_isr::TC_R
• spi_dbi::spi_isr::TC_W
• spi_dbi::spi_isr::TF_EMP_R
• spi_dbi::spi_isr::TF_EMP_W
• spi_dbi::spi_isr::TF_FULL_R
• spi_dbi::spi_isr::TF_FULL_W
• spi_dbi::spi_isr::TF_OVF_R
• spi_dbi::spi_isr::TF_OVF_W
• spi_dbi::spi_isr::TF_READY_R
• spi_dbi::spi_isr::TF_READY_W
• spi_dbi::spi_isr::TF_UDR_R
• spi_dbi::spi_isr::TF_UDR_W
• spi_dbi::spi_mbc::MBC_R
• spi_dbi::spi_mbc::MBC_W
• spi_dbi::spi_mtc::MWTC_R
• spi_dbi::spi_mtc::MWTC_W
• spi_dbi::spi_ndma_mode_ctl::SPI_ACK_M_R
• spi_dbi::spi_ndma_mode_ctl::SPI_ACK_M_W
• spi_dbi::spi_ndma_mode_ctl::SPI_ACT_M_R
• spi_dbi::spi_ndma_mode_ctl::SPI_ACT_M_W
• spi_dbi::spi_ndma_mode_ctl::SPI_DMA_WAIT_R
• spi_dbi::spi_ndma_mode_ctl::SPI_DMA_WAIT_W
• spi_dbi::spi_samp_dl::SAMP_DL_CAL_DONE_R
• spi_dbi::spi_samp_dl::SAMP_DL_CAL_START_R
• spi_dbi::spi_samp_dl::SAMP_DL_CAL_START_W
• spi_dbi::spi_samp_dl::SAMP_DL_R
• spi_dbi::spi_samp_dl::SAMP_DL_SW_EN_R
• spi_dbi::spi_samp_dl::SAMP_DL_SW_EN_W
• spi_dbi::spi_samp_dl::SAMP_DL_SW_R
• spi_dbi::spi_samp_dl::SAMP_DL_SW_W
• spi_dbi::spi_tcr::CPHA_R
• spi_dbi::spi_tcr::CPHA_W
• spi_dbi::spi_tcr::CPOL_R
• spi_dbi::spi_tcr::CPOL_W
• spi_dbi::spi_tcr::DDB_R
• spi_dbi::spi_tcr::DDB_W
• spi_dbi::spi_tcr::DHB_R
• spi_dbi::spi_tcr::DHB_W
• spi_dbi::spi_tcr::FBS_R
• spi_dbi::spi_tcr::FBS_W
• spi_dbi::spi_tcr::RPSM_R
• spi_dbi::spi_tcr::RPSM_W
• spi_dbi::spi_tcr::SDC1_R
• spi_dbi::spi_tcr::SDC1_W
• spi_dbi::spi_tcr::SDC_R
• spi_dbi::spi_tcr::SDC_W
• spi_dbi::spi_tcr::SDDM_R
• spi_dbi::spi_tcr::SDDM_W
• spi_dbi::spi_tcr::SDM_R
• spi_dbi::spi_tcr::SDM_W
• spi_dbi::spi_tcr::SPOL_R
• spi_dbi::spi_tcr::SPOL_W
• spi_dbi::spi_tcr::SSCTL_R
• spi_dbi::spi_tcr::SSCTL_W
• spi_dbi::spi_tcr::SS_LEVEL_R
• spi_dbi::spi_tcr::SS_LEVEL_W
• spi_dbi::spi_tcr::SS_OWNER_R
• spi_dbi::spi_tcr::SS_OWNER_W
• spi_dbi::spi_tcr::SS_SEL_R
• spi_dbi::spi_tcr::SS_SEL_W
• spi_dbi::spi_tcr::XCH_R
• spi_dbi::spi_tcr::XCH_W
• spi_dbi::spi_wcr::SWC_R
• spi_dbi::spi_wcr::SWC_W
• spi_dbi::spi_wcr::WWC_R
• spi_dbi::spi_wcr::WWC_W
• spinlock::SPINLOCK_IRQ_EN_REG
• spinlock::SPINLOCK_IRQ_STA_REG
• spinlock::SPINLOCK_LOCKID_REG
• spinlock::SPINLOCK_LOCK_REG
• spinlock::SPINLOCK_STATUS_REG
• spinlock::SPINLOCK_SYSTATUS_REG
• spinlock::spinlock_irq_en_reg::LOCK_IRQ_EN_R
• spinlock::spinlock_irq_en_reg::LOCK_IRQ_EN_W
• spinlock::spinlock_irq_sta_reg::LOCK_IRQ_STATUS_R
• spinlock::spinlock_irq_sta_reg::LOCK_IRQ_STATUS_W
• spinlock::spinlock_lock_reg::TAKEN_R
• spinlock::spinlock_lock_reg::TAKEN_W
• spinlock::spinlock_status_reg::LOCK_REG_STATUS_R
• spinlock::spinlock_systatus_reg::IU0_R
• spinlock::spinlock_systatus_reg::LOCKS_NUM_R
• sys_cfg::DSP_BOOT_RAMMAP
• sys_cfg::EMAC_EPHY_CLK0
• sys_cfg::RES240_CTRL
• sys_cfg::RESCAL_CTRL
• sys_cfg::RESCAL_STATUS
• sys_cfg::SYS_LDO_CTRL
• sys_cfg::VER
• sys_cfg::dsp_boot_rammap::DSP_BOOT_SRAM_REMAP_ENABLE_R
• sys_cfg::dsp_boot_rammap::DSP_BOOT_SRAM_REMAP_ENABLE_W
• sys_cfg::emac_ephy_clk0::BPS_EFUSE_R
• sys_cfg::emac_ephy_clk0::BPS_EFUSE_W
• sys_cfg::emac_ephy_clk0::CLK_SEL_R
• sys_cfg::emac_ephy_clk0::CLK_SEL_W
• sys_cfg::emac_ephy_clk0::EPHY_MODE_R
• sys_cfg::emac_ephy_clk0::EPHY_MODE_W
• sys_cfg::emac_ephy_clk0::EPIT_R
• sys_cfg::emac_ephy_clk0::EPIT_W
• sys_cfg::emac_ephy_clk0::ERXDC_R
• sys_cfg::emac_ephy_clk0::ERXDC_W
• sys_cfg::emac_ephy_clk0::ERXIE_R
• sys_cfg::emac_ephy_clk0::ERXIE_W
• sys_cfg::emac_ephy_clk0::ETCS_R
• sys_cfg::emac_ephy_clk0::ETCS_W
• sys_cfg::emac_ephy_clk0::ETXDC_R
• sys_cfg::emac_ephy_clk0::ETXDC_W
• sys_cfg::emac_ephy_clk0::ETXIE_R
• sys_cfg::emac_ephy_clk0::ETXIE_W
• sys_cfg::emac_ephy_clk0::LED_POL_R
• sys_cfg::emac_ephy_clk0::LED_POL_W
• sys_cfg::emac_ephy_clk0::PHY_ADDR_R
• sys_cfg::emac_ephy_clk0::PHY_ADDR_W
• sys_cfg::emac_ephy_clk0::PHY_SELECT_R
• sys_cfg::emac_ephy_clk0::PHY_SELECT_W
• sys_cfg::emac_ephy_clk0::RMII_EN_R
• sys_cfg::emac_ephy_clk0::RMII_EN_W
• sys_cfg::emac_ephy_clk0::SHUTDOWN_R
• sys_cfg::emac_ephy_clk0::SHUTDOWN_W
• sys_cfg::emac_ephy_clk0::XMII_SEL_R
• sys_cfg::emac_ephy_clk0::XMII_SEL_W
• sys_cfg::res240_ctrl::DDR_RES240_TRIM_R
• sys_cfg::res240_ctrl::DDR_RES240_TRIM_W
• sys_cfg::rescal_ctrl::CAL_ANA_EN_R
• sys_cfg::rescal_ctrl::CAL_ANA_EN_W
• sys_cfg::rescal_ctrl::CAL_EN_R
• sys_cfg::rescal_ctrl::CAL_EN_W
• sys_cfg::rescal_ctrl::DDR_RES240_TRIMMING_SEL_R
• sys_cfg::rescal_ctrl::DDR_RES240_TRIMMING_SEL_W
• sys_cfg::rescal_ctrl::RESCAL_MODE_R
• sys_cfg::rescal_ctrl::RESCAL_MODE_W
• sys_cfg::rescal_status::COUT_R
• sys_cfg::rescal_status::RES_CAL_DO_R
• sys_cfg::sys_ldo_ctrl::LDOA_TRIM_R
• sys_cfg::sys_ldo_ctrl::LDOA_TRIM_W
• sys_cfg::sys_ldo_ctrl::LDOB_TRIM_R
• sys_cfg::sys_ldo_ctrl::LDOB_TRIM_W
• sys_cfg::sys_ldo_ctrl::SPARE_R
• sys_cfg::sys_ldo_ctrl::SPARE_W
• sys_cfg::ver::BOOT_SEL_PAD_STA_R
• sys_cfg::ver::FEL_SEL_PAD_STA_R
• tcon_lcd0::LCD_3D_FIFO_REG
• tcon_lcd0::LCD_BASIC0_REG
• tcon_lcd0::LCD_BASIC1_REG
• tcon_lcd0::LCD_BASIC2_REG
• tcon_lcd0::LCD_BASIC3_REG
• tcon_lcd0::LCD_CEU_COEF_ADD_REG
• tcon_lcd0::LCD_CEU_COEF_MUL_REG
• tcon_lcd0::LCD_CEU_COEF_RANG_REG
• tcon_lcd0::LCD_CEU_CTL_REG
• tcon_lcd0::LCD_CMAP_CTL_REG
• tcon_lcd0::LCD_CMAP_EVEN0_REG
• tcon_lcd0::LCD_CMAP_EVEN1_REG
• tcon_lcd0::LCD_CMAP_ODD0_REG
• tcon_lcd0::LCD_CMAP_ODD1_REG
• tcon_lcd0::LCD_CPU_IF_REG
• tcon_lcd0::LCD_CPU_RD0_REG
• tcon_lcd0::LCD_CPU_RD1_REG
• tcon_lcd0::LCD_CPU_TRI0_REG
• tcon_lcd0::LCD_CPU_TRI1_REG
• tcon_lcd0::LCD_CPU_TRI2_REG
• tcon_lcd0::LCD_CPU_TRI3_REG
• tcon_lcd0::LCD_CPU_TRI4_REG
• tcon_lcd0::LCD_CPU_TRI5_REG
• tcon_lcd0::LCD_CPU_WR_REG
• tcon_lcd0::LCD_CTL_REG
• tcon_lcd0::LCD_DCLK_REG
• tcon_lcd0::LCD_DEBUG_REG
• tcon_lcd0::LCD_FRM_CTL_REG
• tcon_lcd0::LCD_FRM_SEED_REG
• tcon_lcd0::LCD_FRM_TAB_REG
• tcon_lcd0::LCD_GAMMA_TABLE_REG
• tcon_lcd0::LCD_GCTL_REG
• tcon_lcd0::LCD_GINT0_REG
• tcon_lcd0::LCD_GINT1_REG
• tcon_lcd0::LCD_HV_IF_REG
• tcon_lcd0::LCD_IO_POL_REG
• tcon_lcd0::LCD_IO_TRI_REG
• tcon_lcd0::LCD_LVDS0_ANA_REG
• tcon_lcd0::LCD_LVDS1_ANA_REG
• tcon_lcd0::LCD_LVDS1_IF_REG
• tcon_lcd0::LCD_LVDS_IF_REG
• tcon_lcd0::LCD_SAFE_PERIOD_REG
• tcon_lcd0::LCD_SLAVE_STOP_POS_REG
• tcon_lcd0::LCD_SYNC_CTL_REG
• tcon_lcd0::LCD_SYNC_POS_REG
• tcon_tv0::TV_BASIC0_REG
• tcon_tv0::TV_BASIC1_REG
• tcon_tv0::TV_BASIC2_REG
• tcon_tv0::TV_BASIC3_REG
• tcon_tv0::TV_BASIC4_REG
• tcon_tv0::TV_BASIC5_REG
• tcon_tv0::TV_CEU_COEF_MUL_REG
• tcon_tv0::TV_CEU_COEF_RANG_REG
• tcon_tv0::TV_CEU_CTL_REG
• tcon_tv0::TV_CTL_REG
• tcon_tv0::TV_DATA_IO_POL0_REG
• tcon_tv0::TV_DATA_IO_POL1_REG
• tcon_tv0::TV_DATA_IO_TRI0_REG
• tcon_tv0::TV_DATA_IO_TRI1_REG
• tcon_tv0::TV_DEBUG_REG
• tcon_tv0::TV_FILL_BEGIN_REG
• tcon_tv0::TV_FILL_CTL_REG
• tcon_tv0::TV_FILL_DATA_REG
• tcon_tv0::TV_FILL_END_REG
• tcon_tv0::TV_GCTL_REG
• tcon_tv0::TV_GINT0_REG
• tcon_tv0::TV_GINT1_REG
• tcon_tv0::TV_IO_POL_REG
• tcon_tv0::TV_IO_TRI_REG
• tcon_tv0::TV_PIXELDEPTH_MODE_REG
• tcon_tv0::TV_SAFE_PERIOD_REG
• tcon_tv0::TV_SRC_CTL_REG
• ths::THS_ALARMO_INTS
• ths::THS_ALARM_CTRL
• ths::THS_ALARM_INTC
• ths::THS_ALARM_INTS
• ths::THS_CDATA
• ths::THS_CTRL
• ths::THS_DATA
• ths::THS_DATA_INTC
• ths::THS_DATA_INTS
• ths::THS_EN
• ths::THS_FILTER
• ths::THS_PER
• ths::THS_SHUTDOWN_CTRL
• ths::THS_SHUT_INTC
• ths::THS_SHUT_INTS
• ths::ths_alarm_ctrl::ALARM_T_HOT_R
• ths::ths_alarm_ctrl::ALARM_T_HOT_W
• ths::ths_alarm_ctrl::ALARM_T_HYST_R
• ths::ths_alarm_ctrl::ALARM_T_HYST_W
• ths::ths_alarm_intc::ALARM_INT_EN_R
• ths::ths_alarm_intc::ALARM_INT_EN_W
• ths::ths_alarm_ints::ALARM_INT_STS_R
• ths::ths_alarm_ints::ALARM_INT_STS_W
• ths::ths_alarmo_ints::ALARM_OFF_STS_R
• ths::ths_alarmo_ints::ALARM_OFF_STS_W
• ths::ths_cdata::THS_CDATA_R
• ths::ths_cdata::THS_CDATA_W
• ths::ths_ctrl::TACQ_R
• ths::ths_ctrl::TACQ_W
• ths::ths_data::THS_DATA_R
• ths::ths_data_intc::THS_DATA_IRQ_EN_R
• ths::ths_data_intc::THS_DATA_IRQ_EN_W
• ths::ths_data_ints::THS_DATA_IRQ_STS_R
• ths::ths_data_ints::THS_DATA_IRQ_STS_W
• ths::ths_en::THS_EN_R
• ths::ths_en::THS_EN_W
• ths::ths_filter::FILTER_EN_R
• ths::ths_filter::FILTER_EN_W
• ths::ths_filter::FILTER_TYPE_R
• ths::ths_filter::FILTER_TYPE_W
• ths::ths_per::THERMAL_PER_R
• ths::ths_per::THERMAL_PER_W
• ths::ths_shut_intc::SHUT_INT_EN_R
• ths::ths_shut_intc::SHUT_INT_EN_W
• ths::ths_shut_ints::SHUT_INT_STS_R
• ths::ths_shut_ints::SHUT_INT_STS_W
• ths::ths_shutdown_ctrl::SHUT_T_HOT_R
• ths::ths_shutdown_ctrl::SHUT_T_HOT_W
• timer::AVS_CNT0
• timer::AVS_CNT1
• timer::AVS_CNT_CTL
• timer::AVS_CNT_DIV
• timer::TMR_CTRL
• timer::TMR_CUR_VALUE
• timer::TMR_INTV_VALUE
• timer::TMR_IRQ_EN
• timer::TMR_IRQ_STA
• timer::WDOG_CFG
• timer::WDOG_CTRL
• timer::WDOG_IRQ_EN
• timer::WDOG_IRQ_STA
• timer::WDOG_MODE
• timer::WDOG_OUTPUT_CFG
• timer::WDOG_SOFT_RST
• timer::avs_cnt_ctl::AVS_CNT_EN_R
• timer::avs_cnt_ctl::AVS_CNT_EN_W
• timer::avs_cnt_ctl::AVS_CNT_PS_R
• timer::avs_cnt_ctl::AVS_CNT_PS_W
• timer::avs_cnt_div::AVS_CNT_D_R
• timer::avs_cnt_div::AVS_CNT_D_W
• timer::tmr_ctrl::TMR_CLK_PRES_R
• timer::tmr_ctrl::TMR_CLK_PRES_W
• timer::tmr_ctrl::TMR_CLK_SRC_R
• timer::tmr_ctrl::TMR_CLK_SRC_W
• timer::tmr_ctrl::TMR_EN_R
• timer::tmr_ctrl::TMR_EN_W
• timer::tmr_ctrl::TMR_MODE_R
• timer::tmr_ctrl::TMR_MODE_W
• timer::tmr_ctrl::TMR_RELOAD_R
• timer::tmr_ctrl::TMR_RELOAD_W
• timer::tmr_irq_en::TMR0_IRQ_EN_R
• timer::tmr_irq_en::TMR0_IRQ_EN_W
• timer::tmr_irq_en::TMR1_IRQ_EN_R
• timer::tmr_irq_en::TMR1_IRQ_EN_W
• timer::tmr_irq_sta::TMR0_IRQ_PEND_R
• timer::tmr_irq_sta::TMR0_IRQ_PEND_W
• timer::tmr_irq_sta::TMR1_IRQ_PEND_R
• timer::tmr_irq_sta::TMR1_IRQ_PEND_W
• timer::wdog_cfg::KEY_FIELD_W
• timer::wdog_cfg::WDOG_CLK_SRC_R
• timer::wdog_cfg::WDOG_CLK_SRC_W
• timer::wdog_cfg::WDOG_MODE_R
• timer::wdog_cfg::WDOG_MODE_W
• timer::wdog_ctrl::WDOG_KEY_FIELD_W
• timer::wdog_ctrl::WDOG_RESTART_R
• timer::wdog_ctrl::WDOG_RESTART_W
• timer::wdog_irq_en::WDOG_IRQ_EN_R
• timer::wdog_irq_en::WDOG_IRQ_EN_W
• timer::wdog_irq_sta::WDOG_IRQ_PEND_R
• timer::wdog_irq_sta::WDOG_IRQ_PEND_W
• timer::wdog_mode::KEY_FIELD_W
• timer::wdog_mode::WDOG_EN_R
• timer::wdog_mode::WDOG_EN_W
• timer::wdog_mode::WDOG_INTV_VALUE_R
• timer::wdog_mode::WDOG_INTV_VALUE_W
• timer::wdog_output_cfg::WDOG_OUTPUT_CONFIG_R
• timer::wdog_output_cfg::WDOG_OUTPUT_CONFIG_W
• timer::wdog_soft_rst::KEY_FIELD_W
• timer::wdog_soft_rst::SOFT_RST_EN_R
• timer::wdog_soft_rst::SOFT_RST_EN_W
• tpadc::TP_CALI_DATA
• tpadc::TP_CTRL0
• tpadc::TP_CTRL1
• tpadc::TP_CTRL2
• tpadc::TP_CTRL3
• tpadc::TP_DATA
• tpadc::TP_INT_FIFO_CTRL
• tpadc::TP_INT_FIFO_STAT
• tpadc::tp_cali_data::TP_CDAT_R
• tpadc::tp_cali_data::TP_CDAT_W
• tpadc::tp_ctrl0::ADC_CLK_DIVIDER_R
• tpadc::tp_ctrl0::ADC_CLK_DIVIDER_W
• tpadc::tp_ctrl0::ADC_FIRST_DLY_MODE_R
• tpadc::tp_ctrl0::ADC_FIRST_DLY_MODE_W
• tpadc::tp_ctrl0::ADC_FIRST_DLY_R
• tpadc::tp_ctrl0::ADC_FIRST_DLY_W
• tpadc::tp_ctrl0::FS_DIV_R
• tpadc::tp_ctrl0::FS_DIV_W
• tpadc::tp_ctrl0::TACQ_R
• tpadc::tp_ctrl0::TACQ_W
• tpadc::tp_ctrl1::ADC_CHAN_SELECT_R
• tpadc::tp_ctrl1::ADC_CHAN_SELECT_W
• tpadc::tp_ctrl1::CHOPPER_EN_R
• tpadc::tp_ctrl1::CHOPPER_EN_W
• tpadc::tp_ctrl1::STYLUS_UP_DEBOUNCE_EN_R
• tpadc::tp_ctrl1::STYLUS_UP_DEBOUNCE_EN_W
• tpadc::tp_ctrl1::STYLUS_UP_DEBOUNCE_R
• tpadc::tp_ctrl1::STYLUS_UP_DEBOUNCE_W
• tpadc::tp_ctrl1::TOUCH_PAN_CALI_EN_R
• tpadc::tp_ctrl1::TOUCH_PAN_CALI_EN_W
• tpadc::tp_ctrl1::TP_DUAL_EN_R
• tpadc::tp_ctrl1::TP_DUAL_EN_W
• tpadc::tp_ctrl1::TP_EN_R
• tpadc::tp_ctrl1::TP_EN_W
• tpadc::tp_ctrl1::TP_MODE_SELECT_R
• tpadc::tp_ctrl1::TP_MODE_SELECT_W
• tpadc::tp_ctrl2::PRE_MEA_EN_R
• tpadc::tp_ctrl2::PRE_MEA_EN_W
• tpadc::tp_ctrl2::PRE_MEA_THRE_CNT_R
• tpadc::tp_ctrl2::PRE_MEA_THRE_CNT_W
• tpadc::tp_ctrl2::TP_FIFO_MODE_SELECT_R
• tpadc::tp_ctrl2::TP_FIFO_MODE_SELECT_W
• tpadc::tp_ctrl2::TP_SENSITIVE_ADJUST_R
• tpadc::tp_ctrl2::TP_SENSITIVE_ADJUST_W
• tpadc::tp_ctrl3::FILTER_EN_R
• tpadc::tp_ctrl3::FILTER_EN_W
• tpadc::tp_ctrl3::FILTER_TYPE_R
• tpadc::tp_ctrl3::FILTER_TYPE_W
• tpadc::tp_data::TP_DATA_R
• tpadc::tp_int_fifo_ctrl::TP_DATA_ERQ_EN_R
• tpadc::tp_int_fifo_ctrl::TP_DATA_ERQ_EN_W
• tpadc::tp_int_fifo_ctrl::TP_DATA_IRQ_EN_R
• tpadc::tp_int_fifo_ctrl::TP_DATA_IRQ_EN_W
• tpadc::tp_int_fifo_ctrl::TP_DATA_XY_CHANGE_R
• tpadc::tp_int_fifo_ctrl::TP_DATA_XY_CHANGE_W
• tpadc::tp_int_fifo_ctrl::TP_DOWN_IRQ_EN_R
• tpadc::tp_int_fifo_ctrl::TP_DOWN_IRQ_EN_W
• tpadc::tp_int_fifo_ctrl::TP_FIFO_FLUSH_R
• tpadc::tp_int_fifo_ctrl::TP_FIFO_FLUSH_W
• tpadc::tp_int_fifo_ctrl::TP_FIFO_TRIG_LEVEL_R
• tpadc::tp_int_fifo_ctrl::TP_FIFO_TRIG_LEVEL_W
• tpadc::tp_int_fifo_ctrl::TP_OVERRUN_IRQ_EN_R
• tpadc::tp_int_fifo_ctrl::TP_OVERRUN_IRQ_EN_W
• tpadc::tp_int_fifo_ctrl::TP_UP_IRQ_EN_R
• tpadc::tp_int_fifo_ctrl::TP_UP_IRQ_EN_W
• tpadc::tp_int_fifo_stat::FIFO_DATA_PENDING_R
• tpadc::tp_int_fifo_stat::FIFO_DATA_PENDING_W
• tpadc::tp_int_fifo_stat::FIFO_OVERRUN_PENDING_R
• tpadc::tp_int_fifo_stat::FIFO_OVERRUN_PENDING_W
• tpadc::tp_int_fifo_stat::RXA_CNT_R
• tpadc::tp_int_fifo_stat::TP_DOWN_PENDING_R
• tpadc::tp_int_fifo_stat::TP_DOWN_PENDING_W
• tpadc::tp_int_fifo_stat::TP_IDLE_FLG_R
• tpadc::tp_int_fifo_stat::TP_UP_PENDING_R
• tpadc::tp_int_fifo_stat::TP_UP_PENDING_W
• tvd0::TVD_CLAMP_AGC1
• tvd0::TVD_CLAMP_AGC2
• tvd0::TVD_CLOCK1
• tvd0::TVD_CLOCK2
• tvd0::TVD_DEBUG1
• tvd0::TVD_EN
• tvd0::TVD_ENHANCE1
• tvd0::TVD_ENHANCE2
• tvd0::TVD_ENHANCE3
• tvd0::TVD_HLOCK1
• tvd0::TVD_HLOCK2
• tvd0::TVD_HLOCK3
• tvd0::TVD_HLOCK4
• tvd0::TVD_HLOCK5
• tvd0::TVD_IRQ_CTL
• tvd0::TVD_IRQ_STATUS
• tvd0::TVD_MODE
• tvd0::TVD_STATUS1
• tvd0::TVD_STATUS2
• tvd0::TVD_STATUS3
• tvd0::TVD_STATUS4
• tvd0::TVD_STATUS5
• tvd0::TVD_STATUS6
• tvd0::TVD_VLOCK1
• tvd0::TVD_VLOCK2
• tvd0::TVD_WB1
• tvd0::TVD_WB2
• tvd0::TVD_WB3
• tvd0::TVD_WB4
• tvd0::TVD_YC_SEP1
• tvd0::TVD_YC_SEP2
• tvd_top::TVD_3D_CTL1
• tvd_top::TVD_3D_CTL2
• tvd_top::TVD_3D_CTL3
• tvd_top::TVD_3D_CTL4
• tvd_top::TVD_3D_CTL5
• tvd_top::TVD_ADC_CFG
• tvd_top::TVD_ADC_CTL
• tvd_top::TVD_TOP_CTL
• tvd_top::TVD_TOP_MAP
• tve::TVE_000_REG
• tve::TVE_004_REG
• tve::TVE_008_REG
• tve::TVE_00C_REG
• tve::TVE_010_REG
• tve::TVE_014_REG
• tve::TVE_018_REG
• tve::TVE_01C_REG
• tve::TVE_020_REG
• tve::TVE_024_REG
• tve::TVE_030_REG
• tve::TVE_034_REG
• tve::TVE_038_REG
• tve::TVE_03C_REG
• tve::TVE_0F8_REG
• tve::TVE_0FC_REG
• tve::TVE_100_REG
• tve::TVE_104_REG
• tve::TVE_108_REG
• tve::TVE_10C_REG
• tve::TVE_110_REG
• tve::TVE_114_REG
• tve::TVE_118_REG
• tve::TVE_11C_REG
• tve::TVE_120_REG
• tve::TVE_124_REG
• tve::TVE_128_REG
• tve::TVE_12C_REG
• tve::TVE_130_REG
• tve::TVE_134_REG
• tve::TVE_138_REG
• tve::TVE_13C_REG
• tve::TVE_380_REG
• tve::TVE_384_REG
• tve_top::TVE_DAC_CFG0
• tve_top::TVE_DAC_CFG1
• tve_top::TVE_DAC_CFG2
• tve_top::TVE_DAC_CFG3
• tve_top::TVE_DAC_MAP
• tve_top::TVE_DAC_STATUS
• tve_top::TVE_DAC_TEST
• twi::TWI_ADDR
• twi::TWI_CCR
• twi::TWI_CNTR
• twi::TWI_DATA
• twi::TWI_DRV_BUS_CTRL
• twi::TWI_DRV_CFG
• twi::TWI_DRV_CTRL
• twi::TWI_DRV_DMA_CFG
• twi::TWI_DRV_FIFO_CON
• twi::TWI_DRV_FMT
• twi::TWI_DRV_INT_CTRL
• twi::TWI_DRV_RECV_FIFO_ACC
• twi::TWI_DRV_SEND_FIFO_ACC
• twi::TWI_DRV_SLV
• twi::TWI_EFR
• twi::TWI_LCR
• twi::TWI_SRST
• twi::TWI_STAT
• twi::TWI_XADDR
• twi::twi_addr::GCE_R
• twi::twi_addr::GCE_W
• twi::twi_addr::SLA_R
• twi::twi_addr::SLA_W
• twi::twi_ccr::CLK_DUTY_R
• twi::twi_ccr::CLK_DUTY_W
• twi::twi_ccr::CLK_M_R
• twi::twi_ccr::CLK_M_W
• twi::twi_ccr::CLK_N_R
• twi::twi_ccr::CLK_N_W
• twi::twi_cntr::A_ACK_R
• twi::twi_cntr::A_ACK_W
• twi::twi_cntr::BUS_EN_R
• twi::twi_cntr::BUS_EN_W
• twi::twi_cntr::CLK_COUNT_MODE_R
• twi::twi_cntr::CLK_COUNT_MODE_W
• twi::twi_cntr::INT_EN_R
• twi::twi_cntr::INT_EN_W
• twi::twi_cntr::INT_FLAG_R
• twi::twi_cntr::INT_FLAG_W
• twi::twi_cntr::M_STA_R
• twi::twi_cntr::M_STA_W
• twi::twi_cntr::M_STP_R
• twi::twi_cntr::M_STP_W
• twi::twi_data::DATA_R
• twi::twi_data::DATA_W
• twi::twi_drv_bus_ctrl::CLK_COUNT_MODE_W
• twi::twi_drv_bus_ctrl::CLK_DUTY_R
• twi::twi_drv_bus_ctrl::CLK_DUTY_W
• twi::twi_drv_bus_ctrl::CLK_M_R
• twi::twi_drv_bus_ctrl::CLK_M_W
• twi::twi_drv_bus_ctrl::CLK_N_R
• twi::twi_drv_bus_ctrl::CLK_N_W
• twi::twi_drv_bus_ctrl::SCL_MOE_R
• twi::twi_drv_bus_ctrl::SCL_MOE_W
• twi::twi_drv_bus_ctrl::SCL_MOV_R
• twi::twi_drv_bus_ctrl::SCL_MOV_W
• twi::twi_drv_bus_ctrl::SCL_STA_R
• twi::twi_drv_bus_ctrl::SDA_MOE_R
• twi::twi_drv_bus_ctrl::SDA_MOE_W
• twi::twi_drv_bus_ctrl::SDA_MOV_R
• twi::twi_drv_bus_ctrl::SDA_MOV_W
• twi::twi_drv_bus_ctrl::SDA_STA_R
• twi::twi_drv_cfg::PACKET_CNT_R
• twi::twi_drv_cfg::PACKET_CNT_W
• twi::twi_drv_cfg::PKT_INTERVAL_R
• twi::twi_drv_cfg::PKT_INTERVAL_W
• twi::twi_drv_ctrl::READ_TRAN_MODE_R
• twi::twi_drv_ctrl::READ_TRAN_MODE_W
• twi::twi_drv_ctrl::RESTART_MODE_R
• twi::twi_drv_ctrl::RESTART_MODE_W
• twi::twi_drv_ctrl::SOFT_RESET_R
• twi::twi_drv_ctrl::SOFT_RESET_W
• twi::twi_drv_ctrl::START_TRAN_R
• twi::twi_drv_ctrl::START_TRAN_W
• twi::twi_drv_ctrl::TIMEOUT_N_R
• twi::twi_drv_ctrl::TIMEOUT_N_W
• twi::twi_drv_ctrl::TRAN_RESULT_R
• twi::twi_drv_ctrl::TRAN_RESULT_W
• twi::twi_drv_ctrl::TWI_DRV_EN_R
• twi::twi_drv_ctrl::TWI_DRV_EN_W
• twi::twi_drv_ctrl::TWI_STA_R
• twi::twi_drv_dma_cfg::DMA_RX_EN_R
• twi::twi_drv_dma_cfg::DMA_RX_EN_W
• twi::twi_drv_dma_cfg::DMA_TX_EN_R
• twi::twi_drv_dma_cfg::DMA_TX_EN_W
• twi::twi_drv_dma_cfg::RX_TRIG_R
• twi::twi_drv_dma_cfg::RX_TRIG_W
• twi::twi_drv_dma_cfg::TX_TRIG_R
• twi::twi_drv_dma_cfg::TX_TRIG_W
• twi::twi_drv_fifo_con::RECV_FIFO_CLEAR_R
• twi::twi_drv_fifo_con::RECV_FIFO_CLEAR_W
• twi::twi_drv_fifo_con::RECV_FIFO_CONTENT_R
• twi::twi_drv_fifo_con::RECV_FIFO_CONTENT_W
• twi::twi_drv_fifo_con::SEND_FIFO_CLEAR_R
• twi::twi_drv_fifo_con::SEND_FIFO_CLEAR_W
• twi::twi_drv_fifo_con::SEND_FIFO_CONTENT_R
• twi::twi_drv_fifo_con::SEND_FIFO_CONTENT_W
• twi::twi_drv_fmt::ADDR_BYTE_R
• twi::twi_drv_fmt::ADDR_BYTE_W
• twi::twi_drv_fmt::DATA_BYTE_R
• twi::twi_drv_fmt::DATA_BYTE_W
• twi::twi_drv_int_ctrl::RX_REQ_INT_EN_R
• twi::twi_drv_int_ctrl::RX_REQ_INT_EN_W
• twi::twi_drv_int_ctrl::RX_REQ_PD_R
• twi::twi_drv_int_ctrl::RX_REQ_PD_W
• twi::twi_drv_int_ctrl::TRAN_COM_INT_EN_R
• twi::twi_drv_int_ctrl::TRAN_COM_INT_EN_W
• twi::twi_drv_int_ctrl::TRAN_COM_PD_R
• twi::twi_drv_int_ctrl::TRAN_COM_PD_W
• twi::twi_drv_int_ctrl::TRAN_ERR_INT_EN_R
• twi::twi_drv_int_ctrl::TRAN_ERR_INT_EN_W
• twi::twi_drv_int_ctrl::TRAN_ERR_PD_R
• twi::twi_drv_int_ctrl::TRAN_ERR_PD_W
• twi::twi_drv_int_ctrl::TX_REQ_INT_EN_R
• twi::twi_drv_int_ctrl::TX_REQ_INT_EN_W
• twi::twi_drv_int_ctrl::TX_REQ_PD_R
• twi::twi_drv_int_ctrl::TX_REQ_PD_W
• twi::twi_drv_recv_fifo_acc::RECV_DATA_FIFO_R
• twi::twi_drv_send_fifo_acc::SEND_DATA_FIFO_W
• twi::twi_drv_slv::CMD_R
• twi::twi_drv_slv::CMD_W
• twi::twi_drv_slv::SLV_ID_R
• twi::twi_drv_slv::SLV_ID_W
• twi::twi_drv_slv::SLV_ID_X_R
• twi::twi_drv_slv::SLV_ID_X_W
• twi::twi_efr::DBN_R
• twi::twi_efr::DBN_W
• twi::twi_lcr::SCL_CTL_EN_R
• twi::twi_lcr::SCL_CTL_EN_W
• twi::twi_lcr::SCL_CTL_R
• twi::twi_lcr::SCL_CTL_W
• twi::twi_lcr::SCL_STATE_R
• twi::twi_lcr::SDA_CTL_EN_R
• twi::twi_lcr::SDA_CTL_EN_W
• twi::twi_lcr::SDA_CTL_R
• twi::twi_lcr::SDA_CTL_W
• twi::twi_lcr::SDA_STATE_R
• twi::twi_srst::SOFT_RST_R
• twi::twi_srst::SOFT_RST_W
• twi::twi_stat::STA_R
• twi::twi_xaddr::SLAX_R
• twi::twi_xaddr::SLAX_W
• uart::DBG_DLH
• uart::DBG_DLL
• uart::DLH
• uart::DLL
• uart::DMA_REQ_EN
• uart::FCC
• uart::FCR
• uart::HALT
• uart::HSK
• uart::IER
• uart::IIR
• uart::LCR
• uart::LSR
• uart::MCR
• uart::MSR
• uart::RBR
• uart::RFL
• uart::RXDMA_BL
• uart::RXDMA_CTRL
• uart::RXDMA_DCNT
• uart::RXDMA_IE
• uart::RXDMA_IS
• uart::RXDMA_LMT
• uart::RXDMA_RADDRH
• uart::RXDMA_RADDRL
• uart::RXDMA_SADDRH
• uart::RXDMA_SADDRL
• uart::RXDMA_STA
• uart::RXDMA_STR
• uart::RXDMA_WADDRH
• uart::RXDMA_WADDRL
• uart::SCH
• uart::TFL
• uart::THR
• uart::USR
• uart::dbg_dlh::DBG_DLH_R
• uart::dbg_dll::DBG_DLL_R
• uart::dlh::DLH_R
• uart::dlh::DLH_W
• uart::dll::DLL_R
• uart::dll::DLL_W
• uart::dma_req_en::RX_REQ_ENABLE_R
• uart::dma_req_en::RX_REQ_ENABLE_W
• uart::dma_req_en::TIMEOUT_ENABLE_R
• uart::dma_req_en::TIMEOUT_ENABLE_W
• uart::dma_req_en::TX_REQ_ENABLE_R
• uart::dma_req_en::TX_REQ_ENABLE_W
• uart::fcc::FIFO_DEPTH_R
• uart::fcc::RX_FIFO_CLOCK_ENABLE_R
• uart::fcc::RX_FIFO_CLOCK_ENABLE_W
• uart::fcc::RX_FIFO_CLOCK_MODE_R
• uart::fcc::RX_FIFO_CLOCK_MODE_W
• uart::fcc::TX_FIFO_CLOCK_ENABLE_R
• uart::fcc::TX_FIFO_CLOCK_ENABLE_W
• uart::fcr::DMAM_W
• uart::fcr::FIFOE_W
• uart::fcr::RFIFOR_W
• uart::fcr::RT_W
• uart::fcr::TFT_W
• uart::fcr::XFIFOR_W
• uart::halt::CHANGE_UPDATE_R
• uart::halt::CHANGE_UPDATE_W
• uart::halt::CHCFG_AT_BUSY_R
• uart::halt::CHCFG_AT_BUSY_W
• uart::halt::DMA_PTE_RX_R
• uart::halt::DMA_PTE_RX_W
• uart::halt::HALT_TX_R
• uart::halt::HALT_TX_W
• uart::halt::PTE_R
• uart::halt::PTE_W
• uart::halt::SIR_RX_INVERT_R
• uart::halt::SIR_RX_INVERT_W
• uart::halt::SIR_TX_INVERT_R
• uart::halt::SIR_TX_INVERT_W
• uart::hsk::HSK_R
• uart::hsk::HSK_W
• uart::ier::EDSSI_R
• uart::ier::EDSSI_W
• uart::ier::ELSI_R
• uart::ier::ELSI_W
• uart::ier::ERBFI_R
• uart::ier::ERBFI_W
• uart::ier::ETBEI_R
• uart::ier::ETBEI_W
• uart::ier::PTIME_R
• uart::ier::PTIME_W
• uart::ier::RS485_INT_EN_R
• uart::ier::RS485_INT_EN_W
• uart::iir::FEFLAG_R
• uart::iir::IID_R
• uart::lcr::BC_R
• uart::lcr::BC_W
• uart::lcr::DLAB_R
• uart::lcr::DLAB_W
• uart::lcr::DLS_R
• uart::lcr::DLS_W
• uart::lcr::EPS_R
• uart::lcr::EPS_W
• uart::lcr::PEN_R
• uart::lcr::PEN_W
• uart::lcr::STOP_R
• uart::lcr::STOP_W
• uart::lsr::BI_R
• uart::lsr::DR_R
• uart::lsr::FE_R
• uart::lsr::FIFOERR_R
• uart::lsr::OE_R
• uart::lsr::PE_R
• uart::lsr::TEMT_R
• uart::lsr::THRE_R
• uart::mcr::AFCE_R
• uart::mcr::AFCE_W
• uart::mcr::DTR_R
• uart::mcr::DTR_W
• uart::mcr::FUNCTION_R
• uart::mcr::FUNCTION_W
• uart::mcr::LOOP_R
• uart::mcr::LOOP_W
• uart::mcr::RTS_R
• uart::mcr::RTS_W
• uart::msr::CTS_R
• uart::msr::DCD_R
• uart::msr::DCTS_R
• uart::msr::DDCD_R
• uart::msr::DDSR_R
• uart::msr::DSR_R
• uart::msr::RI_R
• uart::msr::TERI_R
• uart::rbr::RBR_R
• uart::rfl::RFL_R
• uart::rxdma_bl::BUFFER_LENGTH_R
• uart::rxdma_bl::BUFFER_LENGTH_W
• uart::rxdma_ctrl::AHB_BURST_MODE_R
• uart::rxdma_ctrl::AHB_BURST_MODE_W
• uart::rxdma_ctrl::BLK_SIZE_R
• uart::rxdma_ctrl::BLK_SIZE_W
• uart::rxdma_ctrl::ENABLE_R
• uart::rxdma_ctrl::ENABLE_W
• uart::rxdma_ctrl::MODE_R
• uart::rxdma_ctrl::MODE_W
• uart::rxdma_ctrl::TIMEOUT_ENABLE_R
• uart::rxdma_ctrl::TIMEOUT_ENABLE_W
• uart::rxdma_ctrl::TIMEOUT_THRESHOLD_R
• uart::rxdma_ctrl::TIMEOUT_THRESHOLD_W
• uart::rxdma_dcnt::DATA_COUNT_R
• uart::rxdma_dcnt::DATA_COUNT_W
• uart::rxdma_ie::BLK_DONE_R
• uart::rxdma_ie::BLK_DONE_W
• uart::rxdma_ie::BUFFER_OVERRUN_R
• uart::rxdma_ie::BUFFER_OVERRUN_W
• uart::rxdma_ie::LIMIT_DONE_R
• uart::rxdma_ie::LIMIT_DONE_W
• uart::rxdma_ie::TIMEOUT_DONE_R
• uart::rxdma_ie::TIMEOUT_DONE_W
• uart::rxdma_is::BLK_DONE_R
• uart::rxdma_is::BLK_DONE_W
• uart::rxdma_is::BUFFER_OVERRUN_R
• uart::rxdma_is::BUFFER_OVERRUN_W
• uart::rxdma_is::LIMIT_DONE_R
• uart::rxdma_is::LIMIT_DONE_W
• uart::rxdma_is::TIMEOUT_DONE_R
• uart::rxdma_is::TIMEOUT_DONE_W
• uart::rxdma_lmt::LIMIT_SIZE_R
• uart::rxdma_lmt::LIMIT_SIZE_W
• uart::rxdma_raddrh::RADDR_R
• uart::rxdma_raddrh::RADDR_W
• uart::rxdma_saddrh::SADDR_R
• uart::rxdma_saddrh::SADDR_W
• uart::rxdma_sta::BUFFER_READ_ADDRESS_UPDATING_R
• uart::rxdma_sta::BUFFER_READ_ADDRESS_UPDATING_W
• uart::rxdma_sta::BUSY_R
• uart::rxdma_sta::BUSY_W
• uart::rxdma_str::START_R
• uart::rxdma_str::START_W
• uart::rxdma_waddrh::WADDR_R
• uart::sch::SCRATCH_R
• uart::sch::SCRATCH_W
• uart::tfl::TFL_R
• uart::thr::THR_W
• uart::usr::BUSY_R
• uart::usr::RFF_R
• uart::usr::RFNE_R
• uart::usr::TFE_R
• uart::usr::TFNF_R
• usb1::ehci_capability::CAPLENGTH
• usb1::ehci_capability::HCCPARAMS
• usb1::ehci_capability::HCIVERSION
• usb1::ehci_capability::HCSPARAMS
• usb1::ehci_capability::HCSP_PORTROUTE
• usb1::ehci_capability::caplength::CAPLENGTH_R
• usb1::ehci_capability::hccparams::ASYNCHRONOUS_SCHEDULE_PARK_CAPABILITY_R
• usb1::ehci_capability::hccparams::EECP_R
• usb1::ehci_capability::hccparams::ISOCHRONOUS_SCHEDULING_THRESHOLD_R
• usb1::ehci_capability::hccparams::PROGRAMMABLE_FRAME_LIST_FLAG_R
• usb1::ehci_capability::hciversion::HCIVERSION_R
• usb1::ehci_capability::hcsp_portroute::HCSP_PORTROUTE_R
• usb1::ehci_capability::hcsparams::DEBUG_PORT_NUMBER_R
• usb1::ehci_capability::hcsparams::N_CC_R
• usb1::ehci_capability::hcsparams::N_PCC_R
• usb1::ehci_capability::hcsparams::N_PORTS_R
• usb1::ehci_capability::hcsparams::PORT_ROUTING_RULES_R
• usb1::ehci_operational::ASYNCLISTADDR
• usb1::ehci_operational::CONFIGFLAG
• usb1::ehci_operational::CTRLDSSEGMENT
• usb1::ehci_operational::FRINDEX
• usb1::ehci_operational::PERIODICLISTBASE
• usb1::ehci_operational::PORTSC
• usb1::ehci_operational::USBCMD
• usb1::ehci_operational::USBINTR
• usb1::ehci_operational::USBSTS
• usb1::ehci_operational::asynclistaddr::LP_R
• usb1::ehci_operational::asynclistaddr::LP_W
• usb1::ehci_operational::configflag::CF_R
• usb1::ehci_operational::configflag::CF_W
• usb1::ehci_operational::frindex::FRAME_INDEX_R
• usb1::ehci_operational::frindex::FRAME_INDEX_W
• usb1::ehci_operational::periodiclistbase::BASE_ADDRESS_R
• usb1::ehci_operational::periodiclistbase::BASE_ADDRESS_W
• usb1::ehci_operational::portsc::CONNECT_STATUS_CHANGE_R
• usb1::ehci_operational::portsc::CONNECT_STATUS_CHANGE_W
• usb1::ehci_operational::portsc::CURRENT_CONNECT_STATUS_R
• usb1::ehci_operational::portsc::FORCE_PORT_RESUME_R
• usb1::ehci_operational::portsc::FORCE_PORT_RESUME_W
• usb1::ehci_operational::portsc::LINE_STATUS_R
• usb1::ehci_operational::portsc::OVER_CURRENT_ACTIVE_R
• usb1::ehci_operational::portsc::OVER_CURRENT_CHANGE_R
• usb1::ehci_operational::portsc::OVER_CURRENT_CHANGE_W
• usb1::ehci_operational::portsc::PORT_ENABLED_DISABLED_R
• usb1::ehci_operational::portsc::PORT_ENABLED_DISABLED_W
• usb1::ehci_operational::portsc::PORT_ENABLE_DISABLE_CHANGE_R
• usb1::ehci_operational::portsc::PORT_ENABLE_DISABLE_CHANGE_W
• usb1::ehci_operational::portsc::PORT_OWNER_R
• usb1::ehci_operational::portsc::PORT_OWNER_W
• usb1::ehci_operational::portsc::PORT_RESET_R
• usb1::ehci_operational::portsc::PORT_RESET_W
• usb1::ehci_operational::portsc::PORT_TEST_CONTROL_R
• usb1::ehci_operational::portsc::PORT_TEST_CONTROL_W
• usb1::ehci_operational::portsc::SUSPEND_R
• usb1::ehci_operational::portsc::SUSPEND_W
• usb1::ehci_operational::portsc::WKCNNT_E_R
• usb1::ehci_operational::portsc::WKCNNT_E_W
• usb1::ehci_operational::portsc::WKDSCNNT_E_R
• usb1::ehci_operational::portsc::WKDSCNNT_E_W
• usb1::ehci_operational::usbcmd::ASYNCHRONOUS_SCHEDULE_ENABLE_R
• usb1::ehci_operational::usbcmd::ASYNCHRONOUS_SCHEDULE_ENABLE_W
• usb1::ehci_operational::usbcmd::ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNT_R
• usb1::ehci_operational::usbcmd::ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE_R
• usb1::ehci_operational::usbcmd::FRAME_LIST_SIZE_R
• usb1::ehci_operational::usbcmd::FRAME_LIST_SIZE_W
• usb1::ehci_operational::usbcmd::HOST_CONTROLLER_RESET_R
• usb1::ehci_operational::usbcmd::HOST_CONTROLLER_RESET_W
• usb1::ehci_operational::usbcmd::INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_R
• usb1::ehci_operational::usbcmd::INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_W
• usb1::ehci_operational::usbcmd::INTERRUPT_THRESHOLD_CONTROL_R
• usb1::ehci_operational::usbcmd::INTERRUPT_THRESHOLD_CONTROL_W
• usb1::ehci_operational::usbcmd::LIGHT_HOST_CONTROLLER_RESET_R
• usb1::ehci_operational::usbcmd::LIGHT_HOST_CONTROLLER_RESET_W
• usb1::ehci_operational::usbcmd::PERIODIC_SCHEDULE_ENABLE_R
• usb1::ehci_operational::usbcmd::PERIODIC_SCHEDULE_ENABLE_W
• usb1::ehci_operational::usbcmd::RUN_STOP_R
• usb1::ehci_operational::usbcmd::RUN_STOP_W
• usb1::ehci_operational::usbintr::FRAME_LIST_ROLLOVER_ENABLE_R
• usb1::ehci_operational::usbintr::FRAME_LIST_ROLLOVER_ENABLE_W
• usb1::ehci_operational::usbintr::HOST_SYSTEM_ERROR_ENABLE_R
• usb1::ehci_operational::usbintr::HOST_SYSTEM_ERROR_ENABLE_W
• usb1::ehci_operational::usbintr::INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_R
• usb1::ehci_operational::usbintr::INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_W
• usb1::ehci_operational::usbintr::PORT_CHANGE_INTERRUPT_ENABLE_R
• usb1::ehci_operational::usbintr::PORT_CHANGE_INTERRUPT_ENABLE_W
• usb1::ehci_operational::usbintr::USB_ERROR_INTERRUPT_ENABLE_R
• usb1::ehci_operational::usbintr::USB_ERROR_INTERRUPT_ENABLE_W
• usb1::ehci_operational::usbintr::USB_INTERRUPT_ENABLE_R
• usb1::ehci_operational::usbintr::USB_INTERRUPT_ENABLE_W
• usb1::ehci_operational::usbsts::ASYNCHRONOUS_SCHEDULE_STATUS_R
• usb1::ehci_operational::usbsts::FRAME_LIST_ROLLOVER_R
• usb1::ehci_operational::usbsts::FRAME_LIST_ROLLOVER_W
• usb1::ehci_operational::usbsts::HC_HALTED_R
• usb1::ehci_operational::usbsts::HOST_SYSTEM_ERROR_R
• usb1::ehci_operational::usbsts::HOST_SYSTEM_ERROR_W
• usb1::ehci_operational::usbsts::INTERRUPT_ON_ASYNC_ADVANCE_R
• usb1::ehci_operational::usbsts::INTERRUPT_ON_ASYNC_ADVANCE_W
• usb1::ehci_operational::usbsts::PERIODIC_SCHEDULE_STATUS_R
• usb1::ehci_operational::usbsts::PORT_CHANGE_DETECT_R
• usb1::ehci_operational::usbsts::PORT_CHANGE_DETECT_W
• usb1::ehci_operational::usbsts::RECLAMATION_R
• usb1::ehci_operational::usbsts::USBERRINT_R
• usb1::ehci_operational::usbsts::USBERRINT_W
• usb1::ehci_operational::usbsts::USBINT_R
• usb1::ehci_operational::usbsts::USBINT_W
• usb1::hci_controller_phy_interface::HCI_CTRL3
• usb1::hci_controller_phy_interface::HCI_INTERFACE
• usb1::hci_controller_phy_interface::HCI_SIE_PORT_DISABLE_CONTROL
• usb1::hci_controller_phy_interface::PHY_CONTROL
• usb1::hci_controller_phy_interface::PHY_STATUS
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_DETECT_ENABLE_R
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_DETECT_ENABLE_W
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_DETECT_R
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_DETECT_W
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_INTERRUPT_ENABLE_R
• usb1::hci_controller_phy_interface::hci_ctrl3::LINESTATE_CHANGE_INTERRUPT_ENABLE_W
• usb1::hci_controller_phy_interface::hci_ctrl3::REMOTE_WAKEUP_ENABLE_R
• usb1::hci_controller_phy_interface::hci_ctrl3::REMOTE_WAKEUP_ENABLE_W
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_R
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_W
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCR16_ENABLE_R
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCR16_ENABLE_W
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCR8_ENABLE_R
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCR8_ENABLE_W
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_R
• usb1::hci_controller_phy_interface::hci_interface::AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_W
• usb1::hci_controller_phy_interface::hci_interface::DMA_TRANSFER_STATUS_ENABLE_R
• usb1::hci_controller_phy_interface::hci_interface::OHCI_COUNT_SELECT_R
• usb1::hci_controller_phy_interface::hci_interface::OHCI_COUNT_SELECT_W
• usb1::hci_controller_phy_interface::hci_interface::PP2VBUS_R
• usb1::hci_controller_phy_interface::hci_interface::PP2VBUS_W
• usb1::hci_controller_phy_interface::hci_interface::RESUME_K_TO_SE0_TRANSITION_R
• usb1::hci_controller_phy_interface::hci_interface::RESUME_K_TO_SE0_TRANSITION_W
• usb1::hci_controller_phy_interface::hci_interface::ULPI_BYPASS_ENABLE_R
• usb1::hci_controller_phy_interface::hci_interface::ULPI_BYPASS_ENABLE_W
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::PORT_DISABLE_CONTROL_R
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::PORT_DISABLE_CONTROL_W
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::RESUME_SEL_R
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::RESUME_SEL_W
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::SE0_STATUS_R
• usb1::hci_controller_phy_interface::hci_sie_port_disable_control::SE0_STATUS_W
• usb1::hci_controller_phy_interface::phy_control::BIST_EN_A_R
• usb1::hci_controller_phy_interface::phy_control::BIST_EN_A_W
• usb1::hci_controller_phy_interface::phy_control::SIDDQ_R
• usb1::hci_controller_phy_interface::phy_control::SIDDQ_W
• usb1::hci_controller_phy_interface::phy_control::VC_ADDR_R
• usb1::hci_controller_phy_interface::phy_control::VC_ADDR_W
• usb1::hci_controller_phy_interface::phy_control::VC_CLK_R
• usb1::hci_controller_phy_interface::phy_control::VC_CLK_W
• usb1::hci_controller_phy_interface::phy_control::VC_DI_R
• usb1::hci_controller_phy_interface::phy_control::VC_DI_W
• usb1::hci_controller_phy_interface::phy_status::BIST_DONE_R
• usb1::hci_controller_phy_interface::phy_status::BIST_ERROR_R
• usb1::hci_controller_phy_interface::phy_status::VC_DO_R
• usb1::ohci_control_status_partition::HC_COMMAND_STATUS
• usb1::ohci_control_status_partition::HC_CONTROL
• usb1::ohci_control_status_partition::HC_INTERRUPT_DISABLE
• usb1::ohci_control_status_partition::HC_INTERRUPT_ENABLE
• usb1::ohci_control_status_partition::HC_INTERRUPT_STATUS
• usb1::ohci_control_status_partition::hc_command_status::BULKL_LIST_FILLED_R
• usb1::ohci_control_status_partition::hc_command_status::BULKL_LIST_FILLED_W
• usb1::ohci_control_status_partition::hc_command_status::CONTROL_LIST_FILLED_R
• usb1::ohci_control_status_partition::hc_command_status::CONTROL_LIST_FILLED_W
• usb1::ohci_control_status_partition::hc_command_status::HOST_CONTROLLER_RESET_R
• usb1::ohci_control_status_partition::hc_command_status::HOST_CONTROLLER_RESET_W
• usb1::ohci_control_status_partition::hc_command_status::OWERSHIP_CHANGE_REQUEST_R
• usb1::ohci_control_status_partition::hc_command_status::OWERSHIP_CHANGE_REQUEST_W
• usb1::ohci_control_status_partition::hc_command_status::SCHEDULING_OVERRUN_COUNT_R
• usb1::ohci_control_status_partition::hc_control::BULK_LIST_ENABLE_R
• usb1::ohci_control_status_partition::hc_control::BULK_LIST_ENABLE_W
• usb1::ohci_control_status_partition::hc_control::CONTROL_BULK_SERVICE_RATIO_R
• usb1::ohci_control_status_partition::hc_control::CONTROL_BULK_SERVICE_RATIO_W
• usb1::ohci_control_status_partition::hc_control::CONTROL_LIST_ENABLE_R
• usb1::ohci_control_status_partition::hc_control::CONTROL_LIST_ENABLE_W
• usb1::ohci_control_status_partition::hc_control::HOST_CONTROLLER_FUNCTIONAL_STATE_FOR_USB_R
• usb1::ohci_control_status_partition::hc_control::HOST_CONTROLLER_FUNCTIONAL_STATE_FOR_USB_W
• usb1::ohci_control_status_partition::hc_control::INTERRUPT_ROUTING_R
• usb1::ohci_control_status_partition::hc_control::INTERRUPT_ROUTING_W
• usb1::ohci_control_status_partition::hc_control::ISOCHRONOUS_ENABLE_R
• usb1::ohci_control_status_partition::hc_control::ISOCHRONOUS_ENABLE_W
• usb1::ohci_control_status_partition::hc_control::PERIODIC_LIST_ENABLE_R
• usb1::ohci_control_status_partition::hc_control::PERIODIC_LIST_ENABLE_W
• usb1::ohci_control_status_partition::hc_control::REMOTE_WAKEUP_CONNECTED_R
• usb1::ohci_control_status_partition::hc_control::REMOTE_WAKEUP_CONNECTED_W
• usb1::ohci_control_status_partition::hc_control::REMOTE_WAKEUP_ENABLE_R
• usb1::ohci_control_status_partition::hc_control::REMOTE_WAKEUP_ENABLE_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::FRAME_NUMBER_OVERFLOW_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::FRAME_NUMBER_OVERFLOW_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::MASTER_INTERRUPT_DISABLE_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::MASTER_INTERRUPT_DISABLE_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::RESUME_DETECTED_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::RESUME_DETECTED_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::ROOT_HUB_STATUS_CHANGE_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::ROOT_HUB_STATUS_CHANGE_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::SCHEDULING_OVERRUN_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::SCHEDULING_OVERRUN_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::START_OF_FRAME_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::START_OF_FRAME_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::UNRECOVERABLE_ERROR_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::UNRECOVERABLE_ERROR_W
• usb1::ohci_control_status_partition::hc_interrupt_disable::WRITEBACK_DONE_HEAD_R
• usb1::ohci_control_status_partition::hc_interrupt_disable::WRITEBACK_DONE_HEAD_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::FRAME_NUMBER_OVERFLOW_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::FRAME_NUMBER_OVERFLOW_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::MASTER_INTERRUPT_ENABLE_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::MASTER_INTERRUPT_ENABLE_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::RESUME_DETECTED_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::RESUME_DETECTED_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::ROOT_HUB_STATUS_CHANGE_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::ROOT_HUB_STATUS_CHANGE_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::SCHEDULING_OVERRUN_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::SCHEDULING_OVERRUN_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::START_OF_FRAME_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::START_OF_FRAME_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::UNRECOVERABLE_ERROR_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::UNRECOVERABLE_ERROR_W
• usb1::ohci_control_status_partition::hc_interrupt_enable::WRITEBACK_DONE_HEAD_R
• usb1::ohci_control_status_partition::hc_interrupt_enable::WRITEBACK_DONE_HEAD_W
• usb1::ohci_control_status_partition::hc_interrupt_status::FRAME_NUMBER_OVERFLOW_R
• usb1::ohci_control_status_partition::hc_interrupt_status::FRAME_NUMBER_OVERFLOW_W
• usb1::ohci_control_status_partition::hc_interrupt_status::RESUME_DETECTED_R
• usb1::ohci_control_status_partition::hc_interrupt_status::RESUME_DETECTED_W
• usb1::ohci_control_status_partition::hc_interrupt_status::ROOT_HUB_STATUS_CHANGE_R
• usb1::ohci_control_status_partition::hc_interrupt_status::ROOT_HUB_STATUS_CHANGE_W
• usb1::ohci_control_status_partition::hc_interrupt_status::SCHEDULING_OVERRUN_R
• usb1::ohci_control_status_partition::hc_interrupt_status::SCHEDULING_OVERRUN_W
• usb1::ohci_control_status_partition::hc_interrupt_status::START_OF_FRAME_R
• usb1::ohci_control_status_partition::hc_interrupt_status::START_OF_FRAME_W
• usb1::ohci_control_status_partition::hc_interrupt_status::UNRECOVERABLE_ERROR_R
• usb1::ohci_control_status_partition::hc_interrupt_status::UNRECOVERABLE_ERROR_W
• usb1::ohci_control_status_partition::hc_interrupt_status::WRITEBACK_DONE_HEAD_R
• usb1::ohci_control_status_partition::hc_interrupt_status::WRITEBACK_DONE_HEAD_W
• usb1::ohci_frame_counter_partition::HC_FM_INTERVAL
• usb1::ohci_frame_counter_partition::HC_FM_NUMBER
• usb1::ohci_frame_counter_partition::HC_FM_REMAINING
• usb1::ohci_frame_counter_partition::HC_LS_THRESHOLD
• usb1::ohci_frame_counter_partition::HC_PERIODIC_START
• usb1::ohci_frame_counter_partition::hc_fm_interval::FRAME_INTERVAL_R
• usb1::ohci_frame_counter_partition::hc_fm_interval::FRAME_INTERVAL_TOGGLER_R
• usb1::ohci_frame_counter_partition::hc_fm_interval::FRAME_INTERVAL_TOGGLER_W
• usb1::ohci_frame_counter_partition::hc_fm_interval::FRAME_INTERVAL_W
• usb1::ohci_frame_counter_partition::hc_fm_interval::FS_LARGEST_DATA_PACKET_R
• usb1::ohci_frame_counter_partition::hc_fm_interval::FS_LARGEST_DATA_PACKET_W
• usb1::ohci_frame_counter_partition::hc_fm_number::FRAME_NUMBER_R
• usb1::ohci_frame_counter_partition::hc_fm_number::FRAME_NUMBER_W
• usb1::ohci_frame_counter_partition::hc_fm_remaining::FRAME_REMAINING_R
• usb1::ohci_frame_counter_partition::hc_fm_remaining::FRAME_REMAINING_TOGGLE_R
• usb1::ohci_frame_counter_partition::hc_fm_remaining::FRAME_REMAINING_TOGGLE_W
• usb1::ohci_frame_counter_partition::hc_fm_remaining::FRAME_REMAINING_W
• usb1::ohci_frame_counter_partition::hc_ls_threshold::LS_THRESHOLD_R
• usb1::ohci_frame_counter_partition::hc_ls_threshold::LS_THRESHOLD_W
• usb1::ohci_frame_counter_partition::hc_periodic_start::PERIODIC_START_R
• usb1::ohci_frame_counter_partition::hc_periodic_start::PERIODIC_START_W
• usb1::ohci_memory_pointer_partition::HC_BULK_CURRENT_ED
• usb1::ohci_memory_pointer_partition::HC_BULK_HEAD_ED
• usb1::ohci_memory_pointer_partition::HC_CONTROL_CURRENT_ED
• usb1::ohci_memory_pointer_partition::HC_CONTROL_HEAD_ED
• usb1::ohci_memory_pointer_partition::HC_DONE_HEAD
• usb1::ohci_memory_pointer_partition::HC_HCCA
• usb1::ohci_memory_pointer_partition::HC_PERIOD_CURRENT_ED
• usb1::ohci_memory_pointer_partition::hc_bulk_current_ed::BCED_31_4_R
• usb1::ohci_memory_pointer_partition::hc_bulk_current_ed::BCED_31_4_W
• usb1::ohci_memory_pointer_partition::hc_bulk_current_ed::BCED_3_0_R
• usb1::ohci_memory_pointer_partition::hc_bulk_head_ed::BHED_31_4_R
• usb1::ohci_memory_pointer_partition::hc_bulk_head_ed::BHED_31_4_W
• usb1::ohci_memory_pointer_partition::hc_bulk_head_ed::BHED_3_0_R
• usb1::ohci_memory_pointer_partition::hc_control_current_ed::CCED_31_4_R
• usb1::ohci_memory_pointer_partition::hc_control_current_ed::CCED_31_4_W
• usb1::ohci_memory_pointer_partition::hc_control_current_ed::CCED_3_0_R
• usb1::ohci_memory_pointer_partition::hc_control_head_ed::EHCD_31_4_R
• usb1::ohci_memory_pointer_partition::hc_control_head_ed::EHCD_31_4_W
• usb1::ohci_memory_pointer_partition::hc_control_head_ed::EHCD_3_0_R
• usb1::ohci_memory_pointer_partition::hc_done_head::DH_31_4_R
• usb1::ohci_memory_pointer_partition::hc_done_head::DH_31_4_W
• usb1::ohci_memory_pointer_partition::hc_done_head::DH_3_0_R
• usb1::ohci_memory_pointer_partition::hc_hcca::HCCA_31_8_R
• usb1::ohci_memory_pointer_partition::hc_hcca::HCCA_31_8_W
• usb1::ohci_memory_pointer_partition::hc_hcca::HCCA_7_0_R
• usb1::ohci_memory_pointer_partition::hc_period_current_ed::PCED_31_4_R
• usb1::ohci_memory_pointer_partition::hc_period_current_ed::PCED_31_4_W
• usb1::ohci_memory_pointer_partition::hc_period_current_ed::PCED_3_0_R
• usb1::ohci_root_hub_partition::HC_RH_DESCRIPTOR_A
• usb1::ohci_root_hub_partition::HC_RH_DESCRIPTOR_B
• usb1::ohci_root_hub_partition::HC_RH_PORT_STATUS
• usb1::ohci_root_hub_partition::HC_RH_STATUS
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::DEVICE_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::NO_OVER_CURRENT_PROTECTION_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::NO_OVER_CURRENT_PROTECTION_W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::NO_POWER_SWITHCING_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::NO_POWER_SWITHCING_W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::NUMBER_DOWNSTREAM_PORTS_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::OVER_CURRENT_PROTECTION_MODE_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::OVER_CURRENT_PROTECTION_MODE_W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::POWER_ON_TO_POWER_GOOD_TIME_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::POWER_ON_TO_POWER_GOOD_TIME_W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::POWER_SWITCHING_MODE_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_a::POWER_SWITCHING_MODE_W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_b::DEVICE_REMOVABLE_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_b::DEVICE_REMOVABLE_W
• usb1::ohci_root_hub_partition::hc_rh_descriptor_b::PORT_POWER_CONTROL_MASK_R
• usb1::ohci_root_hub_partition::hc_rh_descriptor_b::PORT_POWER_CONTROL_MASK_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::CONNECT_STATUS_CHANGE_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::CONNECT_STATUS_CHANGE_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_ENABLE_STATUS_CHANGE_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_ENABLE_STATUS_CHANGE_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_OVER_CURRENT_INDICATOR_CHANGE_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_OVER_CURRENT_INDICATOR_CHANGE_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_RESET_STATUS_CHANGE_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_RESET_STATUS_CHANGE_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_SUSPEND_STATUS_CHANGE_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::PORT_SUSPEND_STATUS_CHANGE_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_CURRENT_CONNECT_STATUS_W_CLEAR_PORT_ENABLE_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_CURRENT_CONNECT_STATUS_W_CLEAR_PORT_ENABLE_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_LOW_SPEED_DEVICE_ATTACHED_W_CLEAR_PORT_POWER_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_LOW_SPEED_DEVICE_ATTACHED_W_CLEAR_PORT_POWER_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_ENABLE_STATUS_W_SET_PORT_ENABLE_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_ENABLE_STATUS_W_SET_PORT_ENABLE_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_OVER_CURRENT_INDICATOR_W_CLEAR_SUSPEND_STATUS_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_OVER_CURRENT_INDICATOR_W_CLEAR_SUSPEND_STATUS_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_POWER_STATUS_W_SET_PORT_POWER_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_POWER_STATUS_W_SET_PORT_POWER_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_RESET_STATUS_W_SET_PORT_RESET_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_RESET_STATUS_W_SET_PORT_RESET_W
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_SUSPEND_STATUS_W_SET_PORT_SUSPEND_R
• usb1::ohci_root_hub_partition::hc_rh_port_status::R_PORT_SUSPEND_STATUS_W_SET_PORT_SUSPEND_W
• usb1::ohci_root_hub_partition::hc_rh_status::CLEAR_REMOTE_EAKEUP_ENABLE_R
• usb1::ohci_root_hub_partition::hc_rh_status::CLEAR_REMOTE_EAKEUP_ENABLE_W
• usb1::ohci_root_hub_partition::hc_rh_status::OVER_CURRENT_INDICATOR_CHANGE_R
• usb1::ohci_root_hub_partition::hc_rh_status::OVER_CURRENT_INDICATOR_CHANGE_W
• usb1::ohci_root_hub_partition::hc_rh_status::OVER_CURRENT_INDICATOR_R
• usb1::ohci_root_hub_partition::hc_rh_status::OVER_CURRENT_INDICATOR_W
• usb1::ohci_root_hub_partition::hc_rh_status::R_DEVICE_REMOTE_WAKEUP_ENABLE_W_SET_REMOTE_WAKEUP_ENABLE_R
• usb1::ohci_root_hub_partition::hc_rh_status::R_DEVICE_REMOTE_WAKEUP_ENABLE_W_SET_REMOTE_WAKEUP_ENABLE_W
• usb1::ohci_root_hub_partition::hc_rh_status::R_LOCAL_POWER_STATUS_W_CLEAR_GLOBAL_POWER_R
• usb1::ohci_root_hub_partition::hc_rh_status::R_LOCAL_POWER_STATUS_W_CLEAR_GLOBAL_POWER_W
• usb1::ohci_root_hub_partition::hc_rh_status::R_LOCAL_POWER_STATUS_W_SET_GLOBAL_POWER_R
• usb1::ohci_root_hub_partition::hc_rh_status::R_LOCAL_POWER_STATUS_W_SET_GLOBAL_POWER_W