Module qn908x_rs::spi0
[−]
[src]
spi
Modules
cfg |
SPI Configuration register |
div |
SPI clock Divider |
dly |
SPI Delay register |
fifocfg |
FIFO configuration and enable register. |
fifointenclr |
FIFO interrupt enable clear (disable) and read register. |
fifointenset |
FIFO interrupt enable set (enable) and read register. |
fifointstat |
FIFO interrupt status register. |
fiford |
FIFO read data. |
fifordnopop |
FIFO data read with no FIFO pop. |
fifostat |
FIFO status register. |
fifotrig |
FIFO trigger settings for interrupt and DMA request. |
fifowr |
FIFO write data. |
id |
SPI module Identification. This value appears in the shared Flexcomm peripheral ID register when SPI is selected. |
intenclr |
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. |
intenset |
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. |
intstat |
SPI Interrupt Status |
stat |
SPI Status. Some status flags can be cleared by writing a 1 to that bit position. |
Structs
CFG |
SPI Configuration register |
DIV |
SPI clock Divider |
DLY |
SPI Delay register |
FIFOCFG |
FIFO configuration and enable register. |
FIFOINTENCLR |
FIFO interrupt enable clear (disable) and read register. |
FIFOINTENSET |
FIFO interrupt enable set (enable) and read register. |
FIFOINTSTAT |
FIFO interrupt status register. |
FIFORD |
FIFO read data. |
FIFORDNOPOP |
FIFO data read with no FIFO pop. |
FIFOSTAT |
FIFO status register. |
FIFOTRIG |
FIFO trigger settings for interrupt and DMA request. |
FIFOWR |
FIFO write data. |
ID |
SPI module Identification. This value appears in the shared Flexcomm peripheral ID register when SPI is selected. |
INTENCLR |
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. |
INTENSET |
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. |
INTSTAT |
SPI Interrupt Status |
RegisterBlock |
Register block |
STAT |
SPI Status. Some status flags can be cleared by writing a 1 to that bit position. |