Module qn908x_rs::bledp
[−]
[src]
bledp
Modules
| access_address |
access address register |
| ant_pdu_data0 |
pdu data 0 to 1 byte, and preamble register |
| ant_pdu_data1 |
pdu data 2 to 5 byte |
| ant_pdu_data2 |
pdu data 6 to 9 byte |
| ant_pdu_data3 |
pdu data 10 to 13 byte |
| ant_pdu_data4 |
pdu data 14 to 17 byte |
| ant_pdu_data5 |
pdu data 18 to 21 byte |
| ant_pdu_data6 |
pdu data 22 to 25 byte |
| ant_pdu_data7 |
pdu data 26 to 29 byte |
| antenna_map01 |
antenna switch map register 0 |
| antenna_map23 |
antenna switch map register 1 |
| antenna_map45 |
antenna switch map register 2 |
| antenna_map67 |
antenna switch map register 3 |
| ble_dp_status1 |
datapath status register 1 |
| ble_dp_status2 |
datapath status register 2 |
| ble_dp_status3 |
datapath status register 3 |
| ble_dp_status4 |
datapath status register 4 |
| crcseed |
crc seed |
| df_antenna_ctrl |
antenna register |
| dp_aa_error_ctrl |
AA error control register |
| dp_aa_error_th |
AA error threshold register |
| dp_function_ctrl |
datapath function control register |
| dp_int |
data path interrupt register |
| dp_test_ctrl |
datapath test iinterface register |
| dp_top_system_ctrl |
datapath system control register |
| freq_domain_ctrl1 |
frequency domain control register 1 |
| freq_domain_ctrl2 |
frequency domain control register 2 |
| freq_domain_ctrl3 |
frequency domain control register 3 |
| freq_domain_ctrl4 |
frequency domain control register 4 |
| freq_domain_ctrl5 |
frequency domain control register 5 |
| freq_domain_ctrl6 |
frequency domain control register 5 |
| freq_domain_status1 |
frequency domain status register 1 |
| freq_domain_status2 |
frequency domain status register 2 |
| hp_mode_ctrl1 |
when high hp mode training size same as cfo tracking. |
| hp_mode_ctrl2 |
q paramter in training period of phase offset iir of bmc |
| prop_mode_ctrl |
properity mode control register |
| rx_front_end_ctrl1 |
rx front end control register 1 |
| rx_front_end_ctrl2 |
rx front end control register 2 |
Structs
| ACCESS_ADDRESS |
access address register |
| ANTENNA_MAP01 |
antenna switch map register 0 |
| ANTENNA_MAP23 |
antenna switch map register 1 |
| ANTENNA_MAP45 |
antenna switch map register 2 |
| ANTENNA_MAP67 |
antenna switch map register 3 |
| ANT_PDU_DATA0 |
pdu data 0 to 1 byte, and preamble register |
| ANT_PDU_DATA1 |
pdu data 2 to 5 byte |
| ANT_PDU_DATA2 |
pdu data 6 to 9 byte |
| ANT_PDU_DATA3 |
pdu data 10 to 13 byte |
| ANT_PDU_DATA4 |
pdu data 14 to 17 byte |
| ANT_PDU_DATA5 |
pdu data 18 to 21 byte |
| ANT_PDU_DATA6 |
pdu data 22 to 25 byte |
| ANT_PDU_DATA7 |
pdu data 26 to 29 byte |
| BLE_DP_STATUS1 |
datapath status register 1 |
| BLE_DP_STATUS2 |
datapath status register 2 |
| BLE_DP_STATUS3 |
datapath status register 3 |
| BLE_DP_STATUS4 |
datapath status register 4 |
| CRCSEED |
crc seed |
| DF_ANTENNA_CTRL |
antenna register |
| DP_AA_ERROR_CTRL |
AA error control register |
| DP_AA_ERROR_TH |
AA error threshold register |
| DP_FUNCTION_CTRL |
datapath function control register |
| DP_INT |
data path interrupt register |
| DP_TEST_CTRL |
datapath test iinterface register |
| DP_TOP_SYSTEM_CTRL |
datapath system control register |
| FREQ_DOMAIN_CTRL1 |
frequency domain control register 1 |
| FREQ_DOMAIN_CTRL2 |
frequency domain control register 2 |
| FREQ_DOMAIN_CTRL3 |
frequency domain control register 3 |
| FREQ_DOMAIN_CTRL4 |
frequency domain control register 4 |
| FREQ_DOMAIN_CTRL5 |
frequency domain control register 5 |
| FREQ_DOMAIN_CTRL6 |
frequency domain control register 5 |
| FREQ_DOMAIN_STATUS1 |
frequency domain status register 1 |
| FREQ_DOMAIN_STATUS2 |
frequency domain status register 2 |
| HP_MODE_CTRL1 |
when high hp mode training size same as cfo tracking. |
| HP_MODE_CTRL2 |
q paramter in training period of phase offset iir of bmc |
| PROP_MODE_CTRL |
properity mode control register |
| RX_FRONT_END_CTRL1 |
rx front end control register 1 |
| RX_FRONT_END_CTRL2 |
rx front end control register 2 |
| RegisterBlock |
Register block |