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use std::sync::Arc;
use super::{ArmDebugSequence, ArmDebugSequenceError};
use crate::architecture::arm::{
ap::MemoryAp, component::TraceSink, memory::CoresightComponent, ApAddress, ArmError,
ArmProbeInterface, DpAddress,
};
use crate::session::MissingPermissions;
#[derive(thiserror::Error, Debug)]
pub enum ComponentError {
#[error("Nordic does not support TPIU CLK value of {0}")]
NordicUnsupportedTPUICLKValue(u32),
#[error("nRF52 devices do not have a trace buffer")]
NordicNoTraceMem,
}
const RESET: u8 = 0x00;
const ERASEALL: u8 = 0x04;
const ERASEALLSTATUS: u8 = 0x08;
const APPROTECTSTATUS: u8 = 0x0C;
pub struct Nrf52 {}
impl Nrf52 {
pub fn create() -> Arc<Self> {
Arc::new(Self {})
}
fn is_core_unlocked(
&self,
iface: &mut dyn ArmProbeInterface,
ctrl_ap: ApAddress,
) -> Result<bool, ArmError> {
let status = iface.read_raw_ap_register(ctrl_ap, APPROTECTSTATUS)?;
Ok(status != 0)
}
}
mod clock {
use crate::architecture::arm::{memory::adi_v5_memory_interface::ArmProbe, ArmError};
use bitfield::bitfield;
const CLOCK: u64 = 0x4000_0000;
bitfield! {
pub struct TraceConfig(u32);
impl Debug;
pub u8, traceportspeed, set_traceportspeed: 1, 0;
pub u8, tracemux, set_tracemux: 17, 16;
}
impl TraceConfig {
const ADDRESS: u64 = 0x55C;
pub fn read(memory: &mut dyn ArmProbe) -> Result<Self, ArmError> {
let contents = memory.read_word_32(CLOCK + Self::ADDRESS)?;
Ok(Self(contents))
}
pub fn write(&mut self, memory: &mut dyn ArmProbe) -> Result<(), ArmError> {
memory.write_word_32(CLOCK + Self::ADDRESS, self.0)
}
}
}
impl ArmDebugSequence for Nrf52 {
fn debug_device_unlock(
&self,
iface: &mut dyn ArmProbeInterface,
_default_ap: MemoryAp,
permissions: &crate::Permissions,
) -> Result<(), ArmError> {
let ctrl_ap = ApAddress {
ap: 1,
dp: DpAddress::Default,
};
tracing::info!("Checking if core is unlocked");
if self.is_core_unlocked(iface, ctrl_ap)? {
tracing::info!("Core is already unlocked");
return Ok(());
}
tracing::warn!("Core is locked. Erase procedure will be started to unlock it.");
permissions
.erase_all()
.map_err(|MissingPermissions(desc)| ArmError::MissingPermissions(desc))?;
iface.write_raw_ap_register(ctrl_ap, RESET, 1)?;
iface.write_raw_ap_register(ctrl_ap, RESET, 0)?;
iface.write_raw_ap_register(ctrl_ap, ERASEALL, 1)?;
while iface.read_raw_ap_register(ctrl_ap, ERASEALLSTATUS)? != 0 {}
iface.write_raw_ap_register(ctrl_ap, RESET, 1)?;
iface.write_raw_ap_register(ctrl_ap, RESET, 0)?;
if !self.is_core_unlocked(iface, ctrl_ap)? {
return Err(ArmDebugSequenceError::custom("Could not unlock core").into());
}
Err(ArmError::ReAttachRequired)
}
fn trace_start(
&self,
interface: &mut dyn ArmProbeInterface,
components: &[CoresightComponent],
sink: &TraceSink,
) -> Result<(), ArmError> {
let tpiu_clock = match sink {
TraceSink::TraceMemory => {
tracing::error!("nRF52 does not have a trace buffer");
return Err(ArmError::from(ComponentError::NordicNoTraceMem));
}
TraceSink::Tpiu(config) => config.tpiu_clk(),
TraceSink::Swo(config) => config.tpiu_clk(),
};
let portspeed = match tpiu_clock {
4_000_000 => 3,
8_000_000 => 2,
16_000_000 => 1,
32_000_000 => 0,
tpiu_clk => {
let e = ComponentError::NordicUnsupportedTPUICLKValue(tpiu_clk);
tracing::error!("{:?}", e);
return Err(ArmError::from(e));
}
};
let mut memory = interface.memory_interface(components[0].ap)?;
let mut config = clock::TraceConfig::read(&mut *memory)?;
config.set_traceportspeed(portspeed);
if matches!(sink, TraceSink::Tpiu(_)) {
config.set_tracemux(2);
} else {
config.set_tracemux(1);
}
config.write(&mut *memory)?;
Ok(())
}
}
impl From<ComponentError> for ArmError {
fn from(value: ComponentError) -> ArmError {
ArmError::DebugSequence(ArmDebugSequenceError::custom(value))
}
}