Expand description
§Debugging toolset for embedded devices
§Prerequisites
- Udev rules
§Examples
§Halting the attached chip
use probe_rs::probe::{list::Lister, Probe};
use probe_rs::Permissions;
// Get a list of all available debug probes.
let lister = Lister::new();
let probes = lister.list_all();
// Use the first probe found.
let mut probe = probes[0].open()?;
// Attach to a chip.
let mut session = probe.attach("nrf52", Permissions::default())?;
// Select a core.
let mut core = session.core(0)?;
// Halt the attached core.
core.halt(std::time::Duration::from_millis(10))?;
§Reading from RAM
use probe_rs::{Session, SessionConfig, MemoryInterface};
let session_config = SessionConfig::default();
let mut session = Session::auto_attach("nrf52", session_config)?;
let mut core = session.core(0)?;
// Read a block of 50 32 bit words.
let mut buff = [0u32;50];
core.read_32(0x2000_0000, &mut buff)?;
// Read a single 32 bit word.
let word = core.read_word_32(0x2000_0000)?;
// Writing is just as simple.
let buff = [0u32;50];
core.write_32(0x2000_0000, &buff)?;
// of course we can also write 8bit words.
let buff = [0u8;50];
core.write_8(0x2000_0000, &buff)?;
probe-rs is built around 4 main interfaces: the Probe, Target, Session and Core structs.
Re-exports§
pub use crate::config::Target;
Modules§
- architecture
- All the interface bits for the different architectures.
- config
- Target specific configuration
- flashing
- Flash programming operations.
- integration
- Helper functions for integration tests in your application using probe-rs.
- probe
- Probe drivers
- rtt
- Host side implementation of the RTT (Real-Time Transfer) I/O protocol over probe-rs
- semihosting
- ARM semihosting support.
- vendor
- Vendor support modules.
Macros§
- define_
dp_ register - Defines a new debug port register for typed access.
- memory_
mapped_ bitfield_ register - Create a
MemoryMappedRegister
type, with the required method implementations for:
Structs§
- Core
- Generic core handle representing a physical core on an MCU.
- Core
Dump - A snapshot representation of a core state.
- Core
Information - An struct for storing the current state of a core.
- Core
Register - Describes a core (or CPU / hardware) register with its properties.
Each architecture will have a set of general purpose registers, and potentially some special purpose registers. It also happens that some general purpose registers can be used for special purposes. For instance, some ARM variants allows the
LR
(link register / return address) to be used as general purpose registerR14
.“ - Core
Registers - A static array of all the registers (
CoreRegister
) that apply to a specific architecture. - Core
State - A generic core state which caches the generic parts of the core state.
- Permissions
- The
Permissions
struct represents what a Session is allowed to do with a target. Some operations can be irreversible, so need to be explicitly allowed by the user. - Register
Id - The location of a CPU \register. This is not an actual memory address, but a core specific location that represents a specific core register.
- Session
- The
Session
struct represents an active debug session. - Session
Config - The
SessionConfig
struct is used to configure a newSession
during auto-attach.
Enums§
- Architecture
- The architecture family of a specific
CoreType
. - Breakpoint
Cause - When the core halts due to a breakpoint request, some architectures will allow us to distinguish between a software and hardware breakpoint.
- Core
Dump Error - The overarching error type which contains all possible errors as variants.
- Core
Status - The status of the core.
- Core
Type - Type of a supported core.
- Endian
- The current endianness of a core
- Error
- The overarching error type which contains all possible errors as variants.
- Halt
Reason - The reason why a core was halted.
- Instruction
Set - Instruction set used by a core
- Register
Data Type - The type of data stored in a register, with size in bits encapsulated in the enum.
- Register
Role - This is used to label the register with a specific role that it plays during program execution and exception handling.
This denotes the purpose of a register (e.g.
return address
), while theCoreRegister::name
will contain the architecture specific label of the register. - Register
Value - A value of a core register
- Specific
Core State - The architecture specific core state.
- Unwind
Rule - The rule used to preserve the value of a register between function calls during unwinding, when DWARF unwind information is not available.
- Vector
Catch Condition - When a core hits an exception, we halt the core.
Traits§
- Core
Interface - A generic interface to control a MCU core.
- Memory
Interface - An interface to be implemented for drivers that allow target memory access.
- Memory
Mapped Register - A memory mapped register, for instance ARM debug registers (DHCSR, etc).