[−][src]Module open_vaf::hir
Structs
| BranchDeclaration | |
| Condition | |
| Discipline | |
| Function | |
| FunctionArg | |
| Hir | An High level (tree) IR representing a Verilog-AMS project; It provides stable indicies for every Node because the entire Tree is immutable once created; It uses preallocated constant size arrays for better performance Compared to an AST all references are resolved to their respective ids here and unnecessary constructs like blocks are ignored |
| Module | |
| Nature | |
| Net | |
| Port | |
| WhileLoop |
Enums
| Branch | |
| DisciplineAccess | |
| Expression | |
| Primary | |
| Statement |
Type Definitions
| Block |