[−][src]Module open_vaf::ast_lowering

This module is responsible for lowering an Ast to an Hir

The main transformations in this module are

Name resolution - Names (such as variable references) are resolved to declarations. It is enforced that the resolved declarations are the right type of Hir node (no type checking that happens during hir_lowering. Ids of the resolved declarations are then stored in the HIR inplace of identifiers in the AST
Branch resolution - Unnamed branches ( accessed using for example using <nature>(<net1>,<net2>) ) are created as needed and tracked so that the same unnamed branch isn't created multiple times. Furthermore it is enforced that disciplines of the nets defining a branch are comparable and that branches are only accessed using the flow/potential Nature of those disciplines
Context based information - Some expressions and statements are not allowed in some places (for example in an analog/digital context). During the fold these (states)[ast_to_hir_fold::VerilogContext) are tracked and errors are generated when an illegal expressions/statements is used

The lowering process happens in a series of folds implemented in the ast_to_hir_fold module

Re-exports

pub use ast_to_hir_fold::Fold;

Handles branch resolution which is more complicated because unnamed branches exist and discipline comparability has to be enforced