Struct nucleo_f042k6::exti::emr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register

pub fn mr0(&mut self) -> _MR0W

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> _MR1W

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> _MR2W

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> _MR3W

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> _MR4W

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> _MR5W

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> _MR6W

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> _MR7W

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> _MR8W

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> _MR9W

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> _MR10W

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> _MR11W

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> _MR12W

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> _MR13W

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> _MR14W

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> _MR15W

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> _MR16W

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> _MR17W

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> _MR18W

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> _MR19W

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> _MR20W

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> _MR21W

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> _MR22W

Bit 22 - Event Mask on line 22

pub fn mr23(&mut self) -> _MR23W

Bit 23 - Event Mask on line 23

pub fn mr24(&mut self) -> _MR24W

Bit 24 - Event Mask on line 24

pub fn mr25(&mut self) -> _MR25W

Bit 25 - Event Mask on line 25

pub fn mr26(&mut self) -> _MR26W

Bit 26 - Event Mask on line 26

pub fn mr27(&mut self) -> _MR27W

Bit 27 - Event Mask on line 27