Module nrf91::uarte0_ns

source ·
Expand description

UART with EasyDMA 0

Modules

baudrate
Baud rate. Accuracy depends on the HFCLK source selected.
config
Configuration of parity and hardware flow control
enable
Enable UART
errorsrc
Error source Note : this register is read / write one to clear.
events_cts
CTS is activated (set low). Clear To Send.
events_endrx
Receive buffer is filled up
events_endtx
Last TX byte transmitted
events_error
Error detected
events_ncts
CTS is deactivated (set high). Not Clear To Send.
events_rxdrdy
Data received in RXD (but potentially not yet transferred to Data RAM)
events_rxstarted
UART receiver has started
events_rxto
Receiver timeout
events_txdrdy
Data sent from TXD
events_txstarted
UART transmitter has started
events_txstopped
Transmitter stopped
inten
Enable or disable interrupt
intenclr
Disable interrupt
intenset
Enable interrupt
psel
Register block Unspecified
publish_cts
Publish configuration for event CTS
publish_endrx
Publish configuration for event ENDRX
publish_endtx
Publish configuration for event ENDTX
publish_error
Publish configuration for event ERROR
publish_ncts
Publish configuration for event NCTS
publish_rxdrdy
Publish configuration for event RXDRDY
publish_rxstarted
Publish configuration for event RXSTARTED
publish_rxto
Publish configuration for event RXTO
publish_txdrdy
Publish configuration for event TXDRDY
publish_txstarted
Publish configuration for event TXSTARTED
publish_txstopped
Publish configuration for event TXSTOPPED
rxd
Register block RXD EasyDMA channel
shorts
Shortcuts between local events and tasks
subscribe_flushrx
Subscribe configuration for task FLUSHRX
subscribe_startrx
Subscribe configuration for task STARTRX
subscribe_starttx
Subscribe configuration for task STARTTX
subscribe_stoprx
Subscribe configuration for task STOPRX
subscribe_stoptx
Subscribe configuration for task STOPTX
tasks_flushrx
Flush RX FIFO into RX buffer
tasks_startrx
Start UART receiver
tasks_starttx
Start UART transmitter
tasks_stoprx
Stop UART receiver
tasks_stoptx
Stop UART transmitter
txd
Register block TXD EasyDMA channel

Structs

BAUDRATE
Baud rate. Accuracy depends on the HFCLK source selected.
CONFIG
Configuration of parity and hardware flow control
ENABLE
Enable UART
ERRORSRC
Error source Note : this register is read / write one to clear.
EVENTS_CTS
CTS is activated (set low). Clear To Send.
EVENTS_ENDRX
Receive buffer is filled up
EVENTS_ENDTX
Last TX byte transmitted
EVENTS_ERROR
Error detected
EVENTS_NCTS
CTS is deactivated (set high). Not Clear To Send.
EVENTS_RXDRDY
Data received in RXD (but potentially not yet transferred to Data RAM)
EVENTS_RXSTARTED
UART receiver has started
EVENTS_RXTO
Receiver timeout
EVENTS_TXDRDY
Data sent from TXD
EVENTS_TXSTARTED
UART transmitter has started
EVENTS_TXSTOPPED
Transmitter stopped
INTEN
Enable or disable interrupt
INTENCLR
Disable interrupt
INTENSET
Enable interrupt
PSEL
Register block
PUBLISH_CTS
Publish configuration for event CTS
PUBLISH_ENDRX
Publish configuration for event ENDRX
PUBLISH_ENDTX
Publish configuration for event ENDTX
PUBLISH_ERROR
Publish configuration for event ERROR
PUBLISH_NCTS
Publish configuration for event NCTS
PUBLISH_RXDRDY
Publish configuration for event RXDRDY
PUBLISH_RXSTARTED
Publish configuration for event RXSTARTED
PUBLISH_RXTO
Publish configuration for event RXTO
PUBLISH_TXDRDY
Publish configuration for event TXDRDY
PUBLISH_TXSTARTED
Publish configuration for event TXSTARTED
PUBLISH_TXSTOPPED
Publish configuration for event TXSTOPPED
RXD
Register block
RegisterBlock
Register block
SHORTS
Shortcuts between local events and tasks
SUBSCRIBE_FLUSHRX
Subscribe configuration for task FLUSHRX
SUBSCRIBE_STARTRX
Subscribe configuration for task STARTRX
SUBSCRIBE_STARTTX
Subscribe configuration for task STARTTX
SUBSCRIBE_STOPRX
Subscribe configuration for task STOPRX
SUBSCRIBE_STOPTX
Subscribe configuration for task STOPTX
TASKS_FLUSHRX
Flush RX FIFO into RX buffer
TASKS_STARTRX
Start UART receiver
TASKS_STARTTX
Start UART transmitter
TASKS_STOPRX
Stop UART receiver
TASKS_STOPTX
Stop UART transmitter
TXD
Register block